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brw: Fix and properly use increment_a64_address()

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Since the move to MEMORY_*_LOGICAL the result value was being ignored, so
change to use that.

Since the conversion to use new registers, some issues were introduced:
- Even with `has_64bit_int` ADD with 64-bit immediate value is not supported;
- `dst_high` was not being filled if there was no overflow;
- Only `dst_low` returned.

Found when writing some new code involving large block loads.

Fixes: b79e85a93f ("brw: always use new registers for load address increments")
Fixes: b55f77161d ("intel/brw: Switch to emitting MEMORY_*_LOGICAL opcodes")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit b542ac4ca0)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39462>
This commit is contained in:
Caio Oliveira 2026-01-12 23:17:32 -08:00 • committed by Dylan Baker
parent 3f3b7e4aa3
commit aac49e31f1
2 changed files with 8 additions and 6 deletions
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2
.pick_status.json
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@ -624,7 +624,7 @@
"description": "brw: Fix and properly use increment_a64_address()",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "b79e85a93f961c6396f74e63f851d9579960e8ef",
"notes": null

12
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -5067,7 +5067,7 @@ increment_a64_address(const brw_builder &_bld, brw_reg address, uint32_t v, bool
const brw_builder bld = use_no_mask ? _bld.exec_all().group(8, 0) : _bld;
if (bld.shader->devinfo->has_64bit_int) {
return bld.ADD(address, brw_imm_int(address.type, v));
return bld.ADD(retype(address, BRW_TYPE_UQ), brw_imm_ud(v));
} else {
brw_reg dst = bld.vgrf(BRW_TYPE_UQ);
brw_reg dst_low = subscript(dst, BRW_TYPE_UD, 0);
@ -5077,8 +5077,9 @@ increment_a64_address(const brw_builder &_bld, brw_reg address, uint32_t v, bool
/* Add low and if that overflows, add carry to high. */
bld.ADD(dst_low, src_low, brw_imm_ud(v))->conditional_mod = BRW_CONDITIONAL_O;
bld.ADD(dst_high, src_high, brw_imm_ud(0x1))->predicate = BRW_PREDICATE_NORMAL;
return dst_low;
bld.MOV(dst_high, src_high);
bld.ADD(dst_high, dst_high, brw_imm_ud(0x1))->predicate = BRW_PREDICATE_NORMAL;
return dst;
}
}
@ -7334,8 +7335,9 @@ brw_from_nir_emit_memory_access(nir_to_brw_state &ntb,
mem->flags = flags;
if (brw_type_size_bits(srcs[MEMORY_LOGICAL_ADDRESS].type) == 64) {
increment_a64_address(ubld, srcs[MEMORY_LOGICAL_ADDRESS],
block_bytes, no_mask_handle);
srcs[MEMORY_LOGICAL_ADDRESS] =
increment_a64_address(ubld, srcs[MEMORY_LOGICAL_ADDRESS],
block_bytes, no_mask_handle);
} else {
srcs[MEMORY_LOGICAL_ADDRESS] =
ubld.ADD(retype(srcs[MEMORY_LOGICAL_ADDRESS], BRW_TYPE_UD),