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radeonsi: pass radeon_cmdbuf to emit_cache_flush

Browse source 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2020-12-08 10:57:45 +01:00
parent 7f9a084e7e
commit aa9fe1e423
9 changed files with 19 additions and 22 deletions
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2
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -886,7 +886,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
/* Registers that are not read from memory should be set before this: */
if (sctx->flags)
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
sctx->atoms.s.render_cond.emit(sctx);

2
src/gallium/drivers/radeonsi/si_cp_dma.c
View file

@ -179,7 +179,7 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
* Also wait for the previous CP DMA operations.
*/
if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->flags)
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first && !(*packet_flags & CP_DMA_CLEAR))
*packet_flags |= CP_DMA_RAW_WAIT;

2
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -1723,7 +1723,7 @@ static void si_upload_bindless_descriptors(struct si_context *sctx)
* descriptors directly in memory, in case the GPU is using them.
*/
sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
unsigned desc_slot = (*tex_handle)->desc_slot;

2
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -146,7 +146,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
/* Wait for draw calls to finish if needed. */
if (wait_flags) {
ctx->flags |= wait_flags;
ctx->emit_cache_flush(ctx);
ctx->emit_cache_flush(ctx, &ctx->gfx_cs);
}
ctx->gfx_last_ib_is_busy = (wait_flags & wait_ps_cs) != wait_ps_cs;

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -934,7 +934,7 @@ struct si_context {
void *sh_query_result_shader;
struct si_resource *shadowed_regs;
void (*emit_cache_flush)(struct si_context *ctx);
void (*emit_cache_flush)(struct si_context *ctx, struct radeon_cmdbuf *cs);
struct blitter_context *blitter;
void *noop_blend;

4
src/gallium/drivers/radeonsi/si_state.h
View file

@ -592,8 +592,8 @@ bool si_update_ngg(struct si_context *sctx);
void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
unsigned cp_coher_cntl);
void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx);
void gfx10_emit_cache_flush(struct si_context *sctx);
void si_emit_cache_flush(struct si_context *sctx);
void gfx10_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
void si_trace_emit(struct si_context *sctx);
void si_init_draw_functions(struct si_context *sctx);

21
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -1173,10 +1173,8 @@ void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
*sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
}
extern "C"
void gfx10_emit_cache_flush(struct si_context *ctx)
void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs)
{
struct radeon_cmdbuf *cs = &ctx->gfx_cs;
uint32_t gcr_cntl = 0;
unsigned cb_db_event = 0;
unsigned flags = ctx->flags;
@ -1318,7 +1316,7 @@ void gfx10_emit_cache_flush(struct si_context *ctx)
EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
EOP_DATA_SEL_VALUE_32BIT, wait_mem_scratch, va, ctx->wait_mem_number,
SI_NOT_QUERY);
si_cp_wait_mem(ctx, &ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
si_cp_wait_mem(ctx, cs, va, ctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
}
/* Ignore fields that only modify the behavior of other fields. */
@ -1354,9 +1352,8 @@ void gfx10_emit_cache_flush(struct si_context *ctx)
}
extern "C"
void si_emit_cache_flush(struct si_context *sctx)
void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs)
{
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
uint32_t flags = sctx->flags;
if (!sctx->has_graphics) {
@ -1545,7 +1542,7 @@ void si_emit_cache_flush(struct si_context *sctx)
/* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
* WB must be set on GFX8+ when TC_ACTION is set.
*/
si_emit_surface_sync(sctx, &sctx->gfx_cs,
si_emit_surface_sync(sctx, cs,
cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) |
S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
cp_coher_cntl = 0;
@ -1562,21 +1559,21 @@ void si_emit_cache_flush(struct si_context *sctx)
* WB doesn't work without NC.
*/
si_emit_surface_sync(
sctx, &sctx->gfx_cs,
sctx, cs,
cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1));
cp_coher_cntl = 0;
sctx->num_L2_writebacks++;
}
if (flags & SI_CONTEXT_INV_VCACHE) {
/* Invalidate per-CU VMEM L1. */
si_emit_surface_sync(sctx, &sctx->gfx_cs, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1));
si_emit_surface_sync(sctx, cs, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1));
cp_coher_cntl = 0;
}
}
/* If TC flushes haven't cleared this... */
if (cp_coher_cntl)
si_emit_surface_sync(sctx, &sctx->gfx_cs, cp_coher_cntl);
si_emit_surface_sync(sctx, cs, cp_coher_cntl);
if (is_barrier)
si_prim_discard_signal_next_compute_ib_start(sctx);
@ -2347,7 +2344,7 @@ static void si_draw_vbo(struct pipe_context *ctx,
si_emit_all_states<GFX_VERSION, HAS_TESS, HAS_GS, NGG>
(sctx, info, indirect, prim, instance_count, min_direct_count,
primitive_restart, masked_atoms);
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
/* <-- CUs are idle here. */
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
@ -2378,7 +2375,7 @@ static void si_draw_vbo(struct pipe_context *ctx,
* states, and draw at the end.
*/
if (sctx->flags)
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
/* Only prefetch the API VS and VBO descriptors. */
if (GFX_VERSION >= GFX7 && sctx->prefetch_L2_mask)

2
src/gallium/drivers/radeonsi/si_state_streamout.c
View file

@ -207,7 +207,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx, unsigned num_targ
si_set_rw_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, NULL);
if (wait_now)
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
}
static void gfx10_emit_streamout_begin(struct si_context *sctx)

4
src/gallium/drivers/radeonsi/si_test_dma_perf.c
View file

@ -172,7 +172,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_FLUSH_AND_INV_CB |
SI_CONTEXT_FLUSH_AND_INV_DB;
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
struct pipe_query *q = ctx->create_query(ctx, query_type, 0);
ctx->begin_query(ctx, q);
@ -235,7 +235,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
sctx->flags |= SI_CONTEXT_INV_VCACHE |
(cache_policy == L2_LRU ? 0 : SI_CONTEXT_INV_L2) |
SI_CONTEXT_CS_PARTIAL_FLUSH;
sctx->emit_cache_flush(sctx);
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
}
ctx->end_query(ctx, q);