From aa9435f5d1eaade16eae87ac0d984a906624746a Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Fri, 21 Nov 2025 14:37:45 -0500 Subject: [PATCH] tu: Set 8E09 once This was set the same for GMEM and sysmem render passes. Set it in the beginning instead. Following the blob, only set it for BR. Part-of: --- src/freedreno/vulkan/tu_cmd_buffer.cc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 73eb02c50af..c5b2fea2577 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -2047,8 +2047,10 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs) phys_dev->info->magic.RB_DBG_ECO_CNTL); tu_cs_emit_write_reg(cs, REG_A6XX_RB_RBP_CNTL, phys_dev->info->magic.RB_RBP_CNTL); - if (CHIP >= A7XX) + if (CHIP >= A7XX) { + tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4)); tu_cond_exec_end(cs); + } if (CHIP == A7XX) { tu_cs_emit_regs(cs, TPL1_BICUBIC_WEIGHTS_TABLE_REG(CHIP, 0, 0), @@ -2103,8 +2105,6 @@ tu7_emit_tile_render_begin_regs(struct tu_cs *cs) tu_cs_emit_regs(cs, A7XX_RB_BUFFER_CNTL(0x0)); - tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4)); - tu_cs_emit_regs(cs, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM)); } @@ -2984,8 +2984,6 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, .rt7_sysmem = true, )); - tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4)); - tu_cs_emit_regs(cs, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_SYSMEM)); }