diff --git a/src/freedreno/ci/freedreno-a530-fails.txt b/src/freedreno/ci/freedreno-a530-fails.txt
index 14d131d6918..a2cceb4d14f 100644
--- a/src/freedreno/ci/freedreno-a530-fails.txt
+++ b/src/freedreno/ci/freedreno-a530-fails.txt
@@ -195,9 +195,6 @@ KHR-GLES3.packed_pixels.varied_rectangle.rgba32f,Fail
 KHR-GLES3.packed_pixels.varied_rectangle.rgba32i,Fail
 KHR-GLES3.packed_pixels.varied_rectangle.rgba32ui,Fail
 
-# "[31] Check failed. Received: [1,0,0,2] instead of: [5,0,0,2]"
-KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-fs,Fail
-
 glx@glx-make-current,Crash
 glx@glx-multi-window-single-context,Fail
 glx@glx-query-drawable-glx_fbconfig_id-window,Fail
diff --git a/src/freedreno/ci/freedreno-a630-flakes.txt b/src/freedreno/ci/freedreno-a630-flakes.txt
index 38f3e913d35..d8beb977612 100644
--- a/src/freedreno/ci/freedreno-a630-flakes.txt
+++ b/src/freedreno/ci/freedreno-a630-flakes.txt
@@ -109,13 +109,6 @@ KHR-GLES31.core.tessellation_shader.tessellation_shader_tc_barriers.barrier_guar
 # looks like a cache flushing issue, and it does sometimes pass.
 bypass-dEQP-GLES31.functional.blend_equation_advanced.msaa.*
 
-# Testcase was mostly fixed in 23f7e06cd8d40569f8bfabde9c01d1597573abef, but has
-# flaked in CI since then:
-# " [775] Check failed. Received: [3,0,0,2] instead of: [5,0,0,2]
-#   [806] Check failed. Received: [3,0,0,2] instead of: [5,0,0,2]
-#   ..."
-KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-fs
-
 # Flakes, all seen since merge of:
 # https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258
 # Failures seen so far in different flakes:
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index cf9cc7deabd..98b6c1a9bdd 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1293,10 +1293,10 @@ static void
 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
                           struct ir3_instruction **dst)
 {
-   /* Coherent accesses have to go directly to memory, rather than through
-    * ISAM's texture cache (which isn't coherent with image stores).
+   /* If the image can be written, must use LDIB to retrieve data, rather than
+    * through ISAM (which uses the texture cache and won't get previous writes).
     */
-   if (nir_intrinsic_access(intr) & ACCESS_COHERENT && ctx->compiler->gen >= 5) {
+   if (!(nir_intrinsic_access(intr) & ACCESS_NON_WRITEABLE) && ctx->compiler->gen >= 5) {
       ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
       return;
    }