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pan/bi: Add divergent intrinsic lowering pass
This is undefined behaviour in the hardware but perfectly legal NIR, so lower to an if ladder predicated on the lane ID (the blob's preferred strategy). Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10022>
This commit is contained in:
parent
4055b99de4
commit
aa765c54bd
5 changed files with 174 additions and 2 deletions
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@ -4,6 +4,7 @@ bifrost_FILES := \
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bifrost/bifrost_compile.h \
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bifrost/bi_layout.c \
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bifrost/bi_liveness.c \
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bifrost/bi_lower_divergent_indirects.c \
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bifrost/bi_lower_swizzle.c \
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bifrost/bi_schedule.c \
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bifrost/bi_scoreboard.c \
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128
src/panfrost/bifrost/bi_lower_divergent_indirects.c
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128
src/panfrost/bifrost/bi_lower_divergent_indirects.c
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@ -0,0 +1,128 @@
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/*
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* Copyright (C) 2021 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "compiler.h"
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#include "compiler/nir/nir_builder.h"
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/* Divergent attribute access is undefined behaviour. To avoid divergence,
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* lower to an if-chain like:
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*
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* value = 0;
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* if (lane == 0)
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* value = ld()
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* else if (lane == 1)
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* value = ld()
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* ...
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* else if (lane == MAX_LANE)
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* value = ld()
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*/
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static bool
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bi_lower_divergent_indirects_impl(nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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gl_shader_stage stage = b->shader->info.stage;
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nir_src *offset;
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/* Not all indirect access needs this workaround */
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switch (intr->intrinsic) {
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case nir_intrinsic_load_input:
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case nir_intrinsic_load_interpolated_input:
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/* Attributes and varyings */
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offset = nir_get_io_offset_src(intr);
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break;
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case nir_intrinsic_store_output:
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/* Varyings only */
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if (stage == MESA_SHADER_FRAGMENT)
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return false;
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offset = nir_get_io_offset_src(intr);
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break;
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case nir_intrinsic_image_atomic_add:
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case nir_intrinsic_image_atomic_imin:
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case nir_intrinsic_image_atomic_umin:
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case nir_intrinsic_image_atomic_imax:
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case nir_intrinsic_image_atomic_umax:
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case nir_intrinsic_image_atomic_and:
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case nir_intrinsic_image_atomic_or:
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case nir_intrinsic_image_atomic_xor:
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case nir_intrinsic_image_load:
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case nir_intrinsic_image_store:
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/* Any image access */
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offset = &intr->src[0];
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break;
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default:
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return false;
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}
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if (!nir_src_is_divergent(*offset))
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return false;
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/* This indirect does need it */
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b->cursor = nir_before_instr(instr);
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nir_ssa_def *lane = nir_load_subgroup_invocation(b);
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unsigned *lanes = data;
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/* Write zero in a funny way to bypass lower_load_const_to_scalar */
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bool has_dest = nir_intrinsic_infos[intr->intrinsic].has_dest;
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unsigned size = has_dest ? nir_dest_bit_size(intr->dest) : 32;
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nir_ssa_def *zero = has_dest ? nir_imm_zero(b, 1, size) : NULL;
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nir_ssa_def *zeroes[4] = { zero, zero, zero, zero };
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nir_ssa_def *res = has_dest ?
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nir_vec(b, zeroes, nir_dest_num_components(intr->dest)) : NULL;
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for (unsigned i = 0; i < (*lanes); ++i) {
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nir_push_if(b, nir_ieq_imm(b, lane, i));
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nir_instr *c = nir_instr_clone(b->shader, instr);
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nir_intrinsic_instr *c_intr = nir_instr_as_intrinsic(c);
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nir_builder_instr_insert(b, c);
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nir_pop_if(b, NULL);
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if (has_dest) {
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assert(c_intr->dest.is_ssa);
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nir_ssa_def *c_ssa = &c_intr->dest.ssa;
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res = nir_if_phi(b, c_ssa, res);
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}
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}
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if (has_dest)
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nir_ssa_def_rewrite_uses(&intr->dest.ssa, res);
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nir_instr_remove(instr);
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return true;
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}
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bool
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bi_lower_divergent_indirects(nir_shader *shader, unsigned lanes)
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{
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return nir_shader_instructions_pass(shader,
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bi_lower_divergent_indirects_impl,
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nir_metadata_none, &lanes);
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}
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@ -2907,8 +2907,27 @@ bi_vectorize_filter(const nir_instr *instr, void *data)
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}
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}
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/* XXX: This is a kludge to workaround NIR's lack of divergence metadata. If we
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* keep divergence info around after we consume it for indirect lowering,
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* nir_convert_from_ssa will regress code quality since it will avoid
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* coalescing divergent with non-divergent nodes. */
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static bool
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nir_invalidate_divergence_ssa(nir_ssa_def *ssa, UNUSED void *data)
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{
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ssa->divergent = false;
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return true;
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}
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static bool
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nir_invalidate_divergence(struct nir_builder *b, nir_instr *instr,
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UNUSED void *data)
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{
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return nir_foreach_ssa_def(instr, nir_invalidate_divergence_ssa, NULL);
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}
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static void
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bi_optimize_nir(nir_shader *nir, bool is_blend)
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bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
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{
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bool progress;
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unsigned lower_flrp = 16 | 32 | 64;
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@ -3014,6 +3033,24 @@ bi_optimize_nir(nir_shader *nir, bool is_blend)
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NIR_PASS_V(nir, nir_opt_move, move_all);
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}
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/* We might lower attribute, varying, and image indirects. Use the
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* gathered info to skip the extra analysis in the happy path. */
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bool any_indirects =
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nir->info.inputs_read_indirectly ||
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nir->info.outputs_accessed_indirectly ||
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nir->info.patch_inputs_read_indirectly ||
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nir->info.patch_outputs_accessed_indirectly ||
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nir->info.images_used;
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if (any_indirects) {
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nir_convert_to_lcssa(nir, true, true);
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NIR_PASS_V(nir, nir_divergence_analysis);
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NIR_PASS_V(nir, bi_lower_divergent_indirects,
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bifrost_lanes_per_warp(gpu_id));
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NIR_PASS_V(nir, nir_shader_instructions_pass,
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nir_invalidate_divergence, nir_metadata_all, NULL);
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}
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/* Take us out of SSA */
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NIR_PASS(progress, nir, nir_lower_locals_to_regs);
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NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
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@ -3172,7 +3209,7 @@ bifrost_compile_shader_nir(nir_shader *nir,
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NULL);
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}
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bi_optimize_nir(nir, ctx->inputs->is_blend);
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bi_optimize_nir(nir, ctx->inputs->gpu_id, ctx->inputs->is_blend);
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NIR_PASS_V(nir, pan_nir_reorder_writeout);
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@ -988,4 +988,9 @@ bi_builder_insert(bi_cursor *cursor, bi_instr *I)
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unreachable("Invalid cursor option");
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}
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/* NIR passes */
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bool bi_lower_divergent_indirects(nir_shader *shader, unsigned lanes);
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#endif
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@ -22,6 +22,7 @@
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libpanfrost_bifrost_files = files(
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'bi_layout.c',
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'bi_liveness.c',
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'bi_lower_divergent_indirects.c',
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'bi_lower_swizzle.c',
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'bi_print.c',
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'bi_opt_constant_fold.c',
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