From aa09fc3de0af5b29b86c0b270cff63be5e72095e Mon Sep 17 00:00:00 2001
From: Nanley Chery <nanley.g.chery@intel.com>
Date: Wed, 15 Oct 2025 09:01:21 -0400
Subject: [PATCH] intel/isl: Use 1x Ys/Yf swizzle for IMS layout
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

From the ICL PRMs Volume 5: Memory Data Formats, "Compressed
Multisampled Surfaces":

   Tiling for CMS and UMS Surfaces

   Multisampled CMS and UMS use a modified table from
   non-mulitsampled 2D surfaces.

   [...]

   TileYS: In addition to u and v, the sample slice index “ss” is
   included in the address swizzling according to the following
   table.

   [...]

   TileYF: In addition to u and v, the sample slice index “ss” is
   included in the address swizzling according to the following
   table.

For depth/stencil surfaces with Yf/Ys tiling, don't use the MSAA
swizzles.

With the driver modified forced to prefer Ys/Yf for depth buffers, this
fixes 14 failing tests in the VK CTS group:

   dEQP-VK.pipeline.monolithic.multisample.misc.clear*16x*

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38063>
---
 src/intel/isl/isl.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index b95da701378..ddd959ecf52 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1290,18 +1290,43 @@ isl_tiling_get_info(enum isl_tiling tiling,
          };
 
 #undef YS_OR_YF
+         /* From the ICL PRMs Volume 5: Memory Data Formats, "Compressed
+          * Multisampled Surfaces":
+          *
+          *    Tiling for CMS and UMS Surfaces
+          *
+          *    Multisampled CMS and UMS use a modified table from
+          *    non-mulitsampled 2D surfaces.
+          *
+          *    [...]
+          *
+          *    TileYS: In addition to u and v, the sample slice index “ss” is
+          *    included in the address swizzling according to the following
+          *    table.
+          *
+          *    [...]
+          *
+          *    TileYF: In addition to u and v, the sample slice index “ss” is
+          *    included in the address swizzling according to the following
+          *    table.
+          *
+          * IMS surfaces don't use the MSAA swizzles for Yf/Ys.
+          */
+         const uint32_t sample_idx =
+            (msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) ? 0 :
+            (ffs(samples) - 1);
 
          switch (format_bpb) {
          case 128:
          case 64:
-            SET_SWIZ(_128_64bpp_swiz[ffs(samples) - 1], tiling_bits);
+            SET_SWIZ(_128_64bpp_swiz[sample_idx], tiling_bits);
             break;
          case 32:
          case 16:
-            SET_SWIZ(_32_16bpp_swiz[ffs(samples) - 1], tiling_bits);
+            SET_SWIZ(_32_16bpp_swiz[sample_idx], tiling_bits);
             break;
          case 8:
-            SET_SWIZ(_8bpp_swiz[ffs(samples) - 1], tiling_bits);
+            SET_SWIZ(_8bpp_swiz[sample_idx], tiling_bits);
             break;
          default:
             UNREACHABLE("Unsupported format size");