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radeonsi/rgp: export barriers

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Wrap the si_cp_wait_mem call to emit RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START and
RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END events.

Only for gfx9+ for now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10105>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2021-03-15 12:49:49 +01:00
parent 0e0dc669bd
commit aa077ba3a2
3 changed files with 74 additions and 0 deletions
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18
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -744,7 +744,16 @@ void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs)
EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
EOP_DATA_SEL_VALUE_32BIT, wait_mem_scratch, va, ctx->wait_mem_number,
SI_NOT_QUERY);
if (unlikely(ctx->thread_trace_enabled)) {
si_sqtt_describe_barrier_start(ctx, &ctx->gfx_cs);
}
si_cp_wait_mem(ctx, cs, va, ctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
if (unlikely(ctx->thread_trace_enabled)) {
si_sqtt_describe_barrier_end(ctx, &ctx->gfx_cs, flags);
}
}
radeon_begin_again(cs);
@ -953,7 +962,16 @@ void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs)
si_cp_release_mem(sctx, cs, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT,
wait_mem_scratch, va, sctx->wait_mem_number, SI_NOT_QUERY);
if (unlikely(sctx->thread_trace_enabled)) {
si_sqtt_describe_barrier_start(sctx, &sctx->gfx_cs);
}
si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, WAIT_REG_MEM_EQUAL);
if (unlikely(sctx->thread_trace_enabled)) {
si_sqtt_describe_barrier_end(sctx, &sctx->gfx_cs, sctx->flags);
}
}
/* GFX6-GFX8 only:

4
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1617,6 +1617,10 @@ void
si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_user_event_type type,
const char *str, int len);
void
si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs);
void
si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags);
bool si_init_thread_trace(struct si_context *sctx);
void si_destroy_thread_trace(struct si_context *sctx);
void si_handle_thread_trace(struct si_context *sctx, struct radeon_cmdbuf *rcs);

52
src/gallium/drivers/radeonsi/si_sqtt.c
View file

@ -811,6 +811,58 @@ si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *r
sctx->sqtt_next_event = EventInvalid;
}
void
si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs)
{
struct rgp_sqtt_marker_barrier_start marker = {0};
marker.identifier = RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START;
marker.cb_id = 0;
marker.dword02 = 0xC0000000 + 10; /* RGP_BARRIER_INTERNAL_BASE */
si_emit_thread_trace_userdata(sctx, rcs, &marker, sizeof(marker) / 4);
}
void
si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs,
unsigned flags)
{
struct rgp_sqtt_marker_barrier_end marker = {0};
marker.identifier = RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END;
marker.cb_id = 0;
if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH)
marker.vs_partial_flush = true;
if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH)
marker.ps_partial_flush = true;
if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH)
marker.cs_partial_flush = true;
if (flags & SI_CONTEXT_PFP_SYNC_ME)
marker.pfp_sync_me = true;
if (flags & SI_CONTEXT_INV_VCACHE)
marker.inval_tcp = true;
if (flags & SI_CONTEXT_INV_ICACHE)
marker.inval_sqI = true;
if (flags & SI_CONTEXT_INV_SCACHE)
marker.inval_sqK = true;
if (flags & SI_CONTEXT_INV_L2)
marker.inval_tcc = true;
if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
marker.inval_cb = true;
marker.flush_cb = true;
}
if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
marker.inval_db = true;
marker.flush_db = true;
}
si_emit_thread_trace_userdata(sctx, rcs, &marker, sizeof(marker) / 4);
}
void
si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_user_event_type type,