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ac,radv,radeonsi: a function that sets mutable CB surface fields

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29378>
This commit is contained in:
Samuel Pitoiset 2024-05-24 12:20:01 +02:00 • committed by Marge Bot
parent 6836118cd2
commit a9f4931a91
6 changed files with 333 additions and 404 deletions
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139
src/amd/common/ac_descriptors.c
View file

@ -1110,3 +1110,142 @@ ac_init_cb_surface(const struct radeon_info *info, const struct ac_cb_state *sta
ac_init_gfx6_cb_surface(info, state, cb_format, force_dst_alpha_1, cb);
}
}
void
ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac_mutable_cb_state *state,
struct ac_cb_surface *cb)
{
const struct radeon_surf *surf = state->surf;
uint8_t tile_swizzle = surf->tile_swizzle;
uint64_t va = state->va;
memcpy(cb, state->cb, sizeof(*cb));
if (state->gfx10.nbc_view) {
assert(state->gfx10.nbc_view->valid);
va += state->gfx10.nbc_view->base_address_offset;
tile_swizzle = state->gfx10.nbc_view->tile_swizzle;
}
cb->cb_color_base = va >> 8;
if (info->gfx_level >= GFX9) {
cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
cb->cb_color_base |= tile_swizzle;
} else {
const struct legacy_surf_level *level_info = &surf->u.legacy.level[state->base_level];
cb->cb_color_base += level_info->offset_256B;
/* Only macrotiled modes can set tile swizzle. */
if (level_info->mode == RADEON_SURF_MODE_2D)
cb->cb_color_base |= tile_swizzle;
}
if (info->gfx_level >= GFX12)
return;
/* Set up DCC. */
if (state->dcc_enabled) {
cb->cb_dcc_base = (va + surf->meta_offset) >> 8;
if (info->gfx_level == GFX8)
cb->cb_dcc_base += surf->u.legacy.color.dcc_level[state->base_level].dcc_offset >> 8;
uint32_t dcc_tile_swizzle = tile_swizzle;
dcc_tile_swizzle &= ((1 << surf->meta_alignment_log2) - 1) >> 8;
cb->cb_dcc_base |= dcc_tile_swizzle;
}
if (info->gfx_level >= GFX11) {
cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned);
if (state->dcc_enabled) {
cb->cb_dcc_control |= S_028C78_DISABLE_CONSTANT_ENCODE_REG(1) |
S_028C78_FDCC_ENABLE(1);
if (info->family >= CHIP_GFX1103_R2) {
cb->cb_dcc_control |= S_028C78_ENABLE_MAX_COMP_FRAG_OVERRIDE(1) |
S_028C78_MAX_COMP_FRAGS(state->num_samples >= 4);
}
}
} else if (info->gfx_level >= GFX10) {
cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028EE0_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) |
S_028EE0_CMASK_PIPE_ALIGNED(1) |
S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned);
} else if (info->gfx_level == GFX9) {
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
.pipe_aligned = 1,
};
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_offset)
meta = surf->u.gfx9.color.dcc;
cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028C74_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) |
S_028C74_RB_ALIGNED(meta.rb_aligned) |
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.epitch);
} else {
/* GFX6-8 */
const struct legacy_surf_level *level_info = &surf->u.legacy.level[state->base_level];
uint32_t pitch_tile_max, slice_tile_max, tile_mode_index;
pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
tile_mode_index = ac_tile_mode_index(surf, state->base_level, false);
cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
cb->cb_color_cmask_slice = surf->u.legacy.color.cmask_slice_tile_max;
if (state->fmask_enabled) {
if (info->gfx_level >= GFX7)
cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.color.fmask.pitch_in_pixels / 8 - 1);
cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.color.fmask.tiling_index);
cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.color.fmask.slice_tile_max);
} else {
/* This must be set for fast clear to work without FMASK. */
if (info->gfx_level >= GFX7)
cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
}
}
if (state->cmask_enabled) {
cb->cb_color_cmask = (va + surf->cmask_offset) >> 8;
cb->cb_color_info |= S_028C70_FAST_CLEAR(state->fast_clear_enabled);
} else {
cb->cb_color_cmask = cb->cb_color_base;
}
if (state->fmask_enabled) {
cb->cb_color_fmask = (va + surf->fmask_offset) >> 8;
cb->cb_color_fmask |= surf->fmask_tile_swizzle;
if (state->tc_compat_cmask_enabled) {
assert(state->cmask_enabled);
/* Allow the texture block to read FMASK directly without decompressing it. */
cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
if (info->gfx_level == GFX8) {
/* Set CMASK into a tiling format that allows
* the texture block to read it.
*/
cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
}
}
} else {
cb->cb_color_fmask = cb->cb_color_base;
}
if (info->gfx_level < GFX11)
cb->cb_color_info |= S_028C70_DCC_ENABLE(state->dcc_enabled);
}

34
src/amd/common/ac_descriptors.h
View file

@ -229,11 +229,45 @@ struct ac_cb_surface {
uint32_t cb_color_attrib2; /* GFX9+ */
uint32_t cb_color_attrib3; /* GFX10+ */
uint32_t cb_dcc_control;
uint64_t cb_color_base;
uint64_t cb_color_cmask;
uint64_t cb_color_fmask;
uint64_t cb_dcc_base;
uint32_t cb_color_slice;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
union {
uint32_t cb_color_pitch; /* GFX6-GFX8 */
uint32_t cb_mrt_epitch; /* GFX9+ */
};
};
void
ac_init_cb_surface(const struct radeon_info *info, const struct ac_cb_state *state, struct ac_cb_surface *cb);
struct ac_mutable_cb_state {
const struct radeon_surf *surf;
const struct ac_cb_surface *cb; /* original CB surface */
uint64_t va;
uint32_t base_level : 5;
uint32_t num_samples : 5;
uint32_t fmask_enabled : 1;
uint32_t cmask_enabled : 1;
uint32_t fast_clear_enabled : 1;
uint32_t tc_compat_cmask_enabled : 1;
uint32_t dcc_enabled : 1;
struct {
struct ac_surf_nbc_view *nbc_view;
} gfx10;
};
void
ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac_mutable_cb_state *state,
struct ac_cb_surface *cb);
#ifdef __cplusplus
}
#endif

60
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3670,69 +3670,71 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, struct r
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cmd_buffer->cs, cb_fdcc_control); /* CB_COLOR0_FDCC_CONTROL */
radeon_set_context_reg(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, cb->cb_color_base);
radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4, cb->cb_color_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4, cb->cb_dcc_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, cb->ac.cb_color_base);
radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4, cb->ac.cb_color_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->ac.cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4, cb->ac.cb_dcc_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4, cb->ac.cb_color_attrib2);
radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4, cb->ac.cb_color_attrib3);
} else if (pdev->info.gfx_level >= GFX10) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_base);
radeon_emit(cmd_buffer->cs, 0);
radeon_emit(cmd_buffer->cs, 0);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_view);
radeon_emit(cmd_buffer->cs, cb_color_info);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_attrib);
radeon_emit(cmd_buffer->cs, cb->ac.cb_dcc_control);
radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_cmask);
radeon_emit(cmd_buffer->cs, 0);
radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_fmask);
radeon_emit(cmd_buffer->cs, 0);
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->ac.cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4, cb->cb_color_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4, cb->cb_color_cmask >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4, cb->cb_color_fmask >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4, cb->cb_dcc_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4, cb->ac.cb_color_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
cb->ac.cb_color_cmask >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
cb->ac.cb_color_fmask >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4, cb->ac.cb_dcc_base >> 32);
radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4, cb->ac.cb_color_attrib2);
radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4, cb->ac.cb_color_attrib3);
} else if (pdev->info.gfx_level == GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_base);
radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->ac.cb_color_base >> 32));
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_attrib2);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_view);
radeon_emit(cmd_buffer->cs, cb_color_info);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_attrib);
radeon_emit(cmd_buffer->cs, cb->ac.cb_dcc_control);
radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_cmask);
radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->ac.cb_color_cmask >> 32));
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_fmask);
radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->ac.cb_color_fmask >> 32));
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
radeon_emit(cmd_buffer->cs, cb->ac.cb_dcc_base);
radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->ac.cb_dcc_base >> 32));
radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4, cb->cb_mrt_epitch);
radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4, cb->ac.cb_mrt_epitch);
} else {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_base);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_pitch);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_slice);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_view);
radeon_emit(cmd_buffer->cs, cb_color_info);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_attrib);
radeon_emit(cmd_buffer->cs, cb->ac.cb_dcc_control);
radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_cmask);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_cmask_slice);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_fmask);
radeon_emit(cmd_buffer->cs, cb->ac.cb_color_fmask_slice);
if (is_vi) { /* DCC BASE */
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->ac.cb_dcc_base);
}
}

137
src/amd/vulkan/radv_device.c
View file

@ -1484,7 +1484,6 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
uint64_t va;
const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
const struct radeon_surf *surf = &plane->surface;
uint8_t tile_swizzle = plane->surface.tile_swizzle;
memset(cb, 0, sizeof(*cb));
@ -1514,125 +1513,25 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
uint32_t plane_id = iview->image->disjoint ? iview->plane_id : 0;
va = radv_buffer_get_va(iview->image->bindings[plane_id].bo) + iview->image->bindings[plane_id].offset;
if (iview->nbc_view.valid) {
va += iview->nbc_view.base_address_offset;
tile_swizzle = iview->nbc_view.tile_swizzle;
}
const struct ac_mutable_cb_state mutable_cb_state = {
.surf = surf,
.cb = &cb->ac,
.va = va,
.base_level = iview->vk.base_mip_level,
.num_samples = iview->image->vk.samples,
.fmask_enabled = radv_image_has_fmask(iview->image),
.cmask_enabled = radv_image_has_cmask(iview->image),
.fast_clear_enabled = !(instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS),
.tc_compat_cmask_enabled = radv_image_is_tc_compat_cmask(iview->image),
.dcc_enabled = radv_dcc_enabled(iview->image, iview->vk.base_mip_level) &&
(pdev->info.gfx_level >= GFX11 || !iview->disable_dcc_mrt),
.gfx10 =
{
.nbc_view = iview->nbc_view.valid ? &iview->nbc_view : NULL,
},
};
cb->cb_color_base = va >> 8;
if (pdev->info.gfx_level >= GFX9) {
if (pdev->info.gfx_level >= GFX11) {
cb->ac.cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned);
} else if (pdev->info.gfx_level >= GFX10) {
cb->ac.cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028EE0_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) |
S_028EE0_CMASK_PIPE_ALIGNED(1) |
S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned);
} else {
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
.pipe_aligned = 1,
};
if (surf->meta_offset)
meta = surf->u.gfx9.color.dcc;
cb->ac.cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028C74_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) |
S_028C74_RB_ALIGNED(meta.rb_aligned) | S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.epitch);
}
cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
cb->cb_color_base |= tile_swizzle;
} else {
const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->vk.base_mip_level];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
cb->cb_color_base += level_info->offset_256B;
if (level_info->mode == RADEON_SURF_MODE_2D)
cb->cb_color_base |= tile_swizzle;
pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
tile_mode_index = ac_tile_mode_index(&plane->surface, iview->vk.base_mip_level, false);
cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
cb->cb_color_cmask_slice = surf->u.legacy.color.cmask_slice_tile_max;
cb->ac.cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
if (radv_image_has_fmask(iview->image)) {
if (pdev->info.gfx_level >= GFX7)
cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.color.fmask.pitch_in_pixels / 8 - 1);
cb->ac.cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.color.fmask.tiling_index);
cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.color.fmask.slice_tile_max);
} else {
/* This must be set for fast clear to work without FMASK. */
if (pdev->info.gfx_level >= GFX7)
cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
cb->ac.cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
}
}
/* CMASK variables */
va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset;
va += surf->cmask_offset;
cb->cb_color_cmask = va >> 8;
va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset;
va += surf->meta_offset;
if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && pdev->info.gfx_level <= GFX8)
va += plane->surface.u.legacy.color.dcc_level[iview->vk.base_mip_level].dcc_offset;
unsigned dcc_tile_swizzle = tile_swizzle;
dcc_tile_swizzle &= ((1 << surf->meta_alignment_log2) - 1) >> 8;
cb->cb_dcc_base = va >> 8;
cb->cb_dcc_base |= dcc_tile_swizzle;
if (radv_image_has_fmask(iview->image)) {
va = radv_buffer_get_va(iview->image->bindings[0].bo) + iview->image->bindings[0].offset + surf->fmask_offset;
cb->cb_color_fmask = va >> 8;
cb->cb_color_fmask |= surf->fmask_tile_swizzle;
} else {
cb->cb_color_fmask = cb->cb_color_base;
}
if (radv_image_has_fmask(iview->image)) {
if (radv_image_is_tc_compat_cmask(iview->image)) {
/* Allow the texture block to read FMASK directly without decompressing it. */
cb->ac.cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
if (pdev->info.gfx_level == GFX8) {
/* Set CMASK into a tiling format that allows
* the texture block to read it.
*/
cb->ac.cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
}
}
}
if (radv_image_has_cmask(iview->image) && !(instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->ac.cb_color_info |= S_028C70_FAST_CLEAR(1);
if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && !iview->disable_dcc_mrt &&
pdev->info.gfx_level < GFX11)
cb->ac.cb_color_info |= S_028C70_DCC_ENABLE(1);
if (pdev->info.gfx_level == GFX11 && radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) {
cb->ac.cb_dcc_control |= S_028C78_DISABLE_CONSTANT_ENCODE_REG(1) | S_028C78_FDCC_ENABLE(1);
if (pdev->info.family >= CHIP_GFX1103_R2) {
cb->ac.cb_dcc_control |=
S_028C78_ENABLE_MAX_COMP_FRAG_OVERRIDE(1) | S_028C78_MAX_COMP_FRAGS(iview->image->vk.samples >= 4);
}
}
ac_set_mutable_cb_surface_fields(&pdev->info, &mutable_cb_state, &cb->ac);
}
void

12
src/amd/vulkan/radv_device.h
View file

@ -608,18 +608,6 @@ unsigned radv_get_dcc_max_uncompressed_block_size(const struct radv_device *devi
struct radv_color_buffer_info {
struct ac_cb_surface ac;
uint64_t cb_color_base;
uint64_t cb_color_cmask;
uint64_t cb_color_fmask;
uint64_t cb_dcc_base;
uint32_t cb_color_slice;
uint32_t cb_color_cmask_slice;
uint32_t cb_color_fmask_slice;
union {
uint32_t cb_color_pitch; // GFX6-GFX8
uint32_t cb_mrt_epitch; // GFX9+
};
};
struct radv_ds_buffer_info {

355
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2920,9 +2920,24 @@ static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
}
/* Compute mutable surface parameters. */
uint64_t cb_color_base = tex->buffer.gpu_address >> 8;
uint64_t cb_dcc_base = 0;
unsigned cb_color_info = cb->cb.cb_color_info | tex->cb_color_info;
const struct ac_mutable_cb_state mutable_cb_state = {
.surf = &tex->surface,
.cb = &cb->cb,
.va = tex->buffer.gpu_address,
.base_level = cb->base.u.tex.level,
.num_samples = cb->base.texture->nr_samples,
.fmask_enabled = !!tex->surface.fmask_offset,
/* CMASK and fast clears are configured elsewhere. */
.cmask_enabled = false,
.fast_clear_enabled = false,
.dcc_enabled = vi_dcc_enabled(tex, cb->base.u.tex.level) &&
(i != 1 || !is_msaa_resolve),
};
struct ac_cb_surface cb_surf;
ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
cb_surf.cb_color_info |= tex->cb_color_info;
if (sctx->gfx_level < GFX11) {
if (tex->swap_rgb_to_bgr) {
@ -2933,232 +2948,96 @@ static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
[V_028C70_SWAP_STD_REV] = V_028C70_SWAP_ALT_REV,
[V_028C70_SWAP_ALT_REV] = V_028C70_SWAP_STD_REV,
};
unsigned swap = rgb_to_bgr[G_028C70_COMP_SWAP(cb_color_info)];
unsigned swap = rgb_to_bgr[G_028C70_COMP_SWAP(cb_surf.cb_color_info)];
cb_color_info &= C_028C70_COMP_SWAP;
cb_color_info |= S_028C70_COMP_SWAP(swap);
cb_surf.cb_color_info &= C_028C70_COMP_SWAP;
cb_surf.cb_color_info |= S_028C70_COMP_SWAP(swap);
}
if (cb->base.u.tex.level > 0)
cb_color_info &= C_028C70_FAST_CLEAR;
if (vi_dcc_enabled(tex, cb->base.u.tex.level) && (i != 1 || !is_msaa_resolve))
cb_color_info |= S_028C70_DCC_ENABLE(1);
}
/* Set up DCC. */
if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
dcc_tile_swizzle &= ((1 << tex->surface.meta_alignment_log2) - 1) >> 8;
cb_dcc_base |= dcc_tile_swizzle;
cb_surf.cb_color_info &= C_028C70_FAST_CLEAR;
else
cb_surf.cb_color_cmask = tex->cmask_base_address_reg;
}
if (sctx->gfx_level >= GFX11) {
unsigned cb_color_attrib3, cb_fdcc_control;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
cb_color_attrib3 = cb->cb.cb_color_attrib3 |
S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
cb_fdcc_control = cb->cb.cb_dcc_control |
S_028C78_DISABLE_CONSTANT_ENCODE_REG(1) |
S_028C78_FDCC_ENABLE(vi_dcc_enabled(tex, cb->base.u.tex.level));
if (sctx->family >= CHIP_GFX1103_R2) {
cb_fdcc_control |= S_028C78_ENABLE_MAX_COMP_FRAG_OVERRIDE(1) |
S_028C78_MAX_COMP_FRAGS(cb->base.texture->nr_samples >= 4);
}
radeon_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_color_base);
radeon_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_surf.cb_color_base);
radeon_set_context_reg_seq(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, 4);
radeon_emit(cb->cb.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb->cb.cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb_fdcc_control); /* CB_COLOR0_FDCC_CONTROL */
radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_FDCC_CONTROL */
radeon_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_dcc_base);
radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb.cb_color_attrib2);
radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
radeon_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_surf.cb_dcc_base);
radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
} else if (sctx->gfx_level >= GFX10) {
unsigned cb_color_attrib3;
uint64_t cb_color_fmask, cb_color_cmask;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
if (tex->surface.fmask_offset) {
cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
cb_color_fmask |= tex->surface.fmask_tile_swizzle;
} else {
cb_color_fmask = cb_color_base;
}
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
else
cb_color_cmask = tex->cmask_base_address_reg;
cb_color_attrib3 = cb->cb.cb_color_attrib3 |
S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
S_028EE0_CMASK_PIPE_ALIGNED(1) |
S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(0); /* hole */
radeon_emit(0); /* hole */
radeon_emit(cb->cb.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb->cb.cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb->cb.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
radeon_emit(cb_color_cmask); /* CB_COLOR0_CMASK */
radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
radeon_emit(0); /* hole */
radeon_emit(cb_color_fmask); /* CB_COLOR0_FMASK */
radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
radeon_emit(0); /* hole */
radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
radeon_emit(cb_surf.cb_dcc_base); /* CB_COLOR0_DCC_BASE */
radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
radeon_set_context_reg(R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
cb_color_cmask >> 32);
cb_surf.cb_color_cmask >> 32);
radeon_set_context_reg(R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
cb_color_fmask >> 32);
radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb.cb_color_attrib2);
radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
cb_surf.cb_color_fmask >> 32);
radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
} else if (sctx->gfx_level == GFX9) {
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
.pipe_aligned = 1,
};
unsigned cb_color_attrib = cb->cb.cb_color_attrib;
uint64_t cb_color_fmask, cb_color_cmask;
if (!tex->is_depth && tex->surface.meta_offset)
meta = tex->surface.u.gfx9.color.dcc;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
if (tex->surface.fmask_offset) {
cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
cb_color_fmask |= tex->surface.fmask_tile_swizzle;
} else {
cb_color_fmask = cb_color_base;
}
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
else
cb_color_cmask = tex->cmask_base_address_reg;
cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
S_028C74_RB_ALIGNED(meta.rb_aligned) |
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
radeon_emit(cb->cb.cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
radeon_emit(cb->cb.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb->cb.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
radeon_emit(cb_color_cmask); /* CB_COLOR0_CMASK */
radeon_emit(S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
radeon_emit(cb_color_fmask); /* CB_COLOR0_FMASK */
radeon_emit(S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(S_028C64_BASE_256B(cb_surf.cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
radeon_emit(cb_surf.cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
radeon_emit(S_028C80_BASE_256B(cb_surf.cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
radeon_emit(S_028C88_BASE_256B(cb_surf.cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
radeon_emit(S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
radeon_emit(cb_surf.cb_dcc_base); /* CB_COLOR0_DCC_BASE */
radeon_emit(S_028C98_BASE_256B(cb_surf.cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4,
S_0287A0_EPITCH(tex->surface.u.gfx9.epitch));
radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4, cb_surf.cb_mrt_epitch);
} else {
/* Compute mutable surface parameters (GFX6-GFX8). */
const struct legacy_surf_level *level_info =
&tex->surface.u.legacy.level[cb->base.u.tex.level];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
unsigned cb_color_attrib = cb->cb.cb_color_attrib;
uint64_t cb_color_fmask, cb_color_cmask;
cb_color_base += level_info->offset_256B;
/* Only macrotiled modes can set tile swizzle. */
if (level_info->mode == RADEON_SURF_MODE_2D)
cb_color_base |= tex->surface.tile_swizzle;
if (tex->surface.fmask_offset) {
cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
cb_color_fmask |= tex->surface.fmask_tile_swizzle;
} else {
cb_color_fmask = cb_color_base;
}
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
else
cb_color_cmask = tex->cmask_base_address_reg;
if (cb_dcc_base)
cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8;
pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = level_info->nblk_x * level_info->nblk_y / 64 - 1;
tile_mode_index = ac_tile_mode_index(&tex->surface, cb->base.u.tex.level, false);
cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
if (tex->surface.fmask_offset) {
if (sctx->gfx_level >= GFX7)
cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.color.fmask.pitch_in_pixels / 8 - 1);
cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.color.fmask.tiling_index);
cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.color.fmask.slice_tile_max);
} else {
/* This must be set for fast clear to work without FMASK. */
if (sctx->gfx_level >= GFX7)
cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
}
/* GFX6-8 */
radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C,
sctx->gfx_level >= GFX8 ? 14 : 13);
radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(cb_color_pitch); /* CB_COLOR0_PITCH */
radeon_emit(cb_color_slice); /* CB_COLOR0_SLICE */
radeon_emit(cb->cb.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb->cb.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
radeon_emit(cb_color_cmask); /* CB_COLOR0_CMASK */
radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(cb_surf.cb_color_pitch); /* CB_COLOR0_PITCH */
radeon_emit(cb_surf.cb_color_slice); /* CB_COLOR0_SLICE */
radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
radeon_emit(tex->surface.u.legacy.color.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
radeon_emit(cb_color_fmask); /* CB_COLOR0_FMASK */
radeon_emit(cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
radeon_emit(cb_surf.cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
if (sctx->gfx_level >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
radeon_emit(cb_dcc_base);
radeon_emit(cb_surf.cb_dcc_base);
}
}
for (; i < 8; i++)
@ -3339,47 +3218,29 @@ static void gfx11_dgpu_emit_framebuffer_state(struct si_context *sctx, unsigned
}
/* Compute mutable surface parameters. */
uint64_t cb_color_base = tex->buffer.gpu_address >> 8;
uint64_t cb_dcc_base = 0;
unsigned cb_color_info = cb->cb.cb_color_info | tex->cb_color_info;
const struct ac_mutable_cb_state mutable_cb_state = {
.surf = &tex->surface,
.cb = &cb->cb,
.va = tex->buffer.gpu_address,
.num_samples = cb->base.texture->nr_samples,
.dcc_enabled = vi_dcc_enabled(tex, cb->base.u.tex.level),
};
struct ac_cb_surface cb_surf;
/* Set up DCC. */
if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
dcc_tile_swizzle &= ((1 << tex->surface.meta_alignment_log2) - 1) >> 8;
cb_dcc_base |= dcc_tile_swizzle;
}
cb_surf.cb_color_info |= tex->cb_color_info;
unsigned cb_color_attrib3, cb_fdcc_control;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
cb_color_attrib3 = cb->cb.cb_color_attrib3 |
S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
cb_fdcc_control = cb->cb.cb_dcc_control |
S_028C78_DISABLE_CONSTANT_ENCODE_REG(1) |
S_028C78_FDCC_ENABLE(vi_dcc_enabled(tex, cb->base.u.tex.level));
if (sctx->family >= CHIP_GFX1103_R2) {
cb_fdcc_control |= S_028C78_ENABLE_MAX_COMP_FRAG_OVERRIDE(1) |
S_028C78_MAX_COMP_FRAGS(cb->base.texture->nr_samples >= 4);
}
gfx11_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_color_base);
gfx11_set_context_reg(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, cb->cb.cb_color_view);
gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, cb_color_info);
gfx11_set_context_reg(R_028C74_CB_COLOR0_ATTRIB + i * 0x3C, cb->cb.cb_color_attrib);
gfx11_set_context_reg(R_028C78_CB_COLOR0_DCC_CONTROL + i * 0x3C, cb_fdcc_control);
gfx11_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_dcc_base);
gfx11_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
gfx11_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
gfx11_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb.cb_color_attrib2);
gfx11_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
gfx11_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_surf.cb_color_base);
gfx11_set_context_reg(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, cb_surf.cb_color_view);
gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, cb_surf.cb_color_info);
gfx11_set_context_reg(R_028C74_CB_COLOR0_ATTRIB + i * 0x3C, cb_surf.cb_color_attrib);
gfx11_set_context_reg(R_028C78_CB_COLOR0_DCC_CONTROL + i * 0x3C, cb_surf.cb_dcc_control);
gfx11_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_surf.cb_dcc_base);
gfx11_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
gfx11_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
gfx11_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
gfx11_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
}
for (; i < 8; i++)
if (sctx->framebuffer.dirty_cbufs & (1 << i))
@ -3501,20 +3362,26 @@ static void gfx12_emit_framebuffer_state(struct si_context *sctx, unsigned index
(tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
/* Compute mutable surface parameters. */
uint64_t cb_color_base = ((tex->buffer.gpu_address + tex->surface.u.gfx9.surf_offset) >> 8) |
tex->surface.tile_swizzle;
const struct ac_mutable_cb_state mutable_cb_state = {
.surf = &tex->surface,
.cb = &cb->cb,
.va = tex->buffer.gpu_address,
};
struct ac_cb_surface cb_surf;
gfx12_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x24, cb_color_base);
gfx12_set_context_reg(R_028C64_CB_COLOR0_VIEW + i * 0x24, cb->cb.cb_color_view);
gfx12_set_context_reg(R_028C68_CB_COLOR0_VIEW2 + i * 0x24, cb->cb.cb_color_view2);
gfx12_set_context_reg(R_028C6C_CB_COLOR0_ATTRIB + i * 0x24, cb->cb.cb_color_attrib);
gfx12_set_context_reg(R_028C70_CB_COLOR0_FDCC_CONTROL + i * 0x24, cb->cb.cb_dcc_control);
gfx12_set_context_reg(R_028C78_CB_COLOR0_ATTRIB2 + i * 0x24, cb->cb.cb_color_attrib2);
ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
gfx12_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x24, cb_surf.cb_color_base);
gfx12_set_context_reg(R_028C64_CB_COLOR0_VIEW + i * 0x24, cb_surf.cb_color_view);
gfx12_set_context_reg(R_028C68_CB_COLOR0_VIEW2 + i * 0x24, cb_surf.cb_color_view2);
gfx12_set_context_reg(R_028C6C_CB_COLOR0_ATTRIB + i * 0x24, cb_surf.cb_color_attrib);
gfx12_set_context_reg(R_028C70_CB_COLOR0_FDCC_CONTROL + i * 0x24, cb_surf.cb_dcc_control);
gfx12_set_context_reg(R_028C78_CB_COLOR0_ATTRIB2 + i * 0x24, cb_surf.cb_color_attrib2);
gfx12_set_context_reg(R_028C7C_CB_COLOR0_ATTRIB3 + i * 0x24,
cb->cb.cb_color_attrib3 |
cb_surf.cb_color_attrib3 |
S_028C7C_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode));
gfx12_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4, cb->cb.cb_color_info);
gfx12_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4, cb_surf.cb_color_info);
}
/* Set unbound colorbuffers. */
for (; i < 8; i++)