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i965/miptree: Use the correct BLT pitch

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Retile miptrees to a linear tiling less often. Retiling can cause issues
with imported BOs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 0288fe8d04)
This commit is contained in:
Nanley Chery 2018-05-30 16:32:07 -07:00 • committed by Dylan Baker
parent 32331a3efc
commit a9dbc4b3f4
1 changed files with 6 additions and 6 deletions
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12
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
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@ -509,7 +509,7 @@ free_aux_state_map(enum isl_aux_state **state)
}
static bool
need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
need_to_retile_as_linear(struct brw_context *brw, unsigned blt_pitch,
enum isl_tiling tiling, unsigned samples)
{
if (samples > 1)
@ -518,9 +518,9 @@ need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
if (tiling == ISL_TILING_LINEAR)
return false;
if (ALIGN(row_pitch, 512) >= 32768) {
perf_debug("row pitch %u too large to blit, falling back to untiled",
row_pitch);
if (blt_pitch >= 32768) {
perf_debug("blt pitch %u too large to blit, falling back to untiled",
blt_pitch);
return true;
}
@ -600,7 +600,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
bool is_depth_stencil =
mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT);
if (!is_depth_stencil) {
if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
if (need_to_retile_as_linear(brw, intel_miptree_blt_pitch(mt),
mt->surf.tiling, mt->surf.samples)) {
init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
@ -3577,7 +3577,7 @@ can_blit_slice(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int slice)
{
/* See intel_miptree_blit() for details on the 32k pitch limit. */
if (mt->surf.row_pitch >= 32768)
if (intel_miptree_blt_pitch(mt) >= 32768)
return false;
return true;