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crocus: convert a bunch of is_haswell into verx10 checks.

Browse source 
This just make things easier when gen8 support is added

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11507>
This commit is contained in:
Dave Airlie 2021-06-21 16:24:17 +10:00 • committed by Marge Bot
parent ae17ffedb7
commit a9c1c75e9c
6 changed files with 16 additions and 16 deletions
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10
src/gallium/drivers/crocus/crocus_draw.c
View file

@ -82,7 +82,7 @@ can_cut_index_handle_prim(struct crocus_context *ice,
const struct intel_device_info *devinfo = &screen->devinfo;
/* Haswell can do it all. */
if (devinfo->is_haswell)
if (devinfo->verx10 >= 75)
return true;
if (!can_cut_index_handle_restart_index(ice, draw))
@ -176,7 +176,7 @@ crocus_update_draw_info(struct crocus_context *ice,
ice->state.cut_index;
if (ice->state.primitive_restart != info->primitive_restart ||
ice->state.cut_index != cut_index) {
if (screen->devinfo.is_haswell)
if (screen->devinfo.verx10 >= 75)
ice->state.dirty |= CROCUS_DIRTY_GEN75_VF;
ice->state.primitive_restart = info->primitive_restart;
ice->state.cut_index = info->restart_index;
@ -261,7 +261,7 @@ crocus_indirect_draw_vbo(struct crocus_context *ice,
struct pipe_draw_indirect_info indirect = *dindirect;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
if (devinfo->is_haswell && indirect.indirect_draw_count &&
if (devinfo->verx10 >= 75 && indirect.indirect_draw_count &&
ice->state.predicate == CROCUS_PREDICATE_STATE_USE_BIT) {
/* Upload MI_PREDICATE_RESULT to GPR15.*/
screen->vtbl.load_register_reg64(batch, CS_GPR(15), MI_PREDICATE_RESULT);
@ -284,7 +284,7 @@ crocus_indirect_draw_vbo(struct crocus_context *ice,
indirect.offset += indirect.stride;
}
if (devinfo->is_haswell && indirect.indirect_draw_count &&
if (devinfo->verx10 >= 75 && indirect.indirect_draw_count &&
ice->state.predicate == CROCUS_PREDICATE_STATE_USE_BIT) {
/* Restore MI_PREDICATE_RESULT. */
screen->vtbl.load_register_reg64(batch, MI_PREDICATE_RESULT, CS_GPR(15));
@ -363,7 +363,7 @@ crocus_draw_vbo(struct pipe_context *ctx,
}
if (indirect && indirect->count_from_stream_output &&
!screen->devinfo.is_haswell) {
screen->devinfo.verx10 < 75) {
crocus_draw_vbo_get_vertex_count(ctx, info, drawid_offset, indirect);
return;
}

4
src/gallium/drivers/crocus/crocus_formats.c
View file

@ -451,7 +451,7 @@ crocus_is_format_supported(struct pipe_screen *pscreen,
return false;
/* no stencil texturing prior to haswell */
if (!devinfo->is_haswell) {
if (devinfo->verx10 < 75) {
if (pformat == PIPE_FORMAT_S8_UINT ||
pformat == PIPE_FORMAT_X24S8_UINT ||
pformat == PIPE_FORMAT_S8X24_UINT ||
@ -543,7 +543,7 @@ crocus_is_format_supported(struct pipe_screen *pscreen,
if (usage & PIPE_BIND_VERTEX_BUFFER) {
supported &= isl_format_supports_vertex_fetch(devinfo, format);
if (!devinfo->is_haswell) {
if (devinfo->verx10 < 75) {
/* W/A: Pre-Haswell, the hardware doesn't really support the formats
* we'd like to use here, so upload everything as UINT and fix it in
* the shader

2
src/gallium/drivers/crocus/crocus_pipe_control.c
View file

@ -348,7 +348,7 @@ crocus_memory_barrier(struct pipe_context *ctx, unsigned flags)
/* Typed surface messages are handled by the render cache on IVB, so we
* need to flush it too.
*/
if (!devinfo->is_haswell)
if (devinfo->verx10 < 75)
bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
for (int i = 0; i < ice->batch_count; i++) {

8
src/gallium/drivers/crocus/crocus_program.c
View file

@ -163,7 +163,7 @@ crocus_populate_sampler_prog_key_data(struct crocus_context *ice,
continue;
if (texture->base.target == PIPE_BUFFER)
continue;
if (!devinfo->is_haswell) {
if (devinfo->verx10 < 75) {
key->swizzles[s] = crocus_get_texture_swizzle(ice, texture);
}
@ -196,7 +196,7 @@ crocus_populate_sampler_prog_key_data(struct crocus_context *ice,
* request blue. Haswell can use SCS for this, but Ivybridge
* needs a shader workaround.
*/
if (!devinfo->is_haswell)
if (devinfo->verx10 < 75)
key->gather_channel_quirk_mask |= 1 << s;
break;
default:
@ -1009,7 +1009,7 @@ crocus_setup_binding_table(const struct intel_device_info *devinfo,
/* rewrite the tg4 component from green to blue before replacing the
texture index */
if (devinfo->ver == 7 && !devinfo->is_haswell) {
if (devinfo->verx10 == 70) {
if (tex->component == 1)
if (key->gather_channel_quirk_mask & (1 << tex->texture_index))
tex->component = 2;
@ -2793,7 +2793,7 @@ crocus_create_vs_state(struct pipe_context *ctx,
screen->devinfo.ver <= 5)
ish->nos |= (1ull << CROCUS_NOS_RASTERIZER);
if (!screen->devinfo.is_haswell)
if (screen->devinfo.verx10 < 75)
ish->nos |= (1ull << CROCUS_NOS_VERTEX_ELEMENTS);
if (screen->precompile) {

2
src/gallium/drivers/crocus/crocus_resource.c
View file

@ -564,7 +564,7 @@ crocus_resource_configure_aux(struct crocus_screen *screen,
/* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
* For LOD == 0, we can grow the dimensions to make it work.
*/
if (!devinfo->is_haswell ||
if (devinfo->verx10 < 75 ||
(level == 0 || ((width & 7) == 0 && (height & 3) == 0)))
res->aux.has_hiz |= 1 << level;
}

6
src/gallium/drivers/crocus/crocus_screen.c
View file

@ -239,7 +239,7 @@ crocus_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return devinfo->ver >= 7;
case PIPE_CAP_QUERY_BUFFER_OBJECT:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
return devinfo->is_haswell;
return devinfo->verx10 >= 75;
case PIPE_CAP_CULL_DISTANCE:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
@ -283,7 +283,7 @@ crocus_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return BRW_MAX_SOL_BINDINGS;
case PIPE_CAP_GLSL_FEATURE_LEVEL: {
if (devinfo->is_haswell)
if (devinfo->verx10 >= 75)
return 460;
else if (devinfo->ver >= 7)
return 420;
@ -507,7 +507,7 @@ crocus_get_shader_param(struct pipe_screen *pscreen,
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return devinfo->is_haswell ? CROCUS_MAX_TEXTURE_SAMPLERS : 16;
return (devinfo->verx10 >= 75) ? CROCUS_MAX_TEXTURE_SAMPLERS : 16;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
if (devinfo->ver >= 7 &&
(p_stage == PIPE_SHADER_FRAGMENT ||