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pan/perf: Replace bifrost+ xmls with generated ones
This commit is contained in:
Christoph Pillmayer
parent
d8bdacfce8
commit
a996aab17e
26 changed files with 3573 additions and 2085 deletions
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<!--
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Copyright © 2017-2020 ARM Limited.
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Copyright © 2021-2022 Collabora, Ltd.
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SPDX-License-Identifier: MIT
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-->
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<metrics id="TDVx">
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<category name="Job Manager" per_cpu="no">
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<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
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<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
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<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
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<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
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<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
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<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
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<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
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<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
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<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
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<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
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<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
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<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
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<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
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<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
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<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
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<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
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<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
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<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
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<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
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<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
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<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
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<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
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<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
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</category>
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<category name="Tiler" per_cpu="no">
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<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
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<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
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<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
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<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
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<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
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<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
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<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
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<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
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<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
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<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
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<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
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<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
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<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
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<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
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<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
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<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
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<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
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<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
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<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
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<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
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<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
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<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
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<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
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<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
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</category>
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<category name="Memory System" per_cpu="no">
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<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
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<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
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<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
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<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
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<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
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<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
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<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
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<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
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<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
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<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
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<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
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<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
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<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
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<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
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<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
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<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
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<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
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<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
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<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
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<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
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<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
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<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
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<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
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<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
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<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
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<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
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<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
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<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
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<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
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<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
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<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
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<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
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<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
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<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
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<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
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<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
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<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
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<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
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<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
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</category>
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<category name="Shader Core" per_cpu="no">
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<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
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<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
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<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
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<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
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<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
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<event offset="10" counter="FRAG_PARTIAL_WARPS" title="Core Warps" name="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps"/>
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<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
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<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
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<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
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<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
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<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
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<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
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<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
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<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
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<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
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<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
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<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
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<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
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<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
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<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
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<event offset="27" advanced="yes" counter="EXEC_ACTIVE" title="Core Cycles" name="Execution engine active" description="The number of cycles where the execution engine unit is processing at least one thread." units="cycles"/>
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<event offset="28" counter="EXEC_INSTR_COUNT" title="Core EE Instructions" name="Executed instructions" description="The number of instructions executed per warp." units="instructions"/>
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<event offset="29" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
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<event offset="30" advanced="yes" counter="EXEC_INSTR_STARVING" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where no new threads are available for execution." units="cycles"/>
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<event offset="31" advanced="yes" counter="ARITH_INSTR_SINGLE_FMA" title="Core EE Instructions" name="Arithmetic instructions" description="The number of instructions where the workload is a single FMA pipe arithmetic operation." units="instructions"/>
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<event offset="32" advanced="yes" counter="ARITH_INSTR_DOUBLE" title="Core EE Instructions" name="Dual Arithmetic instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe arithmetic operation." units="instructions"/>
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<event offset="33" advanced="yes" counter="ARITH_INSTR_MSG" title="Core EE Instructions" name="Arithmetic + Message instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe message operation" units="instructions"/>
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<event offset="34" advanced="yes" counter="ARITH_INSTR_MSG_ONLY" title="Core EE Instructions" name="Message instructions" description="The number of instructions where the workload is a single ADD pipe message operation, with no FMA pipe operation" units="instructions"/>
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<event offset="35" counter="TEX_MSGI_NUM_QUADS" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
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<event offset="36" counter="TEX_DFCH_NUM_PASSES" title="Core Texture Quads" name="Texture issues" description="The number of quad-width filtering passes." units="issues"/>
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<event offset="37" counter="TEX_DFCH_NUM_PASSES_MISS" title="Core Texture Quads" name="Descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests"/>
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<event offset="38" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" title="Core Texture Quads" name="Mipmapped texture issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues"/>
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<event offset="39" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" title="Core Texture Quads" name="Trilinear filtered issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues"/>
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<event offset="40" counter="TEX_TFCH_NUM_LINES_FETCHED" title="Core Texture Line Fetches" name="Line fetches" description="The number of texture line fetches from the L2 cache." units="issues"/>
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<event offset="41" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" title="Core Texture Line Fetches" name="Compressed line fetches" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues"/>
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<event offset="42" counter="TEX_TFCH_NUM_OPERATIONS" title="Core Texture Cycles" name="Cache lookups" description="The number of texture cache lookup cycles." units="requests"/>
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<event offset="43" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TSIx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_WARPS" title="Core Warps" name="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" advanced="yes" counter="EXEC_ACTIVE" title="Core Cycles" name="Execution engine active" description="The number of cycles where the execution engine unit is processing at least one thread." units="cycles"/>
|
||||
<event offset="28" counter="EXEC_INSTR_COUNT" title="Core EE Instructions" name="Executed instructions" description="The number of instructions executed per warp." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="30" advanced="yes" counter="EXEC_INSTR_STARVING" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where no new threads are available for execution." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="ARITH_INSTR_SINGLE_FMA" title="Core EE Instructions" name="Arithmetic instructions" description="The number of instructions where the workload is a single FMA pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="ARITH_INSTR_DOUBLE" title="Core EE Instructions" name="Dual Arithmetic instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="33" advanced="yes" counter="ARITH_INSTR_MSG" title="Core EE Instructions" name="Arithmetic + Message instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe message operation" units="instructions"/>
|
||||
<event offset="34" advanced="yes" counter="ARITH_INSTR_MSG_ONLY" title="Core EE Instructions" name="Message instructions" description="The number of instructions where the workload is a single ADD pipe message operation, with no FMA pipe operation" units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_QUADS" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
|
||||
<event offset="36" counter="TEX_DFCH_NUM_PASSES" title="Core Texture Quads" name="Texture issues" description="The number of quad-width filtering passes." units="issues"/>
|
||||
<event offset="37" counter="TEX_DFCH_NUM_PASSES_MISS" title="Core Texture Quads" name="Descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests"/>
|
||||
<event offset="38" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" title="Core Texture Quads" name="Mipmapped texture issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues"/>
|
||||
<event offset="39" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" title="Core Texture Quads" name="Trilinear filtered issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues"/>
|
||||
<event offset="40" counter="TEX_TFCH_NUM_LINES_FETCHED" title="Core Texture Line Fetches" name="Line fetches" description="The number of texture line fetches from the L2 cache." units="issues"/>
|
||||
<event offset="41" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" title="Core Texture Line Fetches" name="Compressed line fetches" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues"/>
|
||||
<event offset="42" counter="TEX_TFCH_NUM_OPERATIONS" title="Core Texture Cycles" name="Cache lookups" description="The number of texture cache lookup cycles." units="requests"/>
|
||||
<event offset="43" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TGOx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_WARPS" title="Core Warps" name="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="17" counter="WARP_REG_SIZE_64" title="Core Warps" name="All register warps" description="The number of warps that require more than 32 registers." units="warps"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="21" counter="FULL_QUAD_WARPS" title="Core Warps" name="Full quad warps" description="The number of warps that are fully populated with quads." units="warps"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" advanced="yes" counter="EXEC_ACTIVE" title="Core Cycles" name="Execution engine active" description="The number of cycles where the execution engine unit is processing at least one thread." units="cycles"/>
|
||||
<event offset="28" counter="EXEC_INSTR_COUNT" title="Core EE Instructions" name="Executed instructions" description="The number of instructions executed per warp." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="30" advanced="yes" counter="EXEC_INSTR_STARVING" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where no new threads are available for execution." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="ARITH_INSTR_SINGLE_FMA" title="Core EE Instructions" name="Arithmetic instructions" description="The number of instructions where the workload is a single FMA pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="ARITH_INSTR_DOUBLE" title="Core EE Instructions" name="Dual Arithmetic instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="33" advanced="yes" counter="ARITH_INSTR_MSG" title="Core EE Instructions" name="Arithmetic + Message instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe message operation" units="instructions"/>
|
||||
<event offset="34" advanced="yes" counter="ARITH_INSTR_MSG_ONLY" title="Core EE Instructions" name="Message instructions" description="The number of instructions where the workload is a single ADD pipe message operation, with no FMA pipe operation" units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_QUADS" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
|
||||
<event offset="36" counter="TEX_DFCH_NUM_PASSES" title="Core Texture Quads" name="Texture issues" description="The number of quad-width filtering passes." units="issues"/>
|
||||
<event offset="37" counter="TEX_DFCH_NUM_PASSES_MISS" title="Core Texture Quads" name="Descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests"/>
|
||||
<event offset="38" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" title="Core Texture Quads" name="Mipmapped texture issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues"/>
|
||||
<event offset="39" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" title="Core Texture Quads" name="Trilinear filtered issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues"/>
|
||||
<event offset="40" counter="TEX_TFCH_NUM_LINES_FETCHED" title="Core Texture Line Fetches" name="Line fetches" description="The number of texture line fetches from the L2 cache." units="issues"/>
|
||||
<event offset="41" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" title="Core Texture Line Fetches" name="Compressed line fetches" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues"/>
|
||||
<event offset="42" counter="TEX_TFCH_NUM_OPERATIONS" title="Core Texture Cycles" name="Cache lookups" description="The number of texture cache lookup cycles." units="requests"/>
|
||||
<event offset="43" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TNAx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES_OUT" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_QUADS_RAST" title="Core Quads" name="Partial rasterized quads" description="The number of partially-rasterized fragment quads created." units="quads"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="17" counter="WARP_REG_SIZE_64" title="Core Warps" name="All register warps" description="The number of warps that require more than 32 registers." units="warps"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="21" counter="FULL_QUAD_WARPS" title="Core Warps" name="Full quad warps" description="The number of warps that are fully populated with quads." units="warps"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" counter="EXEC_INSTR_FMA" title="Core PU Instructions" name="FMA instructions" description="The number of instructions issued to the FMA pipe." units="instructions"/>
|
||||
<event offset="28" counter="EXEC_INSTR_CVT" title="Core PU Instructions" name="CVT instructions" description="The number of instructions issued to the CVT pipe." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_SFU" title="Core PU Instructions" name="SFU instructions" description="The number of instructions issued to the SFU pipe." units="instructions"/>
|
||||
<event offset="30" counter="EXEC_INSTR_MSG" title="Core PU Instructions" name="Message instructions" description="The number of instructions issued to the MSG pipe." units="instructions"/>
|
||||
<event offset="31" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="EXEC_ICACHE_MISS" title="Core PU Instructions" name="Instruction cache misses" description="The number of instruction cache misses." units="requests"/>
|
||||
<event offset="33" advanced="yes" counter="EXEC_STARVE_ARITH" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where the processing unit is starved of work." units="cycles"/>
|
||||
<event offset="34" counter="CALL_BLEND_SHADER" title="Core PU Instructions" name="Blend shader calls" description="The number of blend shader invocations executed." units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_FLITS" title="Texture Bus" name="Input beats" description="The number of texture request message data beats." units="beats"/>
|
||||
<event offset="36" counter="TEX_DFCH_CLK_STALLED" title="Core Texture Stalls" name="Descriptor stall cycles" description="The number of cycles where a quad is stalled on texture descriptor fetch." units="cycles"/>
|
||||
<event offset="37" counter="TEX_TFCH_CLK_STALLED" title="Core Texture Stalls" name="Fetch queue stall cycles" description="The number of cycles where a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles"/>
|
||||
<event offset="38" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" title="Core Texture Stalls" name="Filtering unit stall cycles" description="The number of cycles where the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles"/>
|
||||
<event offset="39" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="40" counter="TEX_FILT_NUM_FXR_OPERATIONS" title="Core Texture Cycles" name="4x bilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement nearest or bilinear filtering." units="cycles"/>
|
||||
<event offset="41" counter="TEX_FILT_NUM_FST_OPERATIONS" title="Core Texture Cycles" name="2x trilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement trilinear filtering." units="cycles"/>
|
||||
<event offset="42" counter="TEX_MSGO_NUM_MSG" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
|
||||
<event offset="43" counter="TEX_MSGO_NUM_FLITS" title="Texture Bus" name="Output beats" description="The number of texture response message data beats." units="beats"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TOTx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES_OUT" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_QUADS_RAST" title="Core Quads" name="Partial rasterized quads" description="The number of partially-rasterized fragment quads created." units="quads"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="17" counter="WARP_REG_SIZE_64" title="Core Warps" name="All register warps" description="The number of warps that require more than 32 registers." units="warps"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="21" counter="FULL_QUAD_WARPS" title="Core Warps" name="Full quad warps" description="The number of warps that are fully populated with quads." units="warps"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" counter="EXEC_INSTR_FMA" title="Core PU Instructions" name="FMA instructions" description="The number of instructions issued to the FMA pipe." units="instructions"/>
|
||||
<event offset="28" counter="EXEC_INSTR_CVT" title="Core PU Instructions" name="CVT instructions" description="The number of instructions issued to the CVT pipe." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_SFU" title="Core PU Instructions" name="SFU instructions" description="The number of instructions issued to the SFU pipe." units="instructions"/>
|
||||
<event offset="30" counter="EXEC_INSTR_MSG" title="Core PU Instructions" name="Message instructions" description="The number of instructions issued to the MSG pipe." units="instructions"/>
|
||||
<event offset="31" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="EXEC_ICACHE_MISS" title="Core PU Instructions" name="Instruction cache misses" description="The number of instruction cache misses." units="requests"/>
|
||||
<event offset="33" advanced="yes" counter="EXEC_STARVE_ARITH" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where the processing unit is starved of work." units="cycles"/>
|
||||
<event offset="34" counter="CALL_BLEND_SHADER" title="Core PU Instructions" name="Blend shader calls" description="The number of blend shader invocations executed." units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_FLITS" title="Texture Bus" name="Input beats" description="The number of texture request message data beats." units="beats"/>
|
||||
<event offset="36" counter="TEX_DFCH_CLK_STALLED" title="Core Texture Stalls" name="Descriptor stall cycles" description="The number of cycles where a quad is stalled on texture descriptor fetch." units="cycles"/>
|
||||
<event offset="37" counter="TEX_TFCH_CLK_STALLED" title="Core Texture Stalls" name="Fetch queue stall cycles" description="The number of cycles where a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles"/>
|
||||
<event offset="38" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" title="Core Texture Stalls" name="Filtering unit stall cycles" description="The number of cycles where the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles"/>
|
||||
<event offset="39" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="40" counter="TEX_FILT_NUM_FXR_OPERATIONS" title="Core Texture Cycles" name="4x bilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement nearest or bilinear filtering." units="cycles"/>
|
||||
<event offset="41" counter="TEX_FILT_NUM_FST_OPERATIONS" title="Core Texture Cycles" name="2x trilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement trilinear filtering." units="cycles"/>
|
||||
<event offset="42" counter="TEX_MSGO_NUM_MSG" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
|
||||
<event offset="43" counter="TEX_MSGO_NUM_FLITS" title="Texture Bus" name="Output beats" description="The number of texture response message data beats." units="beats"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" counter="SHADER_CORE_ACTIVE" title="Core Cycles" name="Any active" description="The number of cycles where the shader core is processing either a non-fragment workload or a fragment workload." units="cycles"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TMIx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_WARPS" title="Core Warps" name="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" advanced="yes" counter="EXEC_ACTIVE" title="Core Cycles" name="Execution engine active" description="The number of cycles where the execution engine unit is processing at least one thread." units="cycles"/>
|
||||
<event offset="28" counter="EXEC_INSTR_COUNT" title="Core EE Instructions" name="Executed instructions" description="The number of instructions executed per warp." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="30" advanced="yes" counter="EXEC_INSTR_STARVING" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where no new threads are available for execution." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="ARITH_INSTR_SINGLE_FMA" title="Core EE Instructions" name="Arithmetic instructions" description="The number of instructions where the workload is a single FMA pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="ARITH_INSTR_DOUBLE" title="Core EE Instructions" name="Dual Arithmetic instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="33" advanced="yes" counter="ARITH_INSTR_MSG" title="Core EE Instructions" name="Arithmetic + Message instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe message operation" units="instructions"/>
|
||||
<event offset="34" advanced="yes" counter="ARITH_INSTR_MSG_ONLY" title="Core EE Instructions" name="Message instructions" description="The number of instructions where the workload is a single ADD pipe message operation, with no FMA pipe operation" units="instructions"/>
|
||||
<event offset="35" counter="TEX_INSTR" title="Core Texture Requests" name="Texture requests" description="The number of thread-width texture operations processed." units="instructions"/>
|
||||
<event offset="36" counter="TEX_INSTR_MIPMAP" title="Core Texture Requests" name="Mipmapped texture request" description="The number of texture operations that act on a mipmapped texture." units="instructions"/>
|
||||
<event offset="37" counter="TEX_INSTR_COMPRESSED" title="Core Texture Requests" name="Compressed texture requests" description="The number of texture operations acting on a compressed texture." units="instructions"/>
|
||||
<event offset="38" counter="TEX_INSTR_3D" title="Core Texture Requests" name="3D texture requests" description="The number of texture operations acting on a 3D texture." units="instructions"/>
|
||||
<event offset="39" counter="TEX_INSTR_TRILINEAR" title="Core Texture Requests" name="Trilinear filtered requests" description="The number of texture operations using a trilinear texture filter." units="instructions"/>
|
||||
<event offset="40" counter="TEX_COORD_ISSUE" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="41" advanced="yes" counter="TEX_COORD_STALL" title="Core Texture Cycles" name="Coordinate stall cycles" description="The number of clock cycles where threads are stalled at the texel coordinate calculation stage." units="cycles"/>
|
||||
<event offset="42" advanced="yes" counter="TEX_STARVE_CACHE" title="Core Texture Cycles" name="Line fill stall cycles" description="The number of clock cycles where at least one thread is waiting for data from the texture cache, but no lookup is completed." units="cycles"/>
|
||||
<event offset="43" advanced="yes" counter="TEX_STARVE_FILTER" title="Core Texture Cycles" name="Partial data stall cycles" description="The number of clock cycles where at least one thread fetched some data from the texture cache, but no filtering operation is started." units="cycles"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC" title="Core Writes" name="Load/store write beats" description="The number of write beats sent by the load/store unit." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" advanced="yes" counter="BEATS_WR_OTHER" title="Core Writes" name="Other write beats" description="The number of write beats sent by any unit that is not specifically identified." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="THEx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_WARPS" title="Core Warps" name="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" advanced="yes" counter="EXEC_ACTIVE" title="Core Cycles" name="Execution engine active" description="The number of cycles where the execution engine unit is processing at least one thread." units="cycles"/>
|
||||
<event offset="28" counter="EXEC_INSTR_COUNT" title="Core EE Instructions" name="Executed instructions" description="The number of instructions executed per warp." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="30" advanced="yes" counter="EXEC_INSTR_STARVING" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where no new threads are available for execution." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="ARITH_INSTR_SINGLE_FMA" title="Core EE Instructions" name="Arithmetic instructions" description="The number of instructions where the workload is a single FMA pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="ARITH_INSTR_DOUBLE" title="Core EE Instructions" name="Dual Arithmetic instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="33" advanced="yes" counter="ARITH_INSTR_MSG" title="Core EE Instructions" name="Arithmetic + Message instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe message operation" units="instructions"/>
|
||||
<event offset="34" advanced="yes" counter="ARITH_INSTR_MSG_ONLY" title="Core EE Instructions" name="Message instructions" description="The number of instructions where the workload is a single ADD pipe message operation, with no FMA pipe operation" units="instructions"/>
|
||||
<event offset="35" counter="TEX_INSTR" title="Core Texture Requests" name="Texture requests" description="The number of thread-width texture operations processed." units="instructions"/>
|
||||
<event offset="36" counter="TEX_INSTR_MIPMAP" title="Core Texture Requests" name="Mipmapped texture request" description="The number of texture operations that act on a mipmapped texture." units="instructions"/>
|
||||
<event offset="37" counter="TEX_INSTR_COMPRESSED" title="Core Texture Requests" name="Compressed texture requests" description="The number of texture operations acting on a compressed texture." units="instructions"/>
|
||||
<event offset="38" counter="TEX_INSTR_3D" title="Core Texture Requests" name="3D texture requests" description="The number of texture operations acting on a 3D texture." units="instructions"/>
|
||||
<event offset="39" counter="TEX_INSTR_TRILINEAR" title="Core Texture Requests" name="Trilinear filtered requests" description="The number of texture operations using a trilinear texture filter." units="instructions"/>
|
||||
<event offset="40" counter="TEX_COORD_ISSUE" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="41" advanced="yes" counter="TEX_COORD_STALL" title="Core Texture Cycles" name="Coordinate stall cycles" description="The number of clock cycles where threads are stalled at the texel coordinate calculation stage." units="cycles"/>
|
||||
<event offset="42" advanced="yes" counter="TEX_STARVE_CACHE" title="Core Texture Cycles" name="Line fill stall cycles" description="The number of clock cycles where at least one thread is waiting for data from the texture cache, but no lookup is completed." units="cycles"/>
|
||||
<event offset="43" advanced="yes" counter="TEX_STARVE_FILTER" title="Core Texture Cycles" name="Partial data stall cycles" description="The number of clock cycles where at least one thread fetched some data from the texture cache, but no filtering operation is started." units="cycles"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC" title="Core Writes" name="Load/store write beats" description="The number of write beats sent by the load/store unit." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" advanced="yes" counter="BEATS_WR_OTHER" title="Core Writes" name="Other write beats" description="The number of write beats sent by any unit that is not specifically identified." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TNOx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_WARPS" title="Core Warps" name="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="17" counter="WARP_REG_SIZE_64" title="Core Warps" name="All register warps" description="The number of warps that require more than 32 registers." units="warps"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="21" counter="FULL_QUAD_WARPS" title="Core Warps" name="Full quad warps" description="The number of warps that are fully populated with quads." units="warps"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" advanced="yes" counter="EXEC_ACTIVE" title="Core Cycles" name="Execution engine active" description="The number of cycles where the execution engine unit is processing at least one thread." units="cycles"/>
|
||||
<event offset="28" counter="EXEC_INSTR_COUNT" title="Core EE Instructions" name="Executed instructions" description="The number of instructions executed per warp." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="30" advanced="yes" counter="EXEC_INSTR_STARVING" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where no new threads are available for execution." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="ARITH_INSTR_SINGLE_FMA" title="Core EE Instructions" name="Arithmetic instructions" description="The number of instructions where the workload is a single FMA pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="ARITH_INSTR_DOUBLE" title="Core EE Instructions" name="Dual Arithmetic instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe arithmetic operation." units="instructions"/>
|
||||
<event offset="33" advanced="yes" counter="ARITH_INSTR_MSG" title="Core EE Instructions" name="Arithmetic + Message instructions" description="The number of instructions where the workload is one FMA pipe arithmetic operation and one ADD pipe message operation" units="instructions"/>
|
||||
<event offset="34" advanced="yes" counter="ARITH_INSTR_MSG_ONLY" title="Core EE Instructions" name="Message instructions" description="The number of instructions where the workload is a single ADD pipe message operation, with no FMA pipe operation" units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_QUADS" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
|
||||
<event offset="36" counter="TEX_DFCH_NUM_PASSES" title="Core Texture Quads" name="Texture issues" description="The number of quad-width filtering passes." units="issues"/>
|
||||
<event offset="37" counter="TEX_DFCH_NUM_PASSES_MISS" title="Core Texture Quads" name="Descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests"/>
|
||||
<event offset="38" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" title="Core Texture Quads" name="Mipmapped texture issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues"/>
|
||||
<event offset="39" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" title="Core Texture Quads" name="Trilinear filtered issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues"/>
|
||||
<event offset="40" counter="TEX_TFCH_NUM_LINES_FETCHED" title="Core Texture Line Fetches" name="Line fetches" description="The number of texture line fetches from the L2 cache." units="issues"/>
|
||||
<event offset="41" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" title="Core Texture Line Fetches" name="Compressed line fetches" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues"/>
|
||||
<event offset="42" counter="TEX_TFCH_NUM_OPERATIONS" title="Core Texture Cycles" name="Cache lookups" description="The number of texture cache lookup cycles." units="requests"/>
|
||||
<event offset="43" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TTRx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES_OUT" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_QUADS_RAST" title="Core Quads" name="Partial rasterized quads" description="The number of partially-rasterized fragment quads created." units="quads"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="17" counter="WARP_REG_SIZE_64" title="Core Warps" name="All register warps" description="The number of warps that require more than 32 registers." units="warps"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="21" counter="FULL_QUAD_WARPS" title="Core Warps" name="Full quad warps" description="The number of warps that are fully populated with quads." units="warps"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" counter="EXEC_INSTR_FMA" title="Core PU Instructions" name="FMA instructions" description="The number of instructions issued to the FMA pipe." units="instructions"/>
|
||||
<event offset="28" counter="EXEC_INSTR_CVT" title="Core PU Instructions" name="CVT instructions" description="The number of instructions issued to the CVT pipe." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_SFU" title="Core PU Instructions" name="SFU instructions" description="The number of instructions issued to the SFU pipe." units="instructions"/>
|
||||
<event offset="30" counter="EXEC_INSTR_MSG" title="Core PU Instructions" name="Message instructions" description="The number of instructions issued to the MSG pipe." units="instructions"/>
|
||||
<event offset="31" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="EXEC_ICACHE_MISS" title="Core PU Instructions" name="Instruction cache misses" description="The number of instruction cache misses." units="requests"/>
|
||||
<event offset="33" advanced="yes" counter="EXEC_STARVE_ARITH" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where the processing unit is starved of work." units="cycles"/>
|
||||
<event offset="34" counter="CALL_BLEND_SHADER" title="Core PU Instructions" name="Blend shader calls" description="The number of blend shader invocations executed." units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_FLITS" title="Texture Bus" name="Input beats" description="The number of texture request message data beats." units="beats"/>
|
||||
<event offset="36" counter="TEX_DFCH_CLK_STALLED" title="Core Texture Stalls" name="Descriptor stall cycles" description="The number of cycles where a quad is stalled on texture descriptor fetch." units="cycles"/>
|
||||
<event offset="37" counter="TEX_TFCH_CLK_STALLED" title="Core Texture Stalls" name="Fetch queue stall cycles" description="The number of cycles where a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles"/>
|
||||
<event offset="38" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" title="Core Texture Stalls" name="Filtering unit stall cycles" description="The number of cycles where the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles"/>
|
||||
<event offset="39" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="40" counter="TEX_FILT_NUM_FXR_OPERATIONS" title="Core Texture Cycles" name="4x bilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement nearest or bilinear filtering." units="cycles"/>
|
||||
<event offset="41" counter="TEX_FILT_NUM_FST_OPERATIONS" title="Core Texture Cycles" name="2x trilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement trilinear filtering." units="cycles"/>
|
||||
<event offset="42" counter="TEX_MSGO_NUM_MSG" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
|
||||
<event offset="43" counter="TEX_MSGO_NUM_FLITS" title="Texture Bus" name="Output beats" description="The number of texture response message data beats." units="beats"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" advanced="yes" counter="ARITH_INSTR_FP_MUL" title="Core EE Instructions" name="Multiplier instructions" description="The number of instructions where the workload uses floating-point multiplier hardware." units="instructions"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2017-2020 ARM Limited.
|
||||
Copyright © 2021-2022 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
<metrics id="TBOx">
|
||||
<category name="Job Manager" per_cpu="no">
|
||||
<event offset="6" counter="GPU_ACTIVE" title="GPU Cycles" name="GPU active" description="The number of cycles where the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="IRQ_ACTIVE" title="GPU Cycles" name="Interrupt active" description="The number of cycles where the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="JS0_JOBS" title="GPU Jobs" name="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs"/>
|
||||
<event offset="9" counter="JS0_TASKS" title="GPU Tasks" name="Fragment tasks" description="The number of 32x32 pixel tasks processed by the GPU fragment queue." units="tasks"/>
|
||||
<event offset="10" counter="JS0_ACTIVE" title="GPU Cycles" name="Fragment queue active" description="The number of cycles where work is queued for processing in the GPU fragment queue." units="cycles"/>
|
||||
<event offset="12" advanced="yes" counter="JS0_WAIT_READ" title="GPU Wait Cycles" name="Fragment descriptor reads cycles" description="The number of cycles where queued fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="JS0_WAIT_ISSUE" title="GPU Wait Cycles" name="Fragment job issue cycles" description="The number of cycles where queued fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="14" advanced="yes" counter="JS0_WAIT_DEPEND" title="GPU Wait Cycles" name="Fragment job dependency cycles" description="The number of cycles where queued fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="JS0_WAIT_FINISH" title="GPU Wait Cycles" name="Fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued fragment work to complete." units="cycles"/>
|
||||
<event offset="16" advanced="yes" counter="JS1_JOBS" title="GPU Jobs" name="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs"/>
|
||||
<event offset="17" advanced="yes" counter="JS1_TASKS" title="GPU Tasks" name="Non-fragment tasks" description="The number of tasks processed by the GPU non-fragment queue." units="tasks"/>
|
||||
<event offset="18" counter="JS1_ACTIVE" title="GPU Cycles" name="Non-fragment queue active" description="The number of cycles where work is queued in the GPU non-fragment queue." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="JS1_WAIT_READ" title="GPU Wait Cycles" name="Non-fragment descriptor read cycles" description="The number number of cycles where queued non-fragment work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="JS1_WAIT_ISSUE" title="GPU Wait Cycles" name="Non-fragment job issue cycles" description="The number of cycles where queued non-fragment work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="JS1_WAIT_DEPEND" title="GPU Wait Cycles" name="Non-fragment job dependency cycles" description="The number of cycles where queued non-fragment work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="JS1_WAIT_FINISH" title="GPU Wait Cycles" name="Non-fragment job finish cycles" description="The number of cycles where the GPU is waiting for issued non-fragment work to complete." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="JS2_JOBS" title="GPU Jobs" name="Reserved jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs"/>
|
||||
<event offset="25" advanced="yes" counter="JS2_TASKS" title="GPU Tasks" name="Reserved tasks" description="The number of tasks processed by the GPU reserved queue." units="tasks"/>
|
||||
<event offset="26" advanced="yes" counter="JS2_ACTIVE" title="GPU Cycles" name="Reserved queue active" description="The number of cycles where work is queued in the GPU reserved queue." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="JS2_WAIT_READ" title="GPU Wait Cycles" name="Reserved descriptor read cycles" description="The number of cycles where queued reserved work is waiting for a descriptor load." units="cycles"/>
|
||||
<event offset="29" advanced="yes" counter="JS2_WAIT_ISSUE" title="GPU Wait Cycles" name="Reserved job issue cycles" description="The number of cycles where queued reserved work is waiting for an available processor." units="cycles"/>
|
||||
<event offset="30" advanced="yes" counter="JS2_WAIT_DEPEND" title="GPU Wait Cycles" name="Reserved job dependency cycles" description="The number of cycles where queued reserved work is waiting for dependent work to complete." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="JS2_WAIT_FINISH" title="GPU Wait Cycles" name="Reserved job finish cycles" description="The number of cycles where the GPU is waiting for issued reserved work to complete." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" counter="TILER_ACTIVE" title="GPU Cycles" name="Tiler active" description="The number of cycles where the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Input Primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Input Primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Input Primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" counter="FRONT_FACING" title="Visible Primitives" name="Front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" counter="BACK_FACING" title="Visible Primitives" name="Back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Primitive Culling" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Primitive Culling" name="Facing and XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Primitive Culling" name="Z plane test culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Primitive Culling" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Tiler L2 Accesses" name="Read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE" title="Tiler L2 Accesses" name="Write beats" description="The number of internal bus data write cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Tiler Shading Requests" name="Position shading requests" description="The number of position shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Tiler Cycles" name="Position shading stall cycles" description="The number of cycles where the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Tiler Cycles" name="Position FIFO full cycles" description="The number of cycles where the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Tiler Vertex Cache" name="Position cache hits" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Tiler Vertex Cache" name="Position cache misses" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="31" advanced="yes" counter="VFETCH_STALL" title="Tiler Cycles" name="Primitive assembly busy stall cycles" description="The number of cycles where the tiler is stalled waiting for primitive assembly." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Tiler Vertex Cache" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Tiler Vertex Cache" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Tiler Shading Requests" name="Varying shading requests" description="The number of varying shading requests in the IDVS flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Tiler Cycles" name="Varying shading stall cycles" description="The number of cycles where the tiler has a stalled varying shading request." units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_AXI_ID_STALL" title="Tiler Cycles" name="Write buffer transaction stall cycles" description="The number of cycles where the tiler write buffer can not send data because it has no available write IDs." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_AXI_STALL" title="Tiler Cycles" name="Write buffer write stall cycles" description="The number of cycles where the tiler write buffer can not send data because the bus is not ready." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU Stage 1 Translations" name="MMU lookups" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2 Cache Requests" name="Read requests" description="The number of L2 cache read requests from internal masters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Read stall cycles" description="The number of cycles L2 cache read requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2 Cache Requests" name="Write requests" description="The number of L2 cache write requests from internal masters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Write stall cycles" description="The number of cycles where L2 cache write requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2 Cache Requests" name="Snoop requests" description="The number of L2 snoop requests from internal masters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2 Cache Stall Cycles" name="Snoop stall cycles" description="The number of cycles where L2 cache snoop requests from internal masters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2 Cache Requests" name="L1 read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2 Cache Stall Cycles" name="L1 read stall cycles" description="The number of cycles where L1 cache read requests sent by the L2 cache to an internal master are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2 Cache Requests" name="L1 write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal master." units="requests"/>
|
||||
<event offset="25" counter="L2_ANY_LOOKUP" title="L2 Cache Lookups" name="Any lookup" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="L2 Cache Lookups" name="Read lookup" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="L2 Cache Lookups" name="Write lookup" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2 Cache Lookups" name="External snoop lookups" description="The number of coherency snoop lookups performed that were triggered by an external master." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="External Bus Accesses" name="Read transaction" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="External Bus Accesses" name="ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="External Bus Accesses" name="ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="External Bus Beats" name="Read beat" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="External Bus Stalls" name="Read stall cycles" description="The number of cycles where a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" counter="L2_EXT_AR_CNT_Q1" title="External Bus Outstanding Reads" name="0-25% outstanding" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" counter="L2_EXT_AR_CNT_Q2" title="External Bus Outstanding Reads" name="25-50% outstanding" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" counter="L2_EXT_AR_CNT_Q3" title="External Bus Outstanding Reads" name="50-75% outstanding" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="External Bus Read Latency" name="0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="External Bus Read Latency" name="128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="External Bus Read Latency" name="192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="External Bus Read Latency" name="256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="External Bus Read Latency" name="320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="External Bus Accesses" name="Write transaction" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="External Bus Accesses" name="WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="External Bus Accesses" name="WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="External Bus Accesses" name="WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="External Bus Accesses" name="WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="External Bus Beats" name="Write beat" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="External Bus Stalls" name="Write stall cycles" description="The number of cycles where a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" counter="L2_EXT_AW_CNT_Q1" title="External Bus Outstanding Writes" name="0-25% outstanding" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" counter="L2_EXT_AW_CNT_Q2" title="External Bus Outstanding Writes" name="25-50% outstanding" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" counter="L2_EXT_AW_CNT_Q3" title="External Bus Outstanding Writes" name="50-75% outstanding" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="External Bus Accesses" name="Snoop transactions" description="The number of coherency snoops triggered by external masters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="External Bus Stalls" name="Snoop stall cycles" description="The number of cycles where a coherency snoop triggered by external master is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Core Cycles" name="Fragment active" description="The number of cycles where the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES_OUT" title="Core Primitives" name="Read primitives" description="The number of primitives read from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Core Primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Core Cycles" name="Fragment FPKB active" description="The number of cycles where at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Core Warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_QUADS_RAST" title="Core Quads" name="Partial rasterized quads" description="The number of partially-rasterized fragment quads created." units="quads"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Core Quads" name="Rasterized quads" description="The number of quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Core Quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Core Quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Core Quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Core Quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Core Quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="17" counter="WARP_REG_SIZE_64" title="Core Warps" name="All register warps" description="The number of warps that require more than 32 registers." units="warps"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Core Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Core Tiles" name="Constant tiles killed" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Core Quads" name="FPK occluder quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="21" counter="FULL_QUAD_WARPS" title="Core Warps" name="Full quad warps" description="The number of warps that are fully populated with quads." units="warps"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Core Cycles" name="Non-fragment active" description="The number of cycles where the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Core Tasks" name="Non-fragment tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Core Warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="Core Starvation Cycles" name="Non-fragment starvation cycles" description="The number of cycles where the shader core is processing a non-fragment workload and there are no new threads available for execution." units="cycles"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Core Cycles" name="Execution core active" description="The number of cycles where the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" counter="EXEC_INSTR_FMA" title="Core PU Instructions" name="FMA instructions" description="The number of instructions issued to the FMA pipe." units="instructions"/>
|
||||
<event offset="28" counter="EXEC_INSTR_CVT" title="Core PU Instructions" name="CVT instructions" description="The number of instructions issued to the CVT pipe." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_SFU" title="Core PU Instructions" name="SFU instructions" description="The number of instructions issued to the SFU pipe." units="instructions"/>
|
||||
<event offset="30" counter="EXEC_INSTR_MSG" title="Core PU Instructions" name="Message instructions" description="The number of instructions issued to the MSG pipe." units="instructions"/>
|
||||
<event offset="31" counter="EXEC_INSTR_DIVERGED" title="Core EE Instructions" name="Diverged instructions" description="The number of instructions executed per warp, that have control flow divergence." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="EXEC_ICACHE_MISS" title="Core PU Instructions" name="Instruction cache misses" description="The number of instruction cache misses." units="requests"/>
|
||||
<event offset="33" advanced="yes" counter="EXEC_STARVE_ARITH" title="Core Starvation Cycles" name="Execution engine starvation cycles" description="The number of cycles where the processing unit is starved of work." units="cycles"/>
|
||||
<event offset="34" counter="CALL_BLEND_SHADER" title="Core PU Instructions" name="Blend shader calls" description="The number of blend shader invocations executed." units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_FLITS" title="Texture Bus" name="Input beats" description="The number of texture request message data beats." units="beats"/>
|
||||
<event offset="36" counter="TEX_DFCH_CLK_STALLED" title="Core Texture Stalls" name="Descriptor stall cycles" description="The number of cycles where a quad is stalled on texture descriptor fetch." units="cycles"/>
|
||||
<event offset="37" counter="TEX_TFCH_CLK_STALLED" title="Core Texture Stalls" name="Fetch queue stall cycles" description="The number of cycles where a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles"/>
|
||||
<event offset="38" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" title="Core Texture Stalls" name="Filtering unit stall cycles" description="The number of cycles where the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles"/>
|
||||
<event offset="39" counter="TEX_FILT_NUM_OPERATIONS" title="Core Texture Cycles" name="Texturing active" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="40" counter="TEX_FILT_NUM_FXR_OPERATIONS" title="Core Texture Cycles" name="4x bilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement nearest or bilinear filtering." units="cycles"/>
|
||||
<event offset="41" counter="TEX_FILT_NUM_FST_OPERATIONS" title="Core Texture Cycles" name="2x trilinear filtering active" description="The number of cycles where the filtering unit uses the 4x path to implement trilinear filtering." units="cycles"/>
|
||||
<event offset="42" counter="TEX_MSGO_NUM_MSG" title="Core Texture Quads" name="Texture requests" description="The number of quad-width texture operations processed by the texture unit." units="quads"/>
|
||||
<event offset="43" counter="TEX_MSGO_NUM_FLITS" title="Texture Bus" name="Output beats" description="The number of texture response message data beats." units="beats"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Core Load/Store Cycles" name="Full read cycles" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Core Load/Store Cycles" name="Partial read cycles" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Core Load/Store Cycles" name="Full write cycles" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Core Load/Store Cycles" name="Partial write cycles" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Core Load/Store Cycles" name="Atomic access cycles" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Core Varying Requests" name="Interpolation requests" description="The number of warp-width interpolation operations processed by the varying unit." units="instructions"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="Core Varying Cycles" name="32-bit interpolation active" description="The number of 32-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="Core Varying Cycles" name="16-bit interpolation active" description="The number of 16-bit interpolation cycles processed by the varying unit." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Core Attribute Requests" name="Attribute requests" description="The number of instructions executed by the attribute unit." units="instructions"/>
|
||||
<event offset="53" counter="SHADER_CORE_ACTIVE" title="Core Cycles" name="Any active" description="The number of cycles where the shader core is processing either a non-fragment workload or a fragment workload." units="cycles"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Core L2 Reads" name="Fragment L2 read beats" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Core L2 Reads" name="Fragment external read beats" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Core L2 Reads" name="Load/store L2 read beats" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Core L2 Reads" name="Load/store external read beats" description="The number of read beats received by the load/store unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Core L2 Reads" name="Texture L2 read beats" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Core L2 Reads" name="Texture external read beats" description="The number of read beats received by the texture unit that required an external memory access due to an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Core L2 Reads" name="Other L2 read beats" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Core Writes" name="Load/store other write beats" description="The number of write beats by the load/store unit that are due to any reason other than writeback." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Core Writes" name="Tile buffer write beats" description="The number of write beats sent by the tile buffer writeback unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Core Writes" name="Load/store writeback write beats" description="The number of write beats by the load/store unit that are due to writeback." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2025 Arm, Ltd.
|
||||
Author: Lukas Zapolskas <lukas.zapolskas@arm.com>
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="TVAx" arch_major="10">
|
||||
<category name="CSF" per_cpu="no">
|
||||
<event offset="4" counter="GPU_ACTIVE" title="GPU active" name="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="MCU_ACTIVE" title="MCU active" name="MCU active cycles" description="The number of cycles when the CSF front-end MCU is actively processing." units="cycles"/>
|
||||
<event offset="6" counter="GPU_ITER_ACTIVE" title="Any queue active" name="Any queue active cycles" description="The number of cycles when any GPU queue is active." units="cycles"/>
|
||||
<event offset="10" advanced="yes" counter="IRQ_ACTIVE" title="GPU interrupt active" name="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles"/>
|
||||
<event offset="11" advanced="yes" counter="GPU_IRQ_COUNT" title="GPU interrupts" name="GPU interrupts" description="The number of interrupts raised by the GPU to the CPU." units="interrupts"/>
|
||||
<event offset="12" advanced="yes" counter="CACHE_FLUSH_CYCLES" title="L2 cache flush" name="L2 cache flush cycles" description="The number of cycles spent flushing GPU L2 caches." units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="CACHE_FLUSH" title="L2 cache flushes" name="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests"/>
|
||||
<event offset="16" counter="ITER_TILER_ACTIVE" title="Vertex queued" name="Vertex work queued cycles" description="The number of cycles that the vertex shading queue has work queued." units="cycles"/>
|
||||
<event offset="17" advanced="yes" counter="ITER_TILER_JOB_COMPLETED" title="Vertex jobs" name="Vertex jobs" description="The number of vertex jobs processed." units="jobs"/>
|
||||
<event offset="18" advanced="yes" counter="ITER_TILER_IDVS_TASK_COMPLETED" title="Vertex tasks" name="Vertex tasks" description="The number of vertex tasks processed." units="tasks"/>
|
||||
<event offset="19" advanced="yes" counter="ITER_TILER_TOTAL_IDVS_TASK_ACTIVE_CYCLES" title="Vertex total" name="Total vertex active cycles" description="The total number of vertex shading cycles processed." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="ITER_TILER_IRQ_ACTIVE" title="Vertex queue interrupt active" name="Vertex queue interrupt pending cycles" description="The number of cycles that the vertex queue IRQ was pending." units="cycles"/>
|
||||
<event offset="22" counter="ITER_TILER_READY_BLOCKED" title="Vertex queue endpoint stall" name="Vertex queue endpoint stall cycles" description="The number of cycles the vertex queue is waiting for endpoints to be assigned." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="ITER_TILER_EP_DRAIN" title="Vertex queue endpoint drain stall" name="Vertex queue endpoint drain stall cycles" description="The number of cycles the vertex queue is waiting for endpoints to drain." units="cycles"/>
|
||||
<event offset="24" counter="ITER_COMP_ACTIVE" title="Compute queued" name="Compute work queued cycles" description="The number of cycles that the compute queue has work queued." units="cycles"/>
|
||||
<event offset="25" advanced="yes" counter="ITER_COMP_JOB_COMPLETED" title="Compute jobs" name="Compute jobs" description="The number of compute jobs processed." units="jobs"/>
|
||||
<event offset="26" advanced="yes" counter="ITER_COMP_TASK_COMPLETED" title="Compute tasks" name="Compute tasks" description="The number of compute tasks processed." units="tasks"/>
|
||||
<event offset="27" advanced="yes" counter="ITER_COMP_TOTAL_TASK_ACTIVE_CYCLES" title="Compute total" name="Total compute active cycles" description="The total number of compute shading cycles processed." units="cycles"/>
|
||||
<event offset="28" advanced="yes" counter="ITER_COMP_IRQ_ACTIVE" title="Compute queue interrupt active" name="Compute queue interrupt pending cycles" description="The number of cycles that the compute queue IRQ was pending." units="cycles"/>
|
||||
<event offset="30" counter="ITER_COMP_READY_BLOCKED" title="Compute queue endpoint stall" name="Compute queue endpoint stall cycles" description="The number of cycles the compute queue is waiting for endpoints to be assigned." units="cycles"/>
|
||||
<event offset="31" advanced="yes" counter="ITER_COMP_EP_DRAIN" title="Compute queue endpoint drain stall" name="Compute queue endpoint drain stall cycles" description="The number of cycles the compute queue is waiting for endpoints to drain." units="cycles"/>
|
||||
<event offset="32" counter="ITER_FRAG_ACTIVE" title="Fragment queued" name="Fragment work queued cycles" description="The number of cycles that the fragment queue has work queued." units="cycles"/>
|
||||
<event offset="33" advanced="yes" counter="ITER_FRAG_JOB_COMPLETED" title="Fragment jobs" name="Fragment jobs" description="The number of fragment jobs processed." units="jobs"/>
|
||||
<event offset="34" counter="ITER_FRAG_TASK_COMPLETED" title="Fragment tasks" name="Fragment tasks" description="The number of fragment tasks processed." units="tasks"/>
|
||||
<event offset="35" advanced="yes" counter="ITER_FRAG_TOTAL_TASK_ACTIVE_CYCLES" title="Fragment total" name="Total fragment active cycles" description="The total number of fragment shading cycles processed." units="cycles"/>
|
||||
<event offset="36" advanced="yes" counter="ITER_FRAG_IRQ_ACTIVE" title="Fragment queue interrupt active" name="Fragment queue interrupt pending cycles" description="The number of cycles that the fragment queue IRQ was pending." units="cycles"/>
|
||||
<event offset="38" counter="ITER_FRAG_READY_BLOCKED" title="Fragment queue endpoint stall" name="Fragment queue endpoint stall cycles" description="The number of cycles the fragment queue is waiting for endpoints to be assigned." units="cycles"/>
|
||||
<event offset="40" advanced="yes" counter="CEU_ACTIVE" title="CEU active" name="Command execution unit active cycles" description="The number of cycles that the CEU is processing commands." units="cycles"/>
|
||||
<event offset="45" advanced="yes" counter="LSU_ACTIVE" title="LSU active" name="Command load/store unit active cycles" description="The number of cycles that the load-store unit is processing commands." units="cycles"/>
|
||||
<event offset="48" advanced="yes" counter="CSHWIF0_ENABLED" title="CS0 active" name="Command stream 0 active cycles" description="The number of cycles that command stream interface 0 contained an enabled command stream." units="cycles"/>
|
||||
<event offset="51" advanced="yes" counter="CSHWIF0_WAIT_BLOCKED" title="CS0 wait stall" name="Command stream 0 wait stall cycles" description="The number of cycles that command stream interface 0 was blocked because of a scheduling dependency." units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="CSHWIF1_ENABLED" title="CS1 active" name="Command stream 1 active cycles" description="The number of cycles that command stream interface 1 contained an enabled command stream." units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="CSHWIF1_WAIT_BLOCKED" title="CS1 wait stall" name="Command stream 1 wait stall cycles" description="The number of cycles that command stream interface 1 was blocked because of a scheduling dependency." units="cycles"/>
|
||||
<event offset="56" advanced="yes" counter="CSHWIF2_ENABLED" title="CS2 active" name="Command stream 2 active cycles" description="The number of cycles that command stream interface 2 contained an enabled command stream." units="cycles"/>
|
||||
<event offset="59" advanced="yes" counter="CSHWIF2_WAIT_BLOCKED" title="CS2 wait stall" name="Command stream 2 wait stall cycles" description="The number of cycles that command stream interface 2 was blocked because of a scheduling dependency." units="cycles"/>
|
||||
<event offset="60" advanced="yes" counter="CSHWIF3_ENABLED" title="CS3 active" name="Command stream 3 active cycles" description="The number of cycles that command stream interface 3 contained an enabled command stream." units="cycles"/>
|
||||
<event offset="63" advanced="yes" counter="CSHWIF3_WAIT_BLOCKED" title="CS3 wait stall" name="Command stream 3 wait stall cycles" description="The number of cycles that command stream interface 3 was blocked because of a scheduling dependency." units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="TILER_ACTIVE" title="Tiler active" name="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles"/>
|
||||
<event offset="6" counter="TRIANGLES" title="Triangle primitives" name="Triangle primitives" description="The number of input triangle primitives." units="primitives"/>
|
||||
<event offset="7" counter="LINES" title="Line primitives" name="Line primitives" description="The number of input line primitives." units="primitives"/>
|
||||
<event offset="8" counter="POINTS" title="Point primitives" name="Point primitives" description="The number of input point primitives." units="primitives"/>
|
||||
<event offset="9" advanced="yes" counter="FRONT_FACING" title="Front-facing primitives" name="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="10" advanced="yes" counter="BACK_FACING" title="Back-facing primitives" name="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives"/>
|
||||
<event offset="11" counter="PRIM_VISIBLE" title="Visible primitives" name="Visible primitives" description="The number of primitives that are visible after culling." units="primitives"/>
|
||||
<event offset="12" counter="PRIM_CULLED" title="Facing or XY plane test culled primitives" name="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives"/>
|
||||
<event offset="13" counter="PRIM_CLIPPED" title="Z plane test culled primitives" name="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives"/>
|
||||
<event offset="14" counter="PRIM_SAT_CULLED" title="Sample test culled primitives" name="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="Read beats" name="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats"/>
|
||||
<event offset="21" counter="IDVS_POS_SHAD_REQ" title="Position shading requests" name="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="IDVS_POS_SHAD_STALL" title="Position shading stall" name="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="IDVS_POS_FIFO_FULL" title="Position FIFO full stall" name="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="Position cache hits" name="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="VCACHE_MISS" title="Position cache misses" name="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="34" advanced="yes" counter="IDVS_VBU_HIT" title="Varying cache hits" name="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="IDVS_VBU_MISS" title="Varying cache misses" name="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests"/>
|
||||
<event offset="37" counter="IDVS_VAR_SHAD_REQ" title="Varying shading requests" name="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests"/>
|
||||
<event offset="38" advanced="yes" counter="IDVS_VAR_SHAD_STALL" title="Varying shading stall" name="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU lookups" name="MMU lookup requests" description="The number of main MMU address translations performed." units="requests"/>
|
||||
<event offset="5" advanced="yes" counter="MMU_TABLE_READS_L3" title="L3 table reads" name="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests"/>
|
||||
<event offset="6" advanced="yes" counter="MMU_TABLE_READS_L2" title="L2 table reads" name="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests"/>
|
||||
<event offset="7" advanced="yes" counter="MMU_HIT_L3" title="L3 table read hits" name="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests"/>
|
||||
<event offset="8" advanced="yes" counter="MMU_HIT_L2" title="L2 table read hits" name="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests"/>
|
||||
<event offset="12" advanced="yes" counter="L2_RD_MSG_IN_EVICT" title="Evict requests" name="Input internal evict requests" description="The number of L2 cache line evict requests from internal requesters." units="requests"/>
|
||||
<event offset="13" advanced="yes" counter="L2_RD_MSG_IN_CU" title="Clean unique requests" name="Input internal clean unique requests" description="The number of L2 cache line clean unique requests from internal requesters." units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="Read requests" name="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="Read stall" name="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="Write requests" name="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="Write stall" name="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="Snoop requests" name="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="Snoop stall" name="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L1 read requests" name="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L1 read stall" name="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L1 write requests" name="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests"/>
|
||||
<event offset="25" advanced="yes" counter="L2_ANY_LOOKUP" title="Any lookups" name="Any lookup requests" description="The number of L2 cache lookups performed." units="requests"/>
|
||||
<event offset="26" counter="L2_READ_LOOKUP" title="Read lookups" name="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests"/>
|
||||
<event offset="27" counter="L2_WRITE_LOOKUP" title="Write lookups" name="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="External snoop lookups" name="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests"/>
|
||||
<event offset="29" counter="L2_EXT_READ" title="Read transactions" name="Output external read transactions" description="The number of external read transactions." units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="ReadNoSnoop transactions" name="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="ReadUnique transactions" name="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions"/>
|
||||
<event offset="32" counter="L2_EXT_READ_BEATS" title="Read beats" name="Output external read beats" description="The number of external bus data read cycles." units="beats"/>
|
||||
<event offset="33" counter="L2_EXT_AR_STALL" title="Read stall" name="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="L2_EXT_AR_CNT_Q1" title="0-25% outstanding" name="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="35" advanced="yes" counter="L2_EXT_AR_CNT_Q2" title="25-50% outstanding" name="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="36" advanced="yes" counter="L2_EXT_AR_CNT_Q3" title="50-75% outstanding" name="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="37" counter="L2_EXT_RRESP_0_127" title="0-127 cycles" name="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats"/>
|
||||
<event offset="38" counter="L2_EXT_RRESP_128_191" title="128-191 cycles" name="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats"/>
|
||||
<event offset="39" counter="L2_EXT_RRESP_192_255" title="192-255 cycles" name="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats"/>
|
||||
<event offset="40" counter="L2_EXT_RRESP_256_319" title="256-319 cycles" name="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats"/>
|
||||
<event offset="41" counter="L2_EXT_RRESP_320_383" title="320-383 cycles" name="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats"/>
|
||||
<event offset="42" counter="L2_EXT_WRITE" title="Write transactions" name="Output external write transactions" description="The number of external write transactions." units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="WriteNoSnoopFull transactions" name="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="WriteNoSnoopPartial transactions" name="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="WriteSnoopFull transactions" name="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="WriteSnoopPartial transactions" name="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions"/>
|
||||
<event offset="47" counter="L2_EXT_WRITE_BEATS" title="Write beats" name="Output external write beats" description="The number of external bus data write cycles." units="beats"/>
|
||||
<event offset="48" counter="L2_EXT_W_STALL" title="Write stall" name="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles"/>
|
||||
<event offset="49" advanced="yes" counter="L2_EXT_AW_CNT_Q1" title="0-25% outstanding" name="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions"/>
|
||||
<event offset="50" advanced="yes" counter="L2_EXT_AW_CNT_Q2" title="25-50% outstanding" name="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions"/>
|
||||
<event offset="51" advanced="yes" counter="L2_EXT_AW_CNT_Q3" title="50-75% outstanding" name="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="Snoop transactions" name="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="Snoop stall" name="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" counter="FRAG_ACTIVE" title="Fragment active" name="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="FRAG_PRIMITIVES_OUT" title="Loaded primitives" name="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives"/>
|
||||
<event offset="6" counter="FRAG_PRIM_RAST" title="Rasterized primitives" name="Rasterized primitives" description="The number of primitives being rasterized." units="primitives"/>
|
||||
<event offset="7" counter="FRAG_FPK_ACTIVE" title="Fragment FPK buffer active" name="Forward pixel kill buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles"/>
|
||||
<event offset="9" counter="FRAG_WARPS" title="Fragment warps" name="Fragment warps" description="The number of fragment warps created." units="warps"/>
|
||||
<event offset="10" counter="FRAG_PARTIAL_QUADS_RAST" title="Partial rasterized fine quads" name="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads"/>
|
||||
<event offset="11" counter="FRAG_QUADS_RAST" title="Rasterized fine quads" name="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads"/>
|
||||
<event offset="12" counter="FRAG_QUADS_EZS_TEST" title="Early ZS tested quads" name="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads"/>
|
||||
<event offset="13" counter="FRAG_QUADS_EZS_UPDATE" title="Early ZS updated quads" name="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads"/>
|
||||
<event offset="14" counter="FRAG_QUADS_EZS_KILL" title="Early ZS killed quads" name="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads"/>
|
||||
<event offset="15" counter="FRAG_LZS_TEST" title="Late ZS tested quads" name="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads"/>
|
||||
<event offset="16" counter="FRAG_LZS_KILL" title="Late ZS killed quads" name="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads"/>
|
||||
<event offset="17" counter="WARP_REG_SIZE_64" title="All register warps" name="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps"/>
|
||||
<event offset="18" counter="FRAG_PTILES" title="Tiles" name="Tiles" description="The number of tiles processed by the shader core." units="tiles"/>
|
||||
<event offset="19" counter="FRAG_TRANS_ELIM" title="Killed unchanged tiles" name="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles"/>
|
||||
<event offset="20" counter="QUAD_FPK_KILLER" title="Occluding quads" name="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads"/>
|
||||
<event offset="21" counter="FULL_QUAD_WARPS" title="Full warps" name="Full warps" description="The number of warps that have a full thread slot allocation." units="warps"/>
|
||||
<event offset="22" counter="COMPUTE_ACTIVE" title="Non-fragment active" name="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="Non-fragment tasks" name="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks"/>
|
||||
<event offset="24" counter="COMPUTE_WARPS" title="Non-fragment warps" name="Non-fragment warps" description="The number of non-fragment warps created." units="warps"/>
|
||||
<event offset="26" counter="EXEC_CORE_ACTIVE" title="Execution core active" name="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles"/>
|
||||
<event offset="27" counter="EXEC_INSTR_FMA" title="FMA pipe instructions" name="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions"/>
|
||||
<event offset="28" counter="EXEC_INSTR_CVT" title="CVT pipe instructions" name="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions"/>
|
||||
<event offset="29" counter="EXEC_INSTR_SFU" title="SFU pipe instructions" name="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions"/>
|
||||
<event offset="31" counter="EXEC_INSTR_DIVERGED" title="Diverged instructions" name="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="EXEC_ICACHE_MISS" title="Cache misses" name="Instruction cache misses" description="The number of instruction cache misses." units="requests"/>
|
||||
<event offset="33" advanced="yes" counter="EXEC_STARVE_ARITH" title="Execution engine starvation" name="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles"/>
|
||||
<event offset="34" counter="CALL_BLEND_SHADER" title="Blend shader calls" name="Blend shader instructions" description="The number of blend shader invocations run." units="instructions"/>
|
||||
<event offset="35" counter="TEX_MSGI_NUM_FLITS" title="Input beats" name="Texture message read beats" description="The number of texture request message data beats." units="beats"/>
|
||||
<event offset="36" counter="TEX_DFCH_CLK_STALLED" title="Descriptor stall" name="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles"/>
|
||||
<event offset="37" counter="TEX_TFCH_CLK_STALLED" title="Fetch queue stall" name="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles"/>
|
||||
<event offset="38" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" title="Filtering unit stall" name="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles"/>
|
||||
<event offset="39" counter="TEX_FILT_NUM_OPERATIONS" title="Texture filtering active" name="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles"/>
|
||||
<event offset="40" counter="TEX_FILT_NUM_FXR_OPERATIONS" title="Full bilinear filter active" name="Texture filtering cycles using full bilinear" description="The number of cycles when the filtering unit is filled with bilinear filtering." units="cycles"/>
|
||||
<event offset="41" counter="TEX_FILT_NUM_FST_OPERATIONS" title="Full trilinear filter active" name="Texture filtering cycles using full trilinear" description="The number of cycles when the filtering unit is filled with trilinear filtering." units="cycles"/>
|
||||
<event offset="42" advanced="yes" counter="TEX_MSGO_NUM_MSG" title="Texture messages" name="Texture messages" description="The number of output texture messages from the texture unit." units="issues"/>
|
||||
<event offset="43" counter="TEX_MSGO_NUM_FLITS" title="Output beats" name="Texture message write beats" description="The number of texture response message data beats." units="beats"/>
|
||||
<event offset="44" counter="LS_MEM_READ_FULL" title="Full read" name="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles"/>
|
||||
<event offset="45" counter="LS_MEM_READ_SHORT" title="Partial read" name="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles"/>
|
||||
<event offset="46" counter="LS_MEM_WRITE_FULL" title="Full write" name="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles"/>
|
||||
<event offset="47" counter="LS_MEM_WRITE_SHORT" title="Partial write" name="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles"/>
|
||||
<event offset="48" counter="LS_MEM_ATOMIC" title="Atomic access" name="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles"/>
|
||||
<event offset="49" counter="VARY_INSTR" title="Interpolation requests" name="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests"/>
|
||||
<event offset="50" counter="VARY_SLOT_32" title="32-bit interpolation issues" name="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues"/>
|
||||
<event offset="51" counter="VARY_SLOT_16" title="16-bit interpolation issues" name="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="Attribute requests" name="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions"/>
|
||||
<event offset="53" counter="SHADER_CORE_ACTIVE" title="Any workload active" name="Any workload active cycles" description="The number of cycles when the shader core is processing either a non-fragment workload or a fragment workload." units="cycles"/>
|
||||
<event offset="54" counter="BEATS_RD_FTC" title="Fragment L2 read beats" name="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats"/>
|
||||
<event offset="55" counter="BEATS_RD_FTC_EXT" title="Fragment external read beats" name="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats"/>
|
||||
<event offset="56" counter="BEATS_RD_LSC" title="Load/store L2 read beats" name="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats"/>
|
||||
<event offset="57" counter="BEATS_RD_LSC_EXT" title="Load/store external read beats" name="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats"/>
|
||||
<event offset="58" counter="BEATS_RD_TEX" title="Texture L2 read beats" name="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats"/>
|
||||
<event offset="59" counter="BEATS_RD_TEX_EXT" title="Texture external read beats" name="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="Other L2 read beats" name="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats"/>
|
||||
<event offset="61" counter="BEATS_WR_LSC_OTHER" title="Load/store other write beats" name="Load/store unit other write beats" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats"/>
|
||||
<event offset="62" counter="BEATS_WR_TIB" title="Tile unit write beats" name="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats"/>
|
||||
<event offset="63" counter="BEATS_WR_LSC_WB" title="Load/store write-back write beats" name="Load/store unit write-back write beats" description="The number of write beats by the load/store unit that are because of write-back." units="beats"/>
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -1,316 +0,0 @@
|
|||
<!--
|
||||
Copyright © 2025 Collabora, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="TKRx" arch_major="13">
|
||||
<category name="CSF" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="GPU_ACTIVE" title="GPU_ACTIVE" name="GPU_ACTIVE" description="Number of cycles the GPU was active" units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="MCU_ACTIVE" title="MCU_ACTIVE" name="MCU_ACTIVE" description="Number of cycles the MCU has been active" units="cycles"/>
|
||||
<event offset="6" advanced="yes" counter="GPU_ITER_ACTIVE" title="GPU_ITER_ACTIVE" name="GPU_ITER_ACTIVE" description="Number of cycles any iterator was active" units="cycles"/>
|
||||
<event offset="7" advanced="yes" counter="MMU_FLUSH_COUNT" title="MMU_FLUSH_COUNT" name="MMU_FLUSH_COUNT" description="Number of MMU flush requests" units="requests"/>
|
||||
<event offset="8" advanced="yes" counter="MESSAGES_SENT" title="MESSAGES_SENT" name="MESSAGES_SENT" description="Number of job control bus messages sent" units="jobs"/>
|
||||
<event offset="9" advanced="yes" counter="MESSAGES_RECEIVED" title="MESSAGES_RECEIVED" name="MESSAGES_RECEIVED" description="Number of job control bus messages received" units="jobs"/>
|
||||
<event offset="10" advanced="yes" counter="GPU_IRQ_ACTIVE" title="GPU_IRQ_ACTIVE" name="GPU_IRQ_ACTIVE" description="Number of cycles with active interrupts" units="cycles"/>
|
||||
<event offset="11" advanced="yes" counter="GPU_IRQ_COUNT" title="GPU_IRQ_COUNT" name="GPU_IRQ_COUNT" description="Number of interrupts the GPU raised" units="interrupts"/>
|
||||
<event offset="12" advanced="yes" counter="CACHE_FLUSH_CYCLES" title="CACHE_FLUSH_CYCLES" name="CACHE_FLUSH_CYCLES" description="Number of cycles a L2C cache flush was active" units="cycles"/>
|
||||
<event offset="13" advanced="yes" counter="CACHE_FLUSH" title="CACHE_FLUSH" name="CACHE_FLUSH" description="Number of L2 cache flushes" units="requests"/>
|
||||
<event offset="14" advanced="yes" counter="DOORBELL_IRQ_ACTIVE" title="DOORBELL_IRQ_ACTIVE" name="DOORBELL_IRQ_ACTIVE" description="Number of cycles the doorbell interrupt has been asserted" units="cycles"/>
|
||||
<event offset="15" advanced="yes" counter="DOORBELL_IRQ_COUNT" title="DOORBELL_IRQ_COUNT" name="DOORBELL_IRQ_COUNT" description="Number of times the doorbell interrupt has been raised" units="interrupts"/>
|
||||
<event offset="16" advanced="yes" counter="CEU_ACTIVE" title="CEU_ACTIVE" name="CEU_ACTIVE" description="Number of cycles the CEU has been active" units="cycles"/>
|
||||
<event offset="17" advanced="yes" counter="CEU_READY_BLOCKED" title="CEU_READY_BLOCKED" name="CEU_READY_BLOCKED" description="Number of cycles the CEU has been stalled because it is waiting for a requested command or commands" units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="CEU_COMMAND_COUNT" title="CEU_COMMAND_COUNT" name="CEU_COMMAND_COUNT" description="Number of native commands that the CEU has executed" units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="CEU_STATE_TRANSFER_STALLED" title="CEU_STATE_TRANSFER_STALLED" name="CEU_STATE_TRANSFER_STALLED" description="Number of cycles the CEU was stalled during state transfer" units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="CEU_LSU_REQUEST_STALLED" title="CEU_LSU_REQUEST_STALLED" name="CEU_LSU_REQUEST_STALLED" description="Number of stalled cycles because there are no free LSU handlers" units="cycles"/>
|
||||
<event offset="21" advanced="yes" counter="LSU_ACTIVE" title="LSU_ACTIVE" name="LSU_ACTIVE" description="Number of cycles the LSU was active" units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="LSU_OPERATIONS_COMPLETED" title="LSU_OPERATIONS_COMPLETED" name="LSU_OPERATIONS_COMPLETED" description="Number of LSU operations that have completed" units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="LSU_TOTAL_HANDLERS_ACTIVE_CYCLES" title="LSU_TOTAL_HANDLERS_ACTIVE_CYCLES" name="LSU_TOTAL_HANDLERS_ACTIVE_CYCLES" description="Total number of cycles LSU handlers have been active" units="cycles"/>
|
||||
<event offset="32" advanced="yes" counter="ITER_COMP_ACTIVE" title="ITER_COMP_ACTIVE" name="ITER_COMP_ACTIVE" description="Number of cycles the compute iterator has spent processing jobs and waiting for tasks to complete" units="cycles"/>
|
||||
<event offset="33" advanced="yes" counter="ITER_COMP_JOB_COMPLETED" title="ITER_COMP_JOB_COMPLETED" name="ITER_COMP_JOB_COMPLETED" description="Number of jobs the compute iterator has completed" units="jobs"/>
|
||||
<event offset="34" advanced="yes" counter="ITER_COMP_TASK_COMPLETED" title="ITER_COMP_TASK_COMPLETED" name="ITER_COMP_TASK_COMPLETED" description="Number of tasks the compute iterator has completed" units="tasks"/>
|
||||
<event offset="35" advanced="yes" counter="ITER_COMP_TOTAL_TASK_ACTIVE_CYCLES" title="ITER_COMP_TOTAL_TASK_ACTIVE_CYCLES" name="ITER_COMP_TOTAL_TASK_ACTIVE_CYCLES" description="Total number of cycles compute endpoints have been processing compute tasks" units="cycles"/>
|
||||
<event offset="36" advanced="yes" counter="ITER_COMP_IRQ_ACTIVE" title="ITER_COMP_IRQ_ACTIVE" name="ITER_COMP_IRQ_ACTIVE" description="Number of cycles the compute iterator interrupt has been asserted" units="cycles"/>
|
||||
<event offset="37" advanced="yes" counter="ITER_COMP_IRQ_COUNT" title="ITER_COMP_IRQ_COUNT" name="ITER_COMP_IRQ_COUNT" description="Number of times the compute iterator interrupt has gone active" units="interrupts"/>
|
||||
<event offset="38" advanced="yes" counter="ITER_COMP_READY_BLOCKED" title="ITER_COMP_READY_BLOCKED" name="ITER_COMP_READY_BLOCKED" description="Number of cycles the compute iterator has had at least one task but no ready endpoints" units="cycles"/>
|
||||
<event offset="39" advanced="yes" counter="ITER_COMP_EP_DRAIN" title="ITER_COMP_EP_DRAIN" name="ITER_COMP_EP_DRAIN" description="Number of cycles the compute iterator is waiting for IDVS work to drain" units="cycles"/>
|
||||
<event offset="48" advanced="yes" counter="ITER_FRAG_ACTIVE" title="ITER_FRAG_ACTIVE" name="ITER_FRAG_ACTIVE" description="Number of cycles the fragment iterator has spent processing jobs and waiting for tasks to complete" units="cycles"/>
|
||||
<event offset="49" advanced="yes" counter="ITER_FRAG_JOB_COMPLETED" title="ITER_FRAG_JOB_COMPLETED" name="ITER_FRAG_JOB_COMPLETED" description="Number of jobs the fragment iterator has completed" units="jobs"/>
|
||||
<event offset="50" advanced="yes" counter="ITER_FRAG_TASK_COMPLETED" title="ITER_FRAG_TASK_COMPLETED" name="ITER_FRAG_TASK_COMPLETED" description="Number of tasks the fragment iterator has completed" units="tasks"/>
|
||||
<event offset="51" advanced="yes" counter="ITER_FRAG_TOTAL_TASK_ACTIVE_CYCLES" title="ITER_FRAG_TOTAL_TASK_ACTIVE_CYCLES" name="ITER_FRAG_TOTAL_TASK_ACTIVE_CYCLES" description="Total number of cycles fragment endpoints have been processing fragment tasks" units="cycles"/>
|
||||
<event offset="52" advanced="yes" counter="ITER_FRAG_IRQ_ACTIVE" title="ITER_FRAG_IRQ_ACTIVE" name="ITER_FRAG_IRQ_ACTIVE" description="Number of cycles the fragment iterator interrupt has been asserted" units="cycles"/>
|
||||
<event offset="53" advanced="yes" counter="ITER_FRAG_IRQ_COUNT" title="ITER_FRAG_IRQ_COUNT" name="ITER_FRAG_IRQ_COUNT" description="Number of times the fragment iterator interrupt has gone active" units="interrupts"/>
|
||||
<event offset="54" advanced="yes" counter="ITER_FRAG_READY_BLOCKED" title="ITER_FRAG_READY_BLOCKED" name="ITER_FRAG_READY_BLOCKED" description="Number of cycles the fragment iterator has had at least one task but no ready endpoints" units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="ITER_FRAG_TILE_MAP_READ_WAIT" title="ITER_FRAG_TILE_MAP_READ_WAIT" name="ITER_FRAG_TILE_MAP_READ_WAIT" description="Number of cycles the fragment iterator was waiting on a read of the tile enable mask" units="cycles"/>
|
||||
<event offset="64" advanced="yes" counter="ITER_TILER_ACTIVE" title="ITER_TILER_ACTIVE" name="ITER_TILER_ACTIVE" description="Number of cycles the tile iterator has spent processing jobs and waiting for tasks to complete" units="cycles"/>
|
||||
<event offset="65" advanced="yes" counter="ITER_TILER_JOB_COMPLETED" title="ITER_TILER_JOB_COMPLETED" name="ITER_TILER_JOB_COMPLETED" description="Number of jobs the tile iterator has completed" units="jobs"/>
|
||||
<event offset="66" advanced="yes" counter="ITER_TILER_IDVS_TASK_COMPLETED" title="ITER_TILER_IDVS_TASK_COMPLETED" name="ITER_TILER_IDVS_TASK_COMPLETED" description="Number of IDVS tasks the compute endpoints have completed" units="tasks"/>
|
||||
<event offset="67" advanced="yes" counter="ITER_TILER_TOTAL_IDVS_TASK_ACTIVE_CYCLES" title="ITER_TILER_TOTAL_IDVS_TASK_ACTIVE_CYCLES" name="ITER_TILER_TOTAL_IDVS_TASK_ACTIVE_CYCLES" description="Total number of cycles compute endpoints have been processing IDVS tasks" units="cycles"/>
|
||||
<event offset="68" advanced="yes" counter="ITER_TILER_IRQ_ACTIVE" title="ITER_TILER_IRQ_ACTIVE" name="ITER_TILER_IRQ_ACTIVE" description="Number of cycles the tile iterator interrupt has been asserted" units="cycles"/>
|
||||
<event offset="69" advanced="yes" counter="ITER_TILER_IRQ_COUNT" title="ITER_TILER_IRQ_COUNT" name="ITER_TILER_IRQ_COUNT" description="Number of times the tiler iterator interrupt has gone active" units="interrupts"/>
|
||||
<event offset="70" advanced="yes" counter="ITER_TILER_READY_BLOCKED" title="ITER_TILER_READY_BLOCKED" name="ITER_TILER_READY_BLOCKED" description="Number of cycles the tile iterator has had at least one task but no ready endpoints" units="cycles"/>
|
||||
<event offset="71" advanced="yes" counter="ITER_TILER_EP_DRAIN" title="ITER_TILER_EP_DRAIN" name="ITER_TILER_EP_DRAIN" description="Number of cycles of spent draining compute work before a tiler task can be issued" units="cycles"/>
|
||||
<event offset="80" advanced="yes" counter="CSHWIF0_ENABLED" title="CSHWIF0_ENABLED" name="CSHWIF0_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
|
||||
<event offset="81" advanced="yes" counter="CSHWIF0_PREFETCH_MISS_COUNT" title="CSHWIF0_PREFETCH_MISS_COUNT" name="CSHWIF0_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
|
||||
<event offset="82" advanced="yes" counter="CSHWIF0_IRQ_ACTIVE" title="CSHWIF0_IRQ_ACTIVE" name="CSHWIF0_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
|
||||
<event offset="83" advanced="yes" counter="CSHWIF0_IRQ_COUNT" title="CSHWIF0_IRQ_COUNT" name="CSHWIF0_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
|
||||
<event offset="84" advanced="yes" counter="CSHWIF0_WAIT_BLOCKED" title="CSHWIF0_WAIT_BLOCKED" name="CSHWIF0_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
|
||||
<event offset="86" advanced="yes" counter="CSHWIF1_ENABLED" title="CSHWIF1_ENABLED" name="CSHWIF1_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
|
||||
<event offset="87" advanced="yes" counter="CSHWIF1_PREFETCH_MISS_COUNT" title="CSHWIF1_PREFETCH_MISS_COUNT" name="CSHWIF1_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
|
||||
<event offset="88" advanced="yes" counter="CSHWIF1_IRQ_ACTIVE" title="CSHWIF1_IRQ_ACTIVE" name="CSHWIF1_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
|
||||
<event offset="89" advanced="yes" counter="CSHWIF1_IRQ_COUNT" title="CSHWIF1_IRQ_COUNT" name="CSHWIF1_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
|
||||
<event offset="90" advanced="yes" counter="CSHWIF1_WAIT_BLOCKED" title="CSHWIF1_WAIT_BLOCKED" name="CSHWIF1_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
|
||||
<event offset="92" advanced="yes" counter="CSHWIF2_ENABLED" title="CSHWIF2_ENABLED" name="CSHWIF2_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
|
||||
<event offset="93" advanced="yes" counter="CSHWIF2_PREFETCH_MISS_COUNT" title="CSHWIF2_PREFETCH_MISS_COUNT" name="CSHWIF2_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
|
||||
<event offset="94" advanced="yes" counter="CSHWIF2_IRQ_ACTIVE" title="CSHWIF2_IRQ_ACTIVE" name="CSHWIF2_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
|
||||
<event offset="95" advanced="yes" counter="CSHWIF2_IRQ_COUNT" title="CSHWIF2_IRQ_COUNT" name="CSHWIF2_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
|
||||
<event offset="96" advanced="yes" counter="CSHWIF2_WAIT_BLOCKED" title="CSHWIF2_WAIT_BLOCKED" name="CSHWIF2_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
|
||||
<event offset="98" advanced="yes" counter="CSHWIF3_ENABLED" title="CSHWIF3_ENABLED" name="CSHWIF3_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
|
||||
<event offset="99" advanced="yes" counter="CSHWIF3_PREFETCH_MISS_COUNT" title="CSHWIF3_PREFETCH_MISS_COUNT" name="CSHWIF3_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
|
||||
<event offset="100" advanced="yes" counter="CSHWIF3_IRQ_ACTIVE" title="CSHWIF3_IRQ_ACTIVE" name="CSHWIF3_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
|
||||
<event offset="101" advanced="yes" counter="CSHWIF3_IRQ_COUNT" title="CSHWIF3_IRQ_COUNT" name="CSHWIF3_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
|
||||
<event offset="102" advanced="yes" counter="CSHWIF3_WAIT_BLOCKED" title="CSHWIF3_WAIT_BLOCKED" name="CSHWIF3_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
|
||||
<event offset="104" advanced="yes" counter="CSHWIF4_ENABLED" title="CSHWIF4_ENABLED" name="CSHWIF4_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
|
||||
<event offset="105" advanced="yes" counter="CSHWIF4_PREFETCH_MISS_COUNT" title="CSHWIF4_PREFETCH_MISS_COUNT" name="CSHWIF4_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
|
||||
<event offset="106" advanced="yes" counter="CSHWIF4_IRQ_ACTIVE" title="CSHWIF4_IRQ_ACTIVE" name="CSHWIF4_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
|
||||
<event offset="107" advanced="yes" counter="CSHWIF4_IRQ_COUNT" title="CSHWIF4_IRQ_COUNT" name="CSHWIF4_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
|
||||
<event offset="108" advanced="yes" counter="CSHWIF4_WAIT_BLOCKED" title="CSHWIF4_WAIT_BLOCKED" name="CSHWIF4_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
|
||||
<event offset="110" advanced="yes" counter="CSHWIF5_ENABLED" title="CSHWIF5_ENABLED" name="CSHWIF5_ENABLED" description="Number of cycles the CSHWIF was in an ENABLED state" units="cycles"/>
|
||||
<event offset="111" advanced="yes" counter="CSHWIF5_PREFETCH_MISS_COUNT" title="CSHWIF5_PREFETCH_MISS_COUNT" name="CSHWIF5_PREFETCH_MISS_COUNT" description="Number of cycles the CSHWIF was unable to execute commands because of a prefetch miss" units="cycles"/>
|
||||
<event offset="112" advanced="yes" counter="CSHWIF5_IRQ_ACTIVE" title="CSHWIF5_IRQ_ACTIVE" name="CSHWIF5_IRQ_ACTIVE" description="Number of cycles the CSHWIFs interrupt has been asserted" units="cycles"/>
|
||||
<event offset="113" advanced="yes" counter="CSHWIF5_IRQ_COUNT" title="CSHWIF5_IRQ_COUNT" name="CSHWIF5_IRQ_COUNT" description="Number of times the CSHWIF interrupt has gone active" units="interrupts"/>
|
||||
<event offset="114" advanced="yes" counter="CSHWIF5_WAIT_BLOCKED" title="CSHWIF5_WAIT_BLOCKED" name="CSHWIF5_WAIT_BLOCKED" description="Number of cycles the CSHWIF has been blocked on a WAIT" units="cycles"/>
|
||||
</category>
|
||||
<category name="Tiler" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="TILER_ACTIVE" title="TILER_ACTIVE" name="TILER_ACTIVE" description="Number of cycles the tiler is active" units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="JOBS_PROCESSED" title="JOBS_PROCESSED" name="JOBS_PROCESSED" description="Number of processed tiler jobs" units="jobs"/>
|
||||
<event offset="6" advanced="yes" counter="TRIANGLES" title="TRIANGLES" name="TRIANGLES" description="Number of Triangles processed" units="requests"/>
|
||||
<event offset="7" advanced="yes" counter="LINES" title="LINES" name="LINES" description="Number of Lines processed" units="requests"/>
|
||||
<event offset="8" advanced="yes" counter="POINTS" title="POINTS" name="POINTS" description="Number of Points processed" units="requests"/>
|
||||
<event offset="9" advanced="yes" counter="FRONT_FACING" title="FRONT_FACING" name="FRONT_FACING" description="Number of front facing primitives" units="requests"/>
|
||||
<event offset="10" advanced="yes" counter="BACK_FACING" title="BACK_FACING" name="BACK_FACING" description="Number of back facing primitives" units="requests"/>
|
||||
<event offset="11" advanced="yes" counter="PRIM_VISIBLE" title="PRIM_VISIBLE" name="PRIM_VISIBLE" description="Number of visible primitives" units="requests"/>
|
||||
<event offset="12" advanced="yes" counter="PRIM_FACE_CULLED" title="PRIM_FACE_CULLED" name="PRIM_FACE_CULLED" description="Number of primitives culled by facing" units="requests"/>
|
||||
<event offset="13" advanced="yes" counter="PRIM_FRUSTUM_CULLED" title="PRIM_FRUSTUM_CULLED" name="PRIM_FRUSTUM_CULLED" description="Number of primitives culled as being outside the view frustum" units="requests"/>
|
||||
<event offset="14" advanced="yes" counter="PRIM_SAMPLE_CULLED" title="PRIM_SAMPLE_CULLED" name="PRIM_SAMPLE_CULLED" description="Number of primitives culled because they cannot produce samples" units="requests"/>
|
||||
<event offset="15" advanced="yes" counter="BIN_ALLOC_INIT" title="BIN_ALLOC_INIT" name="BIN_ALLOC_INIT" description="Number of initial bin allocations" units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="BIN_ALLOC_OVERFLOW" title="BIN_ALLOC_OVERFLOW" name="BIN_ALLOC_OVERFLOW" description="Number of overflow bin allocations" units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="BUS_READ" title="BUS_READ" name="BUS_READ" description="Number of read data beats (512-bit) from the L2 cache" units="beats"/>
|
||||
<event offset="18" advanced="yes" counter="BUS_WRITE_UTLB0" title="BUS_WRITE_UTLB0" name="BUS_WRITE_UTLB0" description="Number of write data beats (512-bit) to the L2 cache through µTLB #0" units="beats"/>
|
||||
<event offset="19" advanced="yes" counter="BUS_WRITE_UTLB1" title="BUS_WRITE_UTLB1" name="BUS_WRITE_UTLB1" description="Number of write data beats (512-bit) to the L2 cache through µTLB #1" units="beats"/>
|
||||
<event offset="20" advanced="yes" counter="SUSPENDED" title="SUSPENDED" name="SUSPENDED" description="Number of times the tiler has been suspended" units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="POS_SHADER_WARPS" title="POS_SHADER_WARPS" name="POS_SHADER_WARPS" description="Number of position shading warps" units="warps"/>
|
||||
<event offset="22" advanced="yes" counter="POS_SHADER_PARTIAL_WARPS" title="POS_SHADER_PARTIAL_WARPS" name="POS_SHADER_PARTIAL_WARPS" description="Number of position shading warps that were only partially filled" units="warps"/>
|
||||
<event offset="23" advanced="yes" counter="POS_SHADER_STALL" title="POS_SHADER_STALL" name="POS_SHADER_STALL" description="Number of cycles stalled on shading request interface requesting position shading" units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="POS_FIFO_FULL" title="POS_FIFO_FULL" name="POS_FIFO_FULL" description="Number of cycles the position FIFO is full and blocking position shading requests" units="cycles"/>
|
||||
<event offset="25" advanced="yes" counter="PREFETCH_STALL" title="PREFETCH_STALL" name="PREFETCH_STALL" description="Number of cycles the prefetcher has valid data but is stalled by the latency FIFO" units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="VCACHE_HIT" title="VCACHE_HIT" name="VCACHE_HIT" description="Number of vertex cache hits" units="requests"/>
|
||||
<event offset="27" advanced="yes" counter="LPA_HIT" title="LPA_HIT" name="LPA_HIT" description="Number of hits in late primitive assembly buffer" units="requests"/>
|
||||
<event offset="30" advanced="yes" counter="VFETCH_VERTEX_WAIT" title="VFETCH_VERTEX_WAIT" name="VFETCH_VERTEX_WAIT" description="Number of cycles waiting for a valid shaded positions to be loaded" units="cycles"/>
|
||||
<event offset="32" advanced="yes" counter="PRIMASSY_STALL" title="PRIMASSY_STALL" name="PRIMASSY_STALL" description="Number of cycles the primitive assembly output is stalled" units="cycles"/>
|
||||
<event offset="33" advanced="yes" counter="RESUMED" title="RESUMED" name="RESUMED" description="Number of times the tiler has been resumed" units="requests"/>
|
||||
<event offset="34" advanced="yes" counter="VBU_HIT" title="VBU_HIT" name="VBU_HIT" description="Number of vertex bitmap unit hits" units="requests"/>
|
||||
<event offset="36" advanced="yes" counter="VAR_SHADER_WARPS" title="VAR_SHADER_WARPS" name="VAR_SHADER_WARPS" description="Number of varying shading warps" units="warps"/>
|
||||
<event offset="37" advanced="yes" counter="VAR_SHADER_PARTIAL_WARPS" title="VAR_SHADER_PARTIAL_WARPS" name="VAR_SHADER_PARTIAL_WARPS" description="Number of varying shading warps that were only partially filled" units="warps"/>
|
||||
<event offset="38" advanced="yes" counter="VAR_SHADER_STALL" title="VAR_SHADER_STALL" name="VAR_SHADER_STALL" description="Number of cycles stalled on shading request interface requesting varying shading" units="cycles"/>
|
||||
<event offset="39" advanced="yes" counter="BINNER_STALL" title="BINNER_STALL" name="BINNER_STALL" description="Number of cycles the binner output is stalled" units="cycles"/>
|
||||
<event offset="40" advanced="yes" counter="ITER_STALL" title="ITER_STALL" name="ITER_STALL" description="Number of cycles the iterator output is stalled" units="cycles"/>
|
||||
<event offset="41" advanced="yes" counter="COMPRESS_MISS" title="COMPRESS_MISS" name="COMPRESS_MISS" description="Number of misses in the write compressor" units="requests"/>
|
||||
<event offset="42" advanced="yes" counter="ASN_R_STALL" title="ASN_R_STALL" name="ASN_R_STALL" description="Number of cycles the ASN R transactions are stalled" units="cycles"/>
|
||||
<event offset="43" advanced="yes" counter="PCACHE_HIT" title="PCACHE_HIT" name="PCACHE_HIT" description="Number of pointer cache hits" units="requests"/>
|
||||
<event offset="44" advanced="yes" counter="PCACHE_MISS" title="PCACHE_MISS" name="PCACHE_MISS" description="Number of Pointer Cache misses" units="requests"/>
|
||||
<event offset="45" advanced="yes" counter="PCACHE_MISS_STALL" title="PCACHE_MISS_STALL" name="PCACHE_MISS_STALL" description="Number of cycles waiting to process a miss in the pointer cache" units="cycles"/>
|
||||
<event offset="46" advanced="yes" counter="PCACHE_EVICT_STALL" title="PCACHE_EVICT_STALL" name="PCACHE_EVICT_STALL" description="Number of cycles waiting for eviction in the pointer cache to complete" units="cycles"/>
|
||||
<event offset="47" advanced="yes" counter="PMGR_PTR_WR_STALL" title="PMGR_PTR_WR_STALL" name="PMGR_PTR_WR_STALL" description="Number of cycles waiting for write-back pointer in the pointer manager" units="cycles"/>
|
||||
<event offset="48" advanced="yes" counter="PMGR_PTR_RD_STALL" title="PMGR_PTR_RD_STALL" name="PMGR_PTR_RD_STALL" description="Number of cycles waiting for a valid pointer in the pointer manager" units="cycles"/>
|
||||
<event offset="49" advanced="yes" counter="PMGR_CMD_WR_STALL" title="PMGR_CMD_WR_STALL" name="PMGR_CMD_WR_STALL" description="Number of cycles waiting for the write buffer to accept" units="cycles"/>
|
||||
<event offset="50" advanced="yes" counter="WRBUF_ACTIVE" title="WRBUF_ACTIVE" name="WRBUF_ACTIVE" description="Number of cycles the write buffer is active" units="cycles"/>
|
||||
<event offset="51" advanced="yes" counter="WRBUF_HIT" title="WRBUF_HIT" name="WRBUF_HIT" description="Number of write buffer hits" units="requests"/>
|
||||
<event offset="52" advanced="yes" counter="WRBUF_MISS" title="WRBUF_MISS" name="WRBUF_MISS" description="Number of Write Buffer misses" units="requests"/>
|
||||
<event offset="53" advanced="yes" counter="WRBUF_NO_FREE_LINE_STALL" title="WRBUF_NO_FREE_LINE_STALL" name="WRBUF_NO_FREE_LINE_STALL" description="Number of cycles stalled waiting for a free line in the write buffer" units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="WRBUF_NO_ASN_ID_STALL" title="WRBUF_NO_ASN_ID_STALL" name="WRBUF_NO_ASN_ID_STALL" description="Number of cycles the ASN interface is stalled due to the max transaction limit" units="cycles"/>
|
||||
<event offset="55" advanced="yes" counter="WRBUF_ASN_STALL" title="WRBUF_ASN_STALL" name="WRBUF_ASN_STALL" description="Number of cycles the ASN write data interface is stalled" units="cycles"/>
|
||||
<event offset="56" advanced="yes" counter="UTLB0_TRANS" title="UTLB0_TRANS" name="UTLB0_TRANS" description="Number of transactions processed" units="transactions"/>
|
||||
<event offset="57" advanced="yes" counter="UTLB0_TRANS_HIT" title="UTLB0_TRANS_HIT" name="UTLB0_TRANS_HIT" description="Number of micro-TLB hits" units="requests"/>
|
||||
<event offset="58" advanced="yes" counter="UTLB0_TRANS_STALL" title="UTLB0_TRANS_STALL" name="UTLB0_TRANS_STALL" description="Number of cycles transactions are stalled on the input" units="cycles"/>
|
||||
<event offset="59" advanced="yes" counter="UTLB0_MMU_REQ" title="UTLB0_MMU_REQ" name="UTLB0_MMU_REQ" description="Number of requests sent to the MMU" units="requests"/>
|
||||
<event offset="60" advanced="yes" counter="UTLB1_TRANS" title="UTLB1_TRANS" name="UTLB1_TRANS" description="Number of transactions processed" units="transactions"/>
|
||||
<event offset="61" advanced="yes" counter="UTLB1_TRANS_HIT" title="UTLB1_TRANS_HIT" name="UTLB1_TRANS_HIT" description="Number of micro-TLB hits" units="requests"/>
|
||||
<event offset="62" advanced="yes" counter="UTLB1_TRANS_STALL" title="UTLB1_TRANS_STALL" name="UTLB1_TRANS_STALL" description="Number of cycles transactions are stalled on the input" units="cycles"/>
|
||||
<event offset="63" advanced="yes" counter="UTLB1_MMU_REQ" title="UTLB1_MMU_REQ" name="UTLB1_MMU_REQ" description="Number of requests sent to the MMU" units="requests"/>
|
||||
<event offset="64" advanced="yes" counter="PRIMASSY_POS_SHADER_WAIT" title="PRIMASSY_POS_SHADER_WAIT" name="PRIMASSY_POS_SHADER_WAIT" description="Number of cycles late primitive assembly is waiting for position shading" units="cycles"/>
|
||||
<event offset="65" advanced="yes" counter="RUN_COMMANDS" title="RUN_COMMANDS" name="RUN_COMMANDS" description="Number of RUN commands processed by the tiler" units="requests"/>
|
||||
<event offset="66" advanced="yes" counter="FINISH_COMMANDS" title="FINISH_COMMANDS" name="FINISH_COMMANDS" description="Number of FINISH_TILING commands processed by the tiler" units="requests"/>
|
||||
<event offset="67" advanced="yes" counter="SUSPENDED_EMPTY" title="SUSPENDED_EMPTY" name="SUSPENDED_EMPTY" description="Number of times the tiler has been suspended with no unprocessed jobs" units="jobs"/>
|
||||
<event offset="68" advanced="yes" counter="OOM_COUNT" title="OOM_COUNT" name="OOM_COUNT" description="Number of times an out-of-memory event is raised" units="requests"/>
|
||||
<event offset="69" advanced="yes" counter="OOM_STALL" title="OOM_STALL" name="OOM_STALL" description="Number of cycles between an out-of-memory event and new memory is provided" units="cycles"/>
|
||||
<event offset="70" advanced="yes" counter="PRIM_SCISSOR_CULLED" title="PRIM_SCISSOR_CULLED" name="PRIM_SCISSOR_CULLED" description="Number of primitives culled as being outside the scissor box" units="requests"/>
|
||||
<event offset="71" advanced="yes" counter="PRIM_VISIBLE_DVS" title="PRIM_VISIBLE_DVS" name="PRIM_VISIBLE_DVS" description="Number of primitives selected for deferred vertex shading" units="requests"/>
|
||||
<event offset="72" advanced="yes" counter="FUSED_PRIMITIVES" title="FUSED_PRIMITIVES" name="FUSED_PRIMITIVES" description="Number of fused primitives" units="requests"/>
|
||||
<event offset="73" advanced="yes" counter="FUSED_PRIMITIVES_VISIBLE" title="FUSED_PRIMITIVES_VISIBLE" name="FUSED_PRIMITIVES_VISIBLE" description="Number of visible fused primitives" units="requests"/>
|
||||
<event offset="74" advanced="yes" counter="HEAP_CHUNKS_USED" title="HEAP_CHUNKS_USED" name="HEAP_CHUNKS_USED" description="Number of heap chunks used by the tiler" units="requests"/>
|
||||
<event offset="75" advanced="yes" counter="JOBS_EMPTY" title="JOBS_EMPTY" name="JOBS_EMPTY" description="Number of tiler jobs that are skipped as empty" units="jobs"/>
|
||||
</category>
|
||||
<category name="Shader Core" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="FRAG_ACTIVE" title="FRAG_ACTIVE" name="FRAG_ACTIVE" description="Number of cycles fragment processing is active" units="cycles"/>
|
||||
<event offset="5" advanced="yes" counter="EXEC_INSTR_NARROW" title="EXEC_INSTR_NARROW" name="EXEC_INSTR_NARROW" description="Number of narrow arithmetic operations" units="requests"/>
|
||||
<event offset="6" advanced="yes" counter="FRAG_PRIM_RAST" title="FRAG_PRIM_RAST" name="FRAG_PRIM_RAST" description="Number of rasterized primitives" units="requests"/>
|
||||
<event offset="7" advanced="yes" counter="FRAG_FPK_ACTIVE" title="FRAG_FPK_ACTIVE" name="FRAG_FPK_ACTIVE" description="Number of cycles the forward pixel kill queue contains data" units="cycles"/>
|
||||
<event offset="8" advanced="yes" counter="FRAG_STARVING" title="FRAG_STARVING" name="FRAG_STARVING" description="Number of cycles the fragment front end is starving the execution engine of new threads" units="cycles"/>
|
||||
<event offset="9" advanced="yes" counter="FRAG_WARPS" title="FRAG_WARPS" name="FRAG_WARPS" description="Number of fragment warps started" units="warps"/>
|
||||
<event offset="10" advanced="yes" counter="FRAG_PARTIAL_QUADS_RAST" title="FRAG_PARTIAL_QUADS_RAST" name="FRAG_PARTIAL_QUADS_RAST" description="Number of partial fragment quads rasterized" units="quads"/>
|
||||
<event offset="11" advanced="yes" counter="FRAG_QUADS_RAST" title="FRAG_QUADS_RAST" name="FRAG_QUADS_RAST" description="Number of quads rasterized" units="quads"/>
|
||||
<event offset="12" advanced="yes" counter="FRAG_QUADS_EZS_TEST" title="FRAG_QUADS_EZS_TEST" name="FRAG_QUADS_EZS_TEST" description="Number of quads doing early ZS test" units="quads"/>
|
||||
<event offset="13" advanced="yes" counter="FRAG_QUADS_EZS_UPDATE" title="FRAG_QUADS_EZS_UPDATE" name="FRAG_QUADS_EZS_UPDATE" description="Number of quads doing early ZS update" units="quads"/>
|
||||
<event offset="14" advanced="yes" counter="FRAG_QUADS_EZS_KILL" title="FRAG_QUADS_EZS_KILL" name="FRAG_QUADS_EZS_KILL" description="Number of quads killed by the early ZS test" units="quads"/>
|
||||
<event offset="15" advanced="yes" counter="FRAG_LZS_TEST" title="FRAG_LZS_TEST" name="FRAG_LZS_TEST" description="Number of quads doing late ZS test" units="quads"/>
|
||||
<event offset="16" advanced="yes" counter="FRAG_LZS_KILL" title="FRAG_LZS_KILL" name="FRAG_LZS_KILL" description="Number of quads killed by the late ZS test" units="quads"/>
|
||||
<event offset="17" advanced="yes" counter="WARP_REG_SIZE_64" title="WARP_REG_SIZE_64" name="WARP_REG_SIZE_64" description="Number of warps created with 64 registers allocated" units="warps"/>
|
||||
<event offset="18" advanced="yes" counter="FRAG_PTILES" title="FRAG_PTILES" name="FRAG_PTILES" description="Number of physical tiles rendered" units="tiles"/>
|
||||
<event offset="19" advanced="yes" counter="FRAG_TRANS_ELIM" title="FRAG_TRANS_ELIM" name="FRAG_TRANS_ELIM" description="Number of transaction elimination signature matches" units="transactions"/>
|
||||
<event offset="20" advanced="yes" counter="QUAD_FPK_KILLER" title="QUAD_FPK_KILLER" name="QUAD_FPK_KILLER" description="Number of quads which enter the FPK queue and can kill other quads" units="quads"/>
|
||||
<event offset="21" advanced="yes" counter="FULL_QUAD_WARPS" title="FULL_QUAD_WARPS" name="FULL_QUAD_WARPS" description="Number of warps created with all quads active" units="warps"/>
|
||||
<event offset="22" advanced="yes" counter="COMPUTE_ACTIVE" title="COMPUTE_ACTIVE" name="COMPUTE_ACTIVE" description="Number of cycles compute processing is active" units="cycles"/>
|
||||
<event offset="23" advanced="yes" counter="COMPUTE_TASKS" title="COMPUTE_TASKS" name="COMPUTE_TASKS" description="Number of compute tasks" units="tasks"/>
|
||||
<event offset="24" advanced="yes" counter="COMPUTE_WARPS" title="COMPUTE_WARPS" name="COMPUTE_WARPS" description="Number of compute warps started" units="warps"/>
|
||||
<event offset="25" advanced="yes" counter="COMPUTE_STARVING" title="COMPUTE_STARVING" name="COMPUTE_STARVING" description="Number of cycles unable to issue new compute threads" units="cycles"/>
|
||||
<event offset="26" advanced="yes" counter="EXEC_CORE_ACTIVE" title="EXEC_CORE_ACTIVE" name="EXEC_CORE_ACTIVE" description="Number of cycles the execution core is active" units="cycles"/>
|
||||
<event offset="27" advanced="yes" counter="EXEC_INSTR_FMA" title="EXEC_INSTR_FMA" name="EXEC_INSTR_FMA" description="Number of FMA arithmetic operations per Processing Unit" units="requests"/>
|
||||
<event offset="28" advanced="yes" counter="EXEC_INSTR_CVT" title="EXEC_INSTR_CVT" name="EXEC_INSTR_CVT" description="Number of CVT arithmetic operations per Processing Unit" units="requests"/>
|
||||
<event offset="29" advanced="yes" counter="EXEC_INSTR_SFU" title="EXEC_INSTR_SFU" name="EXEC_INSTR_SFU" description="Number of SFU arithmetic operations per Processing Unit" units="requests"/>
|
||||
<event offset="30" advanced="yes" counter="EXEC_INSTR_MSG" title="EXEC_INSTR_MSG" name="EXEC_INSTR_MSG" description="Number of message instruction per Processing Unit" units="instructions"/>
|
||||
<event offset="31" advanced="yes" counter="EXEC_INSTR_DIVERGED" title="EXEC_INSTR_DIVERGED" name="EXEC_INSTR_DIVERGED" description="Number of diverged instructions per Processing Unit" units="instructions"/>
|
||||
<event offset="32" advanced="yes" counter="EXEC_ICACHE_MISS" title="EXEC_ICACHE_MISS" name="EXEC_ICACHE_MISS" description="Number of I-cache capacity misses" units="requests"/>
|
||||
<event offset="33" advanced="yes" counter="EXEC_STARVE_ARITH" title="EXEC_STARVE_ARITH" name="EXEC_STARVE_ARITH" description="Processing Unit starvation" units="requests"/>
|
||||
<event offset="34" advanced="yes" counter="CALL_BLEND_SHADER" title="CALL_BLEND_SHADER" name="CALL_BLEND_SHADER" description="Number of calls to blend shaders per Processing Unit" units="requests"/>
|
||||
<event offset="35" advanced="yes" counter="TEX_MSGI_NUM_FLITS" title="TEX_MSGI_NUM_FLITS" name="TEX_MSGI_NUM_FLITS" description="Number of texturing request message flits received by the texture mapper" units="requests"/>
|
||||
<event offset="36" advanced="yes" counter="TEX_DFCH_CLK_STALLED" title="TEX_DFCH_CLK_STALLED" name="TEX_DFCH_CLK_STALLED" description="Number of cycles a quad is stalled waiting for a descriptor fetch" units="cycles"/>
|
||||
<event offset="37" advanced="yes" counter="TEX_TFCH_CLK_STALLED" title="TEX_TFCH_CLK_STALLED" name="TEX_TFCH_CLK_STALLED" description="Number of cycles a quad is stalled waiting to enter the texel fetcher" units="cycles"/>
|
||||
<event offset="38" advanced="yes" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" title="TEX_TFCH_STARVED_PENDING_DATA_FETCH" name="TEX_TFCH_STARVED_PENDING_DATA_FETCH" description="Number of cycles the parking buffer was not empty, but no filtering operation was issued" units="cycles"/>
|
||||
<event offset="39" advanced="yes" counter="TEX_FILT_NUM_OPERATIONS" title="TEX_FILT_NUM_OPERATIONS" name="TEX_FILT_NUM_OPERATIONS" description="Number of operations executed in the filtering unit" units="requests"/>
|
||||
<event offset="42" advanced="yes" counter="TEX_MSGO_NUM_MSG" title="TEX_MSGO_NUM_MSG" name="TEX_MSGO_NUM_MSG" description="Number of response messages sent" units="requests"/>
|
||||
<event offset="43" advanced="yes" counter="TEX_RSPS_NUM_OPERATIONS" title="TEX_RSPS_NUM_OPERATIONS" name="TEX_RSPS_NUM_OPERATIONS" description="Number of cycles the texture mapper outputs data" units="cycles"/>
|
||||
<event offset="44" advanced="yes" counter="LS_MEM_READ_FULL" title="LS_MEM_READ_FULL" name="LS_MEM_READ_FULL" description="Number of memory read accesses, full cache line" units="requests"/>
|
||||
<event offset="45" advanced="yes" counter="LS_MEM_READ_SHORT" title="LS_MEM_READ_SHORT" name="LS_MEM_READ_SHORT" description="Number of memory read accesses, partial cache line" units="requests"/>
|
||||
<event offset="46" advanced="yes" counter="LS_MEM_WRITE_FULL" title="LS_MEM_WRITE_FULL" name="LS_MEM_WRITE_FULL" description="Number of memory write accesses, full cache line" units="requests"/>
|
||||
<event offset="47" advanced="yes" counter="LS_MEM_WRITE_SHORT" title="LS_MEM_WRITE_SHORT" name="LS_MEM_WRITE_SHORT" description="Number of memory write accesses, partial cache line" units="requests"/>
|
||||
<event offset="48" advanced="yes" counter="LS_MEM_ATOMIC" title="LS_MEM_ATOMIC" name="LS_MEM_ATOMIC" description="Number of atomic memory accesses" units="requests"/>
|
||||
<event offset="49" advanced="yes" counter="VARY_INSTR" title="VARY_INSTR" name="VARY_INSTR" description="Number of varying instructions" units="instructions"/>
|
||||
<event offset="50" advanced="yes" counter="VARY_SLOT_32" title="VARY_SLOT_32" name="VARY_SLOT_32" description="Number of 32-bit varying slots" units="requests"/>
|
||||
<event offset="51" advanced="yes" counter="VARY_SLOT_16" title="VARY_SLOT_16" name="VARY_SLOT_16" description="Number of 16-bit varying slots" units="requests"/>
|
||||
<event offset="52" advanced="yes" counter="ATTR_INSTR" title="ATTR_INSTR" name="ATTR_INSTR" description="Number of load/store attribute calculations completed" units="requests"/>
|
||||
<event offset="53" advanced="yes" counter="SHADER_CORE_ACTIVE" title="SHADER_CORE_ACTIVE" name="SHADER_CORE_ACTIVE" description="Number of cycles a shader core is active" units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="BEATS_RD_FTC" title="BEATS_RD_FTC" name="BEATS_RD_FTC" description="Number of read beats for the fragment thread creator" units="beats"/>
|
||||
<event offset="55" advanced="yes" counter="BEATS_RD_FTC_EXT" title="BEATS_RD_FTC_EXT" name="BEATS_RD_FTC_EXT" description="Number of external read beats for the fragment thread creator" units="beats"/>
|
||||
<event offset="56" advanced="yes" counter="BEATS_RD_LSC" title="BEATS_RD_LSC" name="BEATS_RD_LSC" description="Number of read beats for the load/store cache" units="beats"/>
|
||||
<event offset="57" advanced="yes" counter="BEATS_RD_LSC_EXT" title="BEATS_RD_LSC_EXT" name="BEATS_RD_LSC_EXT" description="Number of external read beats for the load/store cache" units="beats"/>
|
||||
<event offset="58" advanced="yes" counter="BEATS_RD_TEX" title="BEATS_RD_TEX" name="BEATS_RD_TEX" description="Number of read beats for the texture cache" units="beats"/>
|
||||
<event offset="59" advanced="yes" counter="BEATS_RD_TEX_EXT" title="BEATS_RD_TEX_EXT" name="BEATS_RD_TEX_EXT" description="Number of external read beats for the texture cache" units="beats"/>
|
||||
<event offset="60" advanced="yes" counter="BEATS_RD_OTHER" title="BEATS_RD_OTHER" name="BEATS_RD_OTHER" description="Number of read beats for all other requesters" units="beats"/>
|
||||
<event offset="61" advanced="yes" counter="BEATS_WR_LSC_OTHER" title="BEATS_WR_LSC_OTHER" name="BEATS_WR_LSC_OTHER" description="Number of write beats from the load/store cache due to other reasons" units="beats"/>
|
||||
<event offset="62" advanced="yes" counter="BEATS_WR_TIB" title="BEATS_WR_TIB" name="BEATS_WR_TIB" description="Number of write beats for the tile buffers" units="beats"/>
|
||||
<event offset="63" advanced="yes" counter="BEATS_WR_LSC_WB" title="BEATS_WR_LSC_WB" name="BEATS_WR_LSC_WB" description="Number of write beats from the load/store cache due to write-backs" units="beats"/>
|
||||
<event offset="68" advanced="yes" counter="FRAG_QUADS_COARSE" title="FRAG_QUADS_COARSE" name="FRAG_QUADS_COARSE" description="Number of coarse quads before early culling" units="quads"/>
|
||||
<event offset="69" advanced="yes" counter="FRAG_SHADER_THREADS" title="FRAG_SHADER_THREADS" name="FRAG_SHADER_THREADS" description="Number of fragment shader threads executed" units="threads"/>
|
||||
<event offset="70" advanced="yes" counter="RT_RAY_TRI" title="RT_RAY_TRI" name="RT_RAY_TRI" description="Number of triangle batches tested" units="requests"/>
|
||||
<event offset="71" advanced="yes" counter="RT_RAY_BOX" title="RT_RAY_BOX" name="RT_RAY_BOX" description="Number of acceleration structure nodes tested" units="requests"/>
|
||||
<event offset="72" advanced="yes" counter="RT_RAY_TRI_BIN_1_4" title="RT_RAY_TRI_BIN_1_4" name="RT_RAY_TRI_BIN_1_4" description="Number of triangle batches tested with 1 to 4 active rays in the warp" units="warps"/>
|
||||
<event offset="73" advanced="yes" counter="RT_RAY_TRI_BIN_5_8" title="RT_RAY_TRI_BIN_5_8" name="RT_RAY_TRI_BIN_5_8" description="Number of triangle batches tested with 5 to 8 active rays in the warp" units="warps"/>
|
||||
<event offset="74" advanced="yes" counter="RT_RAY_TRI_BIN_9_12" title="RT_RAY_TRI_BIN_9_12" name="RT_RAY_TRI_BIN_9_12" description="Number of triangle batches tested with 9 to 12 active rays in the warp" units="warps"/>
|
||||
<event offset="75" advanced="yes" counter="RT_RAY_TRI_BIN_13_16" title="RT_RAY_TRI_BIN_13_16" name="RT_RAY_TRI_BIN_13_16" description="Number of triangle batches tested with 13 to 16 active rays in the warp" units="warps"/>
|
||||
<event offset="76" advanced="yes" counter="RT_RAY_BOX_BIN_1_4" title="RT_RAY_BOX_BIN_1_4" name="RT_RAY_BOX_BIN_1_4" description="Number of acceleration structure nodes visited with 1 to 4 active rays in the warp" units="warps"/>
|
||||
<event offset="77" advanced="yes" counter="RT_RAY_BOX_BIN_5_8" title="RT_RAY_BOX_BIN_5_8" name="RT_RAY_BOX_BIN_5_8" description="Number of acceleration structure nodes visited with 5 to 8 active rays in the warp" units="warps"/>
|
||||
<event offset="78" advanced="yes" counter="RT_RAY_BOX_BIN_9_12" title="RT_RAY_BOX_BIN_9_12" name="RT_RAY_BOX_BIN_9_12" description="Number of acceleration structure nodes visited with 9 to 12 active rays in the warp" units="warps"/>
|
||||
<event offset="79" advanced="yes" counter="RT_RAY_BOX_BIN_13_16" title="RT_RAY_BOX_BIN_13_16" name="RT_RAY_BOX_BIN_13_16" description="Number of acceleration structure nodes visited with 13 to 16 active rays in the warp" units="warps"/>
|
||||
<event offset="80" advanced="yes" counter="RT_OPAQUE_HIT" title="RT_OPAQUE_HIT" name="RT_OPAQUE_HIT" description="Number of opaque triangles hit" units="requests"/>
|
||||
<event offset="81" advanced="yes" counter="RT_NON_OPAQUE_HIT" title="RT_NON_OPAQUE_HIT" name="RT_NON_OPAQUE_HIT" description="Number of non-opaque triangles hit" units="requests"/>
|
||||
<event offset="82" advanced="yes" counter="RT_TERM_FIRST_HIT" title="RT_TERM_FIRST_HIT" name="RT_TERM_FIRST_HIT" description="Number of rays that terminate on their first hit" units="requests"/>
|
||||
<event offset="83" advanced="yes" counter="RT_MISS" title="RT_MISS" name="RT_MISS" description="Number of ray-triangle intersection tests that resulted in a miss" units="requests"/>
|
||||
<event offset="84" advanced="yes" counter="RT_RAYS_STARTED" title="RT_RAYS_STARTED" name="RT_RAYS_STARTED" description="Number of rays that tested the root node of a top level acceleration structure" units="requests"/>
|
||||
<event offset="85" advanced="yes" counter="RT_RAY_BOX_ISSUED" title="RT_RAY_BOX_ISSUED" name="RT_RAY_BOX_ISSUED" description="Number of active issue cycles for the ray box data path" units="cycles"/>
|
||||
<event offset="86" advanced="yes" counter="RT_RAY_TRI_ISSUED" title="RT_RAY_TRI_ISSUED" name="RT_RAY_TRI_ISSUED" description="Number of active issue cycles for the ray triangle data path" units="cycles"/>
|
||||
<event offset="87" advanced="yes" counter="TEX_CFCH_NUM_OUTPUT_OPERATIONS" title="TEX_CFCH_NUM_OUTPUT_OPERATIONS" name="TEX_CFCH_NUM_OUTPUT_OPERATIONS" description="Number of cycles the texture mapper spends on transferring uncompressed texel data" units="cycles"/>
|
||||
<event offset="88" advanced="yes" counter="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" title="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" name="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" description="Number of cycles processing simple texture formats" units="cycles"/>
|
||||
<event offset="89" advanced="yes" counter="TEX_CFCH_NUM_L1_CL_OPERATIONS" title="TEX_CFCH_NUM_L1_CL_OPERATIONS" name="TEX_CFCH_NUM_L1_CL_OPERATIONS" description="Number of cycles the texture L1 cache outputs data" units="cycles"/>
|
||||
<event offset="90" advanced="yes" counter="TEX_CFCH_NUM_L1_CT_OPERATIONS" title="TEX_CFCH_NUM_L1_CT_OPERATIONS" name="TEX_CFCH_NUM_L1_CT_OPERATIONS" description="Number of cycles the texture L1 cache is being accessed" units="cycles"/>
|
||||
<event offset="91" advanced="yes" counter="TEX_MSGO_NUM_SINGLE_QUAD_MSG" title="TEX_MSGO_NUM_SINGLE_QUAD_MSG" name="TEX_MSGO_NUM_SINGLE_QUAD_MSG" description="Number of return messages containing only one quad" units="quads"/>
|
||||
<event offset="92" advanced="yes" counter="TEX_TFCH_NUM_TCL_OPERATIONS" title="TEX_TFCH_NUM_TCL_OPERATIONS" name="TEX_TFCH_NUM_TCL_OPERATIONS" description="Number of cycles the texture mapper spends on reading data from the texture cache" units="cycles"/>
|
||||
<event offset="93" advanced="yes" counter="TEX_CFCH_NUM_RP_OPERATIONS" title="TEX_CFCH_NUM_RP_OPERATIONS" name="TEX_CFCH_NUM_RP_OPERATIONS" description="Number of cycles processing complex texture formats" units="cycles"/>
|
||||
<event offset="94" advanced="yes" counter="TEX_TIDX_NUM_OPERATIONS" title="TEX_TIDX_NUM_OPERATIONS" name="TEX_TIDX_NUM_OPERATIONS" description="Number of cycles the texture mapper spends on calculating texel indices" units="cycles"/>
|
||||
<event offset="95" advanced="yes" counter="TEX_MSGI_CLK_STARVED" title="TEX_MSGI_CLK_STARVED" name="TEX_MSGI_CLK_STARVED" description="Number of cycles the texture pipe is active and the message input unit is idle waiting to receive a message" units="cycles"/>
|
||||
<event offset="96" advanced="yes" counter="TEX_TEXP_CLK_ACTIVE" title="TEX_TEXP_CLK_ACTIVE" name="TEX_TEXP_CLK_ACTIVE" description="Number of clock cycles that the texture pipe has been active" units="cycles"/>
|
||||
<event offset="97" advanced="yes" counter="FRAG_PRIMITIVES_OUT" title="FRAG_PRIMITIVES_OUT" name="FRAG_PRIMITIVES_OUT" description="Number of primitives" units="requests"/>
|
||||
<event offset="98" advanced="yes" counter="FRAG_PRIMITIVES_HSR_CULLED" title="FRAG_PRIMITIVES_HSR_CULLED" name="FRAG_PRIMITIVES_HSR_CULLED" description="Number of primitives filtered by the Primitive Classification Unit" units="requests"/>
|
||||
<event offset="99" advanced="yes" counter="FRAG_PRIMITIVES_OUT_PRE_PASS" title="FRAG_PRIMITIVES_OUT_PRE_PASS" name="FRAG_PRIMITIVES_OUT_PRE_PASS" description="Number of primitives rendered in the fragment prepass" units="requests"/>
|
||||
<event offset="100" advanced="yes" counter="FRAG_PRIMITIVES_HSR_DISABLED" title="FRAG_PRIMITIVES_HSR_DISABLED" name="FRAG_PRIMITIVES_HSR_DISABLED" description="Number of primitives in the main-pass that cannot be culled by HSR ID testing" units="requests"/>
|
||||
<event offset="101" advanced="yes" counter="FRAG_QUADS_HSR_BUF_EZS_UPDATE" title="FRAG_QUADS_HSR_BUF_EZS_UPDATE" name="FRAG_QUADS_HSR_BUF_EZS_UPDATE" description="Number of quads updating the HSR ID buffer during early ZS testing" units="quads"/>
|
||||
<event offset="102" advanced="yes" counter="FRAG_QUADS_HSR_BUF_TEST" title="FRAG_QUADS_HSR_BUF_TEST" name="FRAG_QUADS_HSR_BUF_TEST" description="Number of quads tested against the HSR ID buffer" units="quads"/>
|
||||
<event offset="103" advanced="yes" counter="FRAG_QUADS_HSR_BUF_KILLED" title="FRAG_QUADS_HSR_BUF_KILLED" name="FRAG_QUADS_HSR_BUF_KILLED" description="Number of quads killed against the HSR ID buffer" units="quads"/>
|
||||
<event offset="104" advanced="yes" counter="FRAG_WARPS_PRE_PASS" title="FRAG_WARPS_PRE_PASS" name="FRAG_WARPS_PRE_PASS" description="Number of warps created in the fragment prepass" units="warps"/>
|
||||
<event offset="105" advanced="yes" counter="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" title="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" name="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" description="Number of cycles a Fragment Main-pass was stalled by a fragment prepass" units="cycles"/>
|
||||
<event offset="106" advanced="yes" counter="DVS_WARPS" title="DVS_WARPS" name="DVS_WARPS" description="Number of DVS shading warps" units="warps"/>
|
||||
<event offset="112" advanced="yes" counter="EXEC_MSG_STALLED_TEX" title="EXEC_MSG_STALLED_TEX" name="EXEC_MSG_STALLED_TEX" description="Cycles stalled trying to send a message to TEX unit" units="cycles"/>
|
||||
<event offset="113" advanced="yes" counter="EXEC_MSG_STALLED_VARY" title="EXEC_MSG_STALLED_VARY" name="EXEC_MSG_STALLED_VARY" description="Cycles stalled trying to send a message to VARY unit" units="cycles"/>
|
||||
<event offset="114" advanced="yes" counter="EXEC_MSG_STALLED_BLEND" title="EXEC_MSG_STALLED_BLEND" name="EXEC_MSG_STALLED_BLEND" description="Cycles stalled trying to send a message to BLEND unit" units="cycles"/>
|
||||
<event offset="115" advanced="yes" counter="EXEC_MSG_STALLED_ZS" title="EXEC_MSG_STALLED_ZS" name="EXEC_MSG_STALLED_ZS" description="Cycles stalled trying to send a message to ZS unit" units="cycles"/>
|
||||
<event offset="116" advanced="yes" counter="EXEC_MSG_STALLED_LSC" title="EXEC_MSG_STALLED_LSC" name="EXEC_MSG_STALLED_LSC" description="Cycles stalled trying to send a message to LSC unit" units="cycles"/>
|
||||
<event offset="117" advanced="yes" counter="EXEC_MSG_STALLED_ATTR" title="EXEC_MSG_STALLED_ATTR" name="EXEC_MSG_STALLED_ATTR" description="Cycles stalled trying to send a message to ATTR unit" units="cycles"/>
|
||||
<event offset="118" advanced="yes" counter="EXEC_INSTR_SLOT_1" title="EXEC_INSTR_SLOT_1" name="EXEC_INSTR_SLOT_1" description="Instructions issued in slot 1" units="instructions"/>
|
||||
<event offset="119" advanced="yes" counter="EXEC_ISSUE_SLOT_ANY" title="EXEC_ISSUE_SLOT_ANY" name="EXEC_ISSUE_SLOT_ANY" description="Clock cycles where instructions are issued in any slot" units="cycles"/>
|
||||
</category>
|
||||
<category name="Memory System" per_cpu="no">
|
||||
<event offset="4" advanced="yes" counter="MMU_REQUESTS" title="MMU_REQUESTS" name="MMU_REQUESTS" description="Number of requests received by the MMU" units="requests"/>
|
||||
<event offset="5" advanced="yes" counter="MMU_TABLE_READS_L3" title="MMU_TABLE_READS_L3" name="MMU_TABLE_READS_L3" description="Number of level 3 translation table reads" units="requests"/>
|
||||
<event offset="6" advanced="yes" counter="MMU_TABLE_READS_L2" title="MMU_TABLE_READS_L2" name="MMU_TABLE_READS_L2" description="Number of level 2 translation table reads" units="requests"/>
|
||||
<event offset="7" advanced="yes" counter="MMU_HIT_L3" title="MMU_HIT_L3" name="MMU_HIT_L3" description="Number of hits to level 3 page descriptors" units="requests"/>
|
||||
<event offset="8" advanced="yes" counter="MMU_HIT_L2" title="MMU_HIT_L2" name="MMU_HIT_L2" description="Number of hits to level 2 page descriptors" units="requests"/>
|
||||
<event offset="12" advanced="yes" counter="L2_RD_MSG_IN_EVICT" title="L2_RD_MSG_IN_EVICT" name="L2_RD_MSG_IN_EVICT" description="Number of evict messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="13" advanced="yes" counter="L2_RD_MSG_IN_CU" title="L2_RD_MSG_IN_CU" name="L2_RD_MSG_IN_CU" description="Number of clean unique messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="14" advanced="yes" counter="L2_SNP_MSG_IN_SNPRSP" title="L2_SNP_MSG_IN_SNPRSP" name="L2_SNP_MSG_IN_SNPRSP" description="Number of snoop response messages without data received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="15" advanced="yes" counter="L2_RD_MSG_OUT_SNPREQ" title="L2_RD_MSG_OUT_SNPREQ" name="L2_RD_MSG_OUT_SNPREQ" description="Number of snoop request messages sent by the L2C to internal requesters" units="requests"/>
|
||||
<event offset="16" advanced="yes" counter="L2_RD_MSG_IN" title="L2_RD_MSG_IN" name="L2_RD_MSG_IN" description="Number of read messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="17" advanced="yes" counter="L2_RD_MSG_IN_STALL" title="L2_RD_MSG_IN_STALL" name="L2_RD_MSG_IN_STALL" description="Number of cycles input read messages are stalled by the L2C" units="cycles"/>
|
||||
<event offset="18" advanced="yes" counter="L2_WR_MSG_IN" title="L2_WR_MSG_IN" name="L2_WR_MSG_IN" description="Number of write messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="19" advanced="yes" counter="L2_WR_MSG_IN_STALL" title="L2_WR_MSG_IN_STALL" name="L2_WR_MSG_IN_STALL" description="Number of cycles input write messages are stalled by the L2C" units="cycles"/>
|
||||
<event offset="20" advanced="yes" counter="L2_SNP_MSG_IN" title="L2_SNP_MSG_IN" name="L2_SNP_MSG_IN" description="Number of snoop messages received by the L2C from internal requesters" units="requests"/>
|
||||
<event offset="21" advanced="yes" counter="L2_SNP_MSG_IN_STALL" title="L2_SNP_MSG_IN_STALL" name="L2_SNP_MSG_IN_STALL" description="Number of cycles input snoop messages are stalled by the L2C" units="cycles"/>
|
||||
<event offset="22" advanced="yes" counter="L2_RD_MSG_OUT" title="L2_RD_MSG_OUT" name="L2_RD_MSG_OUT" description="Number of read messages sent by the L2C to internal requesters" units="requests"/>
|
||||
<event offset="23" advanced="yes" counter="L2_RD_MSG_OUT_STALL" title="L2_RD_MSG_OUT_STALL" name="L2_RD_MSG_OUT_STALL" description="Number of cycles read messages that are stalled by internal requesters" units="cycles"/>
|
||||
<event offset="24" advanced="yes" counter="L2_WR_MSG_OUT" title="L2_WR_MSG_OUT" name="L2_WR_MSG_OUT" description="Number of write messages sent by the L2C to internal requesters" units="requests"/>
|
||||
<event offset="25" advanced="yes" counter="L2_ANY_LOOKUP" title="L2_ANY_LOOKUP" name="L2_ANY_LOOKUP" description="Number of L2C lookups" units="requests"/>
|
||||
<event offset="26" advanced="yes" counter="L2_READ_LOOKUP" title="L2_READ_LOOKUP" name="L2_READ_LOOKUP" description="Number of L2C lookups performed by read transactions" units="transactions"/>
|
||||
<event offset="27" advanced="yes" counter="L2_WRITE_LOOKUP" title="L2_WRITE_LOOKUP" name="L2_WRITE_LOOKUP" description="Number of L2C lookups performed by write transactions" units="transactions"/>
|
||||
<event offset="28" advanced="yes" counter="L2_EXT_SNOOP_LOOKUP" title="L2_EXT_SNOOP_LOOKUP" name="L2_EXT_SNOOP_LOOKUP" description="Number of L2C lookups performed by external snoop transactions" units="transactions"/>
|
||||
<event offset="29" advanced="yes" counter="L2_EXT_READ" title="L2_EXT_READ" name="L2_EXT_READ" description="Number of external read transactions" units="transactions"/>
|
||||
<event offset="30" advanced="yes" counter="L2_EXT_READ_NOSNP" title="L2_EXT_READ_NOSNP" name="L2_EXT_READ_NOSNP" description="Number of external ReadNoSnoop transactions" units="transactions"/>
|
||||
<event offset="31" advanced="yes" counter="L2_EXT_READ_UNIQUE" title="L2_EXT_READ_UNIQUE" name="L2_EXT_READ_UNIQUE" description="Number of external ReadUnique or ReadOnce transactions" units="transactions"/>
|
||||
<event offset="32" advanced="yes" counter="L2_EXT_READ_BEATS" title="L2_EXT_READ_BEATS" name="L2_EXT_READ_BEATS" description="Number of external read data beats" units="beats"/>
|
||||
<event offset="33" advanced="yes" counter="L2_EXT_AR_STALL" title="L2_EXT_AR_STALL" name="L2_EXT_AR_STALL" description="Number of cycles read address (AR) is stalled" units="cycles"/>
|
||||
<event offset="34" advanced="yes" counter="L2_EXT_AR_CNT_Q1" title="L2_EXT_AR_CNT_Q1" name="L2_EXT_AR_CNT_Q1" description="Number of external read transactions when 0-25% outstanding" units="transactions"/>
|
||||
<event offset="35" advanced="yes" counter="L2_EXT_AR_CNT_Q2" title="L2_EXT_AR_CNT_Q2" name="L2_EXT_AR_CNT_Q2" description="Number of external read transactions when 25-50% outstanding" units="transactions"/>
|
||||
<event offset="36" advanced="yes" counter="L2_EXT_AR_CNT_Q3" title="L2_EXT_AR_CNT_Q3" name="L2_EXT_AR_CNT_Q3" description="Number of external read transactions when 50-75% outstanding" units="transactions"/>
|
||||
<event offset="37" advanced="yes" counter="L2_EXT_RRESP_0_127" title="L2_EXT_RRESP_0_127" name="L2_EXT_RRESP_0_127" description="Number of read responses with 0-127 cycle latency" units="cycles"/>
|
||||
<event offset="38" advanced="yes" counter="L2_EXT_RRESP_128_191" title="L2_EXT_RRESP_128_191" name="L2_EXT_RRESP_128_191" description="Number of read responses with 128-191 cycle latency" units="cycles"/>
|
||||
<event offset="39" advanced="yes" counter="L2_EXT_RRESP_192_255" title="L2_EXT_RRESP_192_255" name="L2_EXT_RRESP_192_255" description="Number of read responses with 192-255 cycle latency" units="cycles"/>
|
||||
<event offset="40" advanced="yes" counter="L2_EXT_RRESP_256_319" title="L2_EXT_RRESP_256_319" name="L2_EXT_RRESP_256_319" description="Number of read responses with 256-319 cycle latency" units="cycles"/>
|
||||
<event offset="41" advanced="yes" counter="L2_EXT_RRESP_320_383" title="L2_EXT_RRESP_320_383" name="L2_EXT_RRESP_320_383" description="Number of read responses with 320-383 cycle latency" units="cycles"/>
|
||||
<event offset="42" advanced="yes" counter="L2_EXT_WRITE" title="L2_EXT_WRITE" name="L2_EXT_WRITE" description="Number of external write transactions" units="transactions"/>
|
||||
<event offset="43" advanced="yes" counter="L2_EXT_WRITE_NOSNP_FULL" title="L2_EXT_WRITE_NOSNP_FULL" name="L2_EXT_WRITE_NOSNP_FULL" description="Number of external WriteNoSnpFull transactions" units="transactions"/>
|
||||
<event offset="44" advanced="yes" counter="L2_EXT_WRITE_NOSNP_PTL" title="L2_EXT_WRITE_NOSNP_PTL" name="L2_EXT_WRITE_NOSNP_PTL" description="Number of external WriteNoSnpPtl transactions" units="transactions"/>
|
||||
<event offset="45" advanced="yes" counter="L2_EXT_WRITE_SNP_FULL" title="L2_EXT_WRITE_SNP_FULL" name="L2_EXT_WRITE_SNP_FULL" description="Number of external WriteBackFull or WriteUniqueFull transactions" units="transactions"/>
|
||||
<event offset="46" advanced="yes" counter="L2_EXT_WRITE_SNP_PTL" title="L2_EXT_WRITE_SNP_PTL" name="L2_EXT_WRITE_SNP_PTL" description="Number of external WriteBackPtl or WriteUniquePtl transactions" units="transactions"/>
|
||||
<event offset="47" advanced="yes" counter="L2_EXT_WRITE_BEATS" title="L2_EXT_WRITE_BEATS" name="L2_EXT_WRITE_BEATS" description="Number of external write data beats" units="beats"/>
|
||||
<event offset="48" advanced="yes" counter="L2_EXT_W_STALL" title="L2_EXT_W_STALL" name="L2_EXT_W_STALL" description="Number of cycles write data (W) is stalled" units="cycles"/>
|
||||
<event offset="49" advanced="yes" counter="L2_EXT_AW_CNT_Q1" title="L2_EXT_AW_CNT_Q1" name="L2_EXT_AW_CNT_Q1" description="Number of external write transactions when the write buffer is 0-25% full" units="transactions"/>
|
||||
<event offset="50" advanced="yes" counter="L2_EXT_AW_CNT_Q2" title="L2_EXT_AW_CNT_Q2" name="L2_EXT_AW_CNT_Q2" description="Number of external write transactions when the write buffer is 25-50% full" units="transactions"/>
|
||||
<event offset="51" advanced="yes" counter="L2_EXT_AW_CNT_Q3" title="L2_EXT_AW_CNT_Q3" name="L2_EXT_AW_CNT_Q3" description="Number of external write transactions when the write buffer is 50-75% full" units="transactions"/>
|
||||
<event offset="52" advanced="yes" counter="L2_EXT_SNOOP" title="L2_EXT_SNOOP" name="L2_EXT_SNOOP" description="Number of external snoop transactions" units="transactions"/>
|
||||
<event offset="53" advanced="yes" counter="L2_EXT_SNOOP_STALL" title="L2_EXT_SNOOP_STALL" name="L2_EXT_SNOOP_STALL" description="Number of cycles external snoop requests are stalled" units="cycles"/>
|
||||
<event offset="54" advanced="yes" counter="L2_EXT_SNOOP_RESP_CLEAN" title="L2_EXT_SNOOP_RESP_CLEAN" name="L2_EXT_SNOOP_RESP_CLEAN" description="Number of external snoops that hit a clean line in the Level 2 cache" units="requests"/>
|
||||
<event offset="55" advanced="yes" counter="L2_EXT_SNOOP_RESP_DATA" title="L2_EXT_SNOOP_RESP_DATA" name="L2_EXT_SNOOP_RESP_DATA" description="Number of external snoops that hit in the Level 2 cache and return data" units="requests"/>
|
||||
<event offset="56" advanced="yes" counter="L2_EXT_SNOOP_INTERNAL" title="L2_EXT_SNOOP_INTERNAL" name="L2_EXT_SNOOP_INTERNAL" description="Number of external snoops that cause snoops to Level 1 caches" units="requests"/>
|
||||
<event offset="59" advanced="yes" counter="L2_CE_MSG_IN" title="L2_CE_MSG_IN" name="L2_CE_MSG_IN" description="Number of internal clean engine messages" units="requests"/>
|
||||
<event offset="60" advanced="yes" counter="L2_CE_LOOKUP" title="L2_CE_LOOKUP" name="L2_CE_LOOKUP" description="Number of lookups performed by clean engine flush transactions" units="transactions"/>
|
||||
<event offset="61" advanced="yes" counter="L2_CE_WB" title="L2_CE_WB" name="L2_CE_WB" description="Number of write-backs caused by clean engine flush transaction" units="transactions"/>
|
||||
<event offset="62" advanced="yes" counter="L2_CE_REPLAY" title="L2_CE_REPLAY" name="L2_CE_REPLAY" description="Number of replayed clean engine flush transactions" units="transactions"/>
|
||||
</category>
|
||||
</metrics>
|
||||
345
src/panfrost/perf/generated/G1.xml
Normal file
345
src/panfrost/perf/generated/G1.xml
Normal file
|
|
@ -0,0 +1,345 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G1">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliBinningQueueActiveCy" title="Binning phase queue active cycles" description="The number of cycles that the binning phase queue is processing work. The binning phase includes position shading, culling, and binning." units="cycles" equation="(ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)" />
|
||||
<event name="MaliBinningQueueAssignStallCy" title="Binning phase queue endpoint stall cycles" description="The number of cycles the binning phase queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_TILER_READY_BLOCKED" offset="70" />
|
||||
<event name="MaliBinningQueueIRQActiveCy" title="Binning phase queue interrupt pending cycles" description="The number of cycles that the binning phase queue IRQ was pending." units="cycles" counter="ITER_TILER_IRQ_ACTIVE" offset="68" />
|
||||
<event name="MaliBinningQueueJob" title="Binning phase jobs" description="The number of binning phase jobs processed." units="jobs" counter="ITER_TILER_JOB_COMPLETED" offset="65" />
|
||||
<event name="MaliBinningQueueTask" title="Binning phase tasks" description="The number of binning phase tasks processed." units="tasks" counter="ITER_TILER_IDVS_TASK_COMPLETED" offset="66" />
|
||||
<event name="MaliBinningQueueUtil" title="Binning phase queue utilization" description="The binning phase queue utilization compared against the GPU active cycles. The binning phase includes position shading, culling, and binning." units="percent" equation="(((ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliBinningQueuedCy" title="Binning phase work queued cycles" description="The number of cycles that the binning phase queue has work queued. The binning phase includes position shading, culling, and binning." units="cycles" counter="ITER_TILER_ACTIVE" offset="64" />
|
||||
<event name="MaliCS0WaitStallCy" title="Command stream 0 wait stall cycles" description="The number of cycles that command stream interface 0 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF0_WAIT_BLOCKED" offset="84" />
|
||||
<event name="MaliCS1WaitStallCy" title="Command stream 1 wait stall cycles" description="The number of cycles that command stream interface 1 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF1_WAIT_BLOCKED" offset="90" />
|
||||
<event name="MaliCS2WaitStallCy" title="Command stream 2 wait stall cycles" description="The number of cycles that command stream interface 2 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF2_WAIT_BLOCKED" offset="96" />
|
||||
<event name="MaliCS3WaitStallCy" title="Command stream 3 wait stall cycles" description="The number of cycles that command stream interface 3 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF3_WAIT_BLOCKED" offset="102" />
|
||||
<event name="MaliCS4WaitStallCy" title="Command stream 4 wait stall cycles" description="The number of cycles that command stream interface 4 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF4_WAIT_BLOCKED" offset="108" />
|
||||
<event name="MaliCS5WaitStallCy" title="Command stream 5 wait stall cycles" description="The number of cycles that command stream interface 5 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF5_WAIT_BLOCKED" offset="114" />
|
||||
<event name="MaliCSDoorbellIRQCy" title="Command stream doorbell interrupt pending cycles" description="The number of cycles that command stream doorbell has an IRQ pending." units="cycles" counter="DOORBELL_IRQ_ACTIVE" offset="14" />
|
||||
<event name="MaliCSFCEUActiveCy" title="Command execution unit active cycles" description="The number of cycles that the CEU is processing commands." units="cycles" counter="CEU_ACTIVE" offset="16" />
|
||||
<event name="MaliCSFCEUUtil" title="Command execution unit utilization" description="The CSF command execution unit utilization compared against the GPU active cycles." units="percent" equation="((CEU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFCS0ActiveCy" title="Command stream 0 active cycles" description="The number of cycles that command stream interface 0 contained an enabled command stream." units="cycles" counter="CSHWIF0_ENABLED" offset="80" />
|
||||
<event name="MaliCSFCS1ActiveCy" title="Command stream 1 active cycles" description="The number of cycles that command stream interface 1 contained an enabled command stream." units="cycles" counter="CSHWIF1_ENABLED" offset="86" />
|
||||
<event name="MaliCSFCS2ActiveCy" title="Command stream 2 active cycles" description="The number of cycles that command stream interface 2 contained an enabled command stream." units="cycles" counter="CSHWIF2_ENABLED" offset="92" />
|
||||
<event name="MaliCSFCS3ActiveCy" title="Command stream 3 active cycles" description="The number of cycles that command stream interface 3 contained an enabled command stream." units="cycles" counter="CSHWIF3_ENABLED" offset="98" />
|
||||
<event name="MaliCSFCS4ActiveCy" title="Command stream 4 active cycles" description="The number of cycles that command stream interface 4 contained an enabled command stream." units="cycles" counter="CSHWIF4_ENABLED" offset="104" />
|
||||
<event name="MaliCSFCS5ActiveCy" title="Command stream 5 active cycles" description="The number of cycles that command stream interface 5 contained an enabled command stream." units="cycles" counter="CSHWIF5_ENABLED" offset="110" />
|
||||
<event name="MaliCSFLSUActiveCy" title="Command load/store unit active cycles" description="The number of cycles that the load-store unit is processing commands." units="cycles" counter="LSU_ACTIVE" offset="21" />
|
||||
<event name="MaliCSFLSUUtil" title="Command load/store unit utilization" description="The CSF load/store unit utilization compared against the GPU active cycles." units="percent" equation="((LSU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFMCUActiveCy" title="MCU active cycles" description="The number of cycles when the CSF front-end MCU is actively processing." units="cycles" counter="MCU_ACTIVE" offset="5" />
|
||||
<event name="MaliCSFMCUUtil" title="Microcontroller utilization" description="The CSF MCU utilization compared against the GPU active cycles." units="percent" equation="((MCU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueueActiveCy" title="Compute queue active cycles" description="The number of cycles that the compute queue is processing work." units="cycles" equation="(ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)" />
|
||||
<event name="MaliCompQueueAssignStallCy" title="Compute queue endpoint stall cycles" description="The number of cycles the compute queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_COMP_READY_BLOCKED" offset="38" />
|
||||
<event name="MaliCompQueueDrainStallCy" title="Compute queue endpoint drain stall cycles" description="The number of cycles the compute queue is waiting for endpoints to drain." units="cycles" counter="ITER_COMP_EP_DRAIN" offset="39" />
|
||||
<event name="MaliCompQueueIRQActiveCy" title="Compute queue interrupt pending cycles" description="The number of cycles that the compute queue IRQ was pending." units="cycles" counter="ITER_COMP_IRQ_ACTIVE" offset="36" />
|
||||
<event name="MaliCompQueueJob" title="Compute jobs" description="The number of compute jobs processed." units="jobs" counter="ITER_COMP_JOB_COMPLETED" offset="33" />
|
||||
<event name="MaliCompQueueTask" title="Compute tasks" description="The number of compute tasks processed." units="tasks" counter="ITER_COMP_TASK_COMPLETED" offset="34" />
|
||||
<event name="MaliCompQueueUtil" title="Compute queue utilization" description="The compute queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueuedCy" title="Compute work queued cycles" description="The number of cycles that the compute queue has work queued." units="cycles" counter="ITER_COMP_ACTIVE" offset="32" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="4" />
|
||||
<event name="MaliGPUAnyQueueActiveCy" title="Any queue active cycles" description="The number of cycles when any GPU queue is active." units="cycles" counter="GPU_ITER_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQ" title="GPU interrupts" description="The number of interrupts raised by the GPU to the CPU." units="interrupts" counter="GPU_IRQ_COUNT" offset="11" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="10" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliMainQueueActiveCy" title="Main phase queue active cycles" description="The number of cycles that the main phase queue is processing work. The main phase includes deferred vertex shading and all fragment shading." units="cycles" equation="(ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)" />
|
||||
<event name="MaliMainQueueAssignStallCy" title="Main phase queue endpoint stall cycles" description="The number of cycles the main phase queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_FRAG_READY_BLOCKED" offset="54" />
|
||||
<event name="MaliMainQueueIRQActiveCy" title="Main phase queue interrupt pending cycles" description="The number of cycles that the main phase queue IRQ was pending." units="cycles" counter="ITER_FRAG_IRQ_ACTIVE" offset="52" />
|
||||
<event name="MaliMainQueueJob" title="Main phase jobs" description="The number of main phase jobs processed." units="jobs" counter="ITER_FRAG_JOB_COMPLETED" offset="49" />
|
||||
<event name="MaliMainQueueTask" title="Main phase tasks" description="The number of fragment tasks processed." units="tasks" counter="ITER_FRAG_TASK_COMPLETED" offset="50" />
|
||||
<event name="MaliMainQueueUtil" title="Main phase queue utilization" description="The main phase queue utilization compared against the GPU active cycles. The main phase includes deferred vertex shading and all fragment shading." units="percent" equation="(((ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliMainQueuedCy" title="Main phase work queued cycles" description="The number of cycles that the main phase queue has work queued. The main phase includes deferred vertex shading and all fragment shading." units="cycles" counter="ITER_FRAG_ACTIVE" offset="48" />
|
||||
<event name="MaliTilerQueueDrainStallCy" title="Binning phase queue endpoint drain stall cycles" description="The number of cycles the binning phase queue is waiting for endpoints to drain." units="cycles" counter="ITER_TILER_EP_DRAIN" offset="71" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheCleanUnique" title="Input internal clean unique requests" description="The number of L2 cache line clean unique requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_CU" offset="13" />
|
||||
<event name="MaliL2CacheEvict" title="Input internal evict requests" description="The number of L2 cache line evict requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_EVICT" offset="12" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="13" />
|
||||
<event name="MaliL2CacheFlushCy" title="L2 cache flush cycles" description="The number of cycles spent flushing GPU L2 caches." units="cycles" counter="CACHE_FLUSH_CYCLES" offset="12" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="max((((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)) - (EXEC_INSTR_SLOT_1)), (EXEC_INSTR_SLOT_1), (EXEC_INSTR_SFU) * 4)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="((max((((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)) - (EXEC_INSTR_SLOT_1)), (EXEC_INSTR_SLOT_1), (EXEC_INSTR_SFU) * 4)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAnyActiveCy" title="Any workload active cycles" description="The number of cycles when the shader core is processing either a non-fragment workload or a fragment workload." units="cycles" counter="SHADER_CORE_ACTIVE" offset="53" />
|
||||
<event name="MaliAnyUtil" title="Shader core clock ratio" description="An estimate of shader core use relative to the GPU top-level clock." units="percent" equation="((SHADER_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliAttrIssueCy" title="Attribute unit issue cycles" description="The total number of attribute unit issue cycles." units="cycles" counter="ATTR_ACTIVE" offset="108" />
|
||||
<event name="MaliAttrUtil" title="Attribute unit utilization" description="The percentage utilization of the attribute unit." units="percent" equation="((ATTR_ACTIVE) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliBlendIssueCy" title="Blend unit issue cycles" description="The total number of blend unit issue cycles." units="cycles" counter="BLEND_ACTIVE" offset="107" />
|
||||
<event name="MaliBlendUtil" title="Blend unit utilization" description="The percentage utilization of the blend unit." units="percent" equation="((BLEND_ACTIVE) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliCompOrBinningActiveCy" title="Compute or binning phase active cycles" description="The number of cycles when the shader core is processing some compute or binning phase workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliCompOrBinningUtil" title="Compute or binning phase utilization" description="The utilization of the shader core compute or binning phase path." units="percent" equation="((COMPUTE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFragWarpOcc" title="Fragment warp occupancy" description="The thread occupancy of the fragment warps." units="percent" equation="((FRAG_SHADER_THREADS) / ((FRAG_WARPS) * (16))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliDefVertWarp" title="Deferred vertex warps" description="The number of deferred vertex warps created." units="warps" counter="DVS_WARPS" offset="106" />
|
||||
<event name="MaliEngArithInstr" title="Arithmetic instruction issue cycles" description="The total number of instructions issued to the FMA, CVT, and SFU pipes." units="instructions" equation="(EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)" />
|
||||
<event name="MaliEngAttrBackpressureCy" title="Attribute unit backpressure cycles" description="The number of cycles new work could not be sent to the attribute unit." units="cycles" counter="EXEC_MSG_STALLED_ATTR" offset="117" />
|
||||
<event name="MaliEngAttrBackpressureRate" title="Attribute unit backpressure percentage" description="The percentage of cycles new work could not be sent to the attribute unit." units="percent" equation="((EXEC_MSG_STALLED_ATTR) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngBlendBackpressureCy" title="Blend unit backpressure cycles" description="The number of cycles new work could not be sent to the blend unit." units="cycles" counter="EXEC_MSG_STALLED_BLEND" offset="114" />
|
||||
<event name="MaliEngBlendBackpressureRate" title="Blend unit backpressure percentage" description="The percentage of cycles new work could not be sent to the blend unit." units="percent" equation="((EXEC_MSG_STALLED_BLEND) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngCVTInstr" title="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions" counter="EXEC_INSTR_CVT" offset="28" />
|
||||
<event name="MaliEngCVTPipeUtil" title="CVT pipe utilization" description="Defines the utilization of the CVT pipes." units="percent" equation="((EXEC_INSTR_CVT) / (2 * (EXEC_CORE_ACTIVE))) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="31" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngFMAInstr" title="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions" counter="EXEC_INSTR_FMA" offset="27" />
|
||||
<event name="MaliEngFMAPipeUtil" title="FMA pipe utilization" description="The utilization of the FMA pipes." units="percent" equation="((EXEC_INSTR_FMA) / (2 * (EXEC_CORE_ACTIVE))) * 100" />
|
||||
<event name="MaliEngLSBackpressureCy" title="Load/store unit backpressure cycles" description="The number of cycles new work could not be sent to the load/store unit." units="cycles" counter="EXEC_MSG_STALLED_LSC" offset="116" />
|
||||
<event name="MaliEngLSBackpressureRate" title="Load/store unit backpressure percentage" description="The percentage of cycles new work could not be sent to the load/store unit." units="percent" equation="((EXEC_MSG_STALLED_LSC) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngNarrowInstr" title="Narrow arithmetic instructions" description="The number of narrow arithmetic instructions." units="instructions" counter="EXEC_INSTR_NARROW" offset="5" />
|
||||
<event name="MaliEngNarrowInstrRate" title="Narrow arithmetic percentage" description="The percentage of arithmetic instructions that operate on 8/16-bit types." units="percent" equation="((EXEC_INSTR_NARROW) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngRTUBackpressureCy" title="Ray tracing unit backpressure cycles" description="The number of cycles new work could not be sent to the ray tracing unit." units="cycles" counter="EXEC_MSG_STALLED_RTU" offset="109" />
|
||||
<event name="MaliEngRTUBackpressureRate" title="Ray tracing unit backpressure percentage" description="The percentage of cycles new work could not be sent to the ray tracing unit." units="percent" equation="((EXEC_MSG_STALLED_RTU) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSFUInstr" title="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions" counter="EXEC_INSTR_SFU" offset="29" />
|
||||
<event name="MaliEngSFUPipeUtil" title="SFU pipe utilization" description="The utilization of the SFU pipe." units="percent" equation="(((EXEC_INSTR_SFU) * 4) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSWBlendInstr" title="Blend shader instructions" description="The number of blend shader invocations run." units="instructions" counter="CALL_BLEND_SHADER" offset="34" />
|
||||
<event name="MaliEngSWBlendRate" title="Shader blend percentage" description="The percentage of fragments that use shader-based blending." units="percent" equation="(((CALL_BLEND_SHADER) * 4) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliEngSlot0IssueCy" title="Slot 0 arithmetic issue cycles" description="The number of arithmetic issue cycles to slot 0." units="cycles" equation="((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)) - (EXEC_INSTR_SLOT_1)" />
|
||||
<event name="MaliEngSlot1IssueCy" title="Slot 1 arithmetic issue cycles" description="The number of arithmetic issue cycles to slot 1." units="cycles" counter="EXEC_INSTR_SLOT_1" offset="118" />
|
||||
<event name="MaliEngSlotAnyIssueCy" title="Any slot arithmetic issue cycles" description="The number of arithmetic issue cycles that issue to either issue slot." units="cycles" counter="EXEC_ISSUE_SLOT_ANY" offset="119" />
|
||||
<event name="MaliEngStarveCy" title="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles" counter="EXEC_STARVE_ARITH" offset="33" />
|
||||
<event name="MaliEngStarveICacheCy" title="Processing unit I-cache starvation cycles" description="The number of cycles when the processing unit is starved of work due to I-cache misses." units="cycles" counter="EXEC_STARVE_ICACHE" offset="32" />
|
||||
<event name="MaliEngTexBackpressureCy" title="Texture unit backpressure cycles" description="The number of cycles new work could not be sent to the texture unit." units="cycles" counter="EXEC_MSG_STALLED_TEX" offset="112" />
|
||||
<event name="MaliEngTexBackpressureRate" title="Texture unit backpressure percentage" description="The percentage of cycles new work could not be sent to the texture unit." units="percent" equation="((EXEC_MSG_STALLED_TEX) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngVarBackpressureCy" title="Varying unit backpressure cycles" description="The number of cycles new work could not be sent to the varying unit." units="cycles" counter="EXEC_MSG_STALLED_VARY" offset="113" />
|
||||
<event name="MaliEngVarBackpressureRate" title="Varying unit backpressure percentage" description="The percentage of cycles new work could not be sent to the varying unit." units="percent" equation="((EXEC_MSG_STALLED_VARY) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngZSBackpressureCy" title="ZS unit backpressure cycles" description="The number of cycles new work could not be sent to the depth/stencil test unit." units="cycles" counter="EXEC_MSG_STALLED_ZS" offset="115" />
|
||||
<event name="MaliEngZSBackpressureRate" title="ZS unit backpressure percentage" description="The percentage of cycles new work could not be sent to the depth/stencil test unit." units="percent" equation="((EXEC_MSG_STALLED_ZS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragInputPrim" title="Input fragment primitives" description="The number of unique primitives loaded by the fragment front-end." units="primitives" equation="((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS)" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (4 * (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (4 * (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliFragMainPassStallCy" title="Fragment main pass stall cycles" description="The number of cycles when the fragment main pass is stalled waiting for prepass results." units="cycles" counter="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" offset="105" />
|
||||
<event name="MaliFragMainPassStallRate" title="Fragment main pass stall percentage" description="The percentage of cycles when the fragment main pass is stalled by the fragment prepass." units="percent" equation="((FRAG_MAIN_PASS_STALLED_BY_PRE_PASS) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragMainThread" title="Fragment main pass threads" description="The number of fragment threads started in the main pass." units="threads" equation="((FRAG_WARPS) - (FRAG_WARPS_PRE_PASS)) * (16)" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="(FRAG_SHADER_THREADS) / ((ITER_FRAG_TASK_COMPLETED) * (64) * (64))" />
|
||||
<event name="MaliFragPrepassCullPrim" title="Fragment prepass culled primitives" description="The number of primitives culled by the fragment prepass." units="primitives" counter="FRAG_PRIMITIVES_HSR_CULLED" offset="98" />
|
||||
<event name="MaliFragPrepassCullPrimRate" title="Fragment prepass primitive culling percentage" description="The percentage of primitives culled by the fragment prepass." units="percent" equation="((FRAG_PRIMITIVES_HSR_CULLED) / (((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrepassEZSUpdateQd" title="Fragment prepass early ZS updated quads" description="The number of quads that update the fragment prepass using early ZS." units="quads" counter="FRAG_QUADS_HSR_BUF_EZS_UPDATE" offset="101" />
|
||||
<event name="MaliFragPrepassKillQd" title="Fragment prepass killed quads" description="The number of quads that are killed by the fragment prepass." units="quads" counter="FRAG_QUADS_HSR_BUF_KILLED" offset="103" />
|
||||
<event name="MaliFragPrepassKillRate" title="Fragment prepass killed quad percentage" description="The percentage of tested quads that are killed by the fragment prepass." units="percent" equation="((FRAG_QUADS_HSR_BUF_KILLED) / (FRAG_QUADS_HSR_BUF_TEST)) * 100" />
|
||||
<event name="MaliFragPrepassPrim" title="Loaded fragment prepass primitives" description="The number of primitives loaded by the fragment front-end for the fragment prepass." units="primitives" counter="FRAG_PRIMITIVES_OUT_PRE_PASS" offset="99" />
|
||||
<event name="MaliFragPrepassPrimRate" title="Fragment prepass primitive percentage" description="The percentage of primitives processed by fragment prepass hidden surface removal." units="percent" equation="((FRAG_PRIMITIVES_OUT_PRE_PASS) / (((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrepassSkipPrimRate" title="Fragment prepass skipped primitive percentage" description="The percentage of primitives that are skipped by the fragment prepass." units="percent" equation="((FRAG_PRIMITIVES_HSR_DISABLED) / (((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrepassSkippedPrim" title="Fragment prepass skipped primitives" description="The number of primitives that are skipped by the fragment prepass." units="primitives" counter="FRAG_PRIMITIVES_HSR_DISABLED" offset="100" />
|
||||
<event name="MaliFragPrepassTestQd" title="Fragment prepass tested quads" description="The number of quads that are tested by the fragment prepass." units="quads" counter="FRAG_QUADS_HSR_BUF_TEST" offset="102" />
|
||||
<event name="MaliFragPrepassThread" title="Fragment prepass threads" description="The number of fragment threads started in the prepass." units="threads" equation="(FRAG_WARPS_PRE_PASS) * (16)" />
|
||||
<event name="MaliFragPrepassWarp" title="Fragment prepass warps" description="The number of fragment prepass warps created." units="warps" counter="FRAG_WARPS_PRE_PASS" offset="104" />
|
||||
<event name="MaliFragPrepassWarpRate" title="Fragment prepass warp percentage" description="The percentage of warps being processed by the fragment prepass." units="percent" equation="((FRAG_WARPS_PRE_PASS) / ((FRAG_WARPS) - (FRAG_WARPS_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrim" title="Loaded fragment primitives" description="The number of primitives loaded by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES_OUT" offset="97" />
|
||||
<event name="MaliFragRastCoarseQd" title="Rasterized coarse quads" description="The number of coarse quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_COARSE" offset="68" />
|
||||
<event name="MaliFragRastPartQd" title="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads" counter="FRAG_PARTIAL_QUADS_RAST" offset="10" />
|
||||
<event name="MaliFragRastPartQdRate" title="Partial coverage percentage" description="The percentage of rasterized fine quads that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_QUADS_RAST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragShadRate" title="Fragment shading rate" description="The percentage of coarse quads generated relative to fine quads rasterized." units="percent" equation="((FRAG_QUADS_COARSE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (16)) / 4" />
|
||||
<event name="MaliFragThread" title="All fragment threads" description="The number of fragment threads started in the prepass and main pass." units="threads" counter="FRAG_SHADER_THREADS" offset="69" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / (((FRAG_WARPS) - (FRAG_WARPS_PRE_PASS)) * (16))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (4 * (FRAG_PTILES))) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliMainActiveCy" title="Main phase active cycles" description="The number of cycles when the shader core is processing a main phase workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliMainUtil" title="Main phase utilization" description="The utilization of the shader core main phase path." units="percent" equation="((FRAG_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragTask" title="Non-main phase core tasks" description="The number of non-main phase tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (16)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (16))" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliRTUActiveCy" title="Ray tracing unit active cycles" description="The total number of ray tracing unit active cycles." units="cycles" counter="RT_ACTIVE" offset="122" />
|
||||
<event name="MaliRTUBLASCull" title="Ray tracing culled BLAS instances" description="The number of BLAS instances culled by by the ray tracing unit." units="issues" counter="RT_RAY_INSTANCE_CULL" offset="127" />
|
||||
<event name="MaliRTUBLASIssue" title="Ray tracing BLAS instances" description="The number of BLAS instances processed by the ray tracing unit." units="issues" counter="RT_RAY_INSTANCE" offset="125" />
|
||||
<event name="MaliRTUBoxIssue" title="Ray tracing box tests" description="The number of boxes issued to the ray tracing unit box test data path." units="issues" counter="RT_BOX_ISSUE_COUNT" offset="85" />
|
||||
<event name="MaliRTUBoxIssueCy" title="Ray tracing box tester issue cycles" description="The number of active issue cycles for the ray tracing box test unit." units="cycles" counter="RT_RAY_BOX_ISSUED" offset="78" />
|
||||
<event name="MaliRTUCacheHit" title="Ray tracing unit cache hit" description="The number of hits in the ray tracing unit cache." units="requests" counter="RT_CACHE_READ_HIT" offset="110" />
|
||||
<event name="MaliRTUCacheMiss" title="Ray tracing unit cache miss" description="The number of misses in the ray tracing unit cache." units="requests" counter="RT_CACHE_READ_MISS" offset="111" />
|
||||
<event name="MaliRTUFirstHitTerm" title="Ray tracing first hit terminations" description="The number of rays that terminate on their first hit." units="rays" counter="RT_TERM_FIRST_HIT" offset="82" />
|
||||
<event name="MaliRTUIssueCy" title="Ray tracing unit issue cycles" description="The number of cycles the ray tracing unit was issuing work." units="cycles" equation="max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))" />
|
||||
<event name="MaliRTUMiss" title="Ray tracing triangle test misses" description="The number of triangle intersection tests that do not intersect." units="rays" counter="RT_MISS" offset="83" />
|
||||
<event name="MaliRTUNewTraceInstr" title="Ray tracing new trace messages" description="The number of ray tracing messages starting new rays." units="requests" counter="RT_TRACE_MSG_NEW" offset="120" />
|
||||
<event name="MaliRTUNonOpaqueHit" title="Ray tracing non-opaque triangle hits" description="The number of non-opaque triangle hits." units="tests" counter="RT_NON_OPAQUE_HIT" offset="81" />
|
||||
<event name="MaliRTUOpaqueHit" title="Ray tracing opaque triangle hits" description="The number of opaque triangle hits." units="tests" counter="RT_OPAQUE_HIT" offset="80" />
|
||||
<event name="MaliRTUPrimCull" title="Ray tracing culled primitives" description="The number of primitives culled by the ray tracing unit testers." units="issues" counter="RT_RAY_TRI_CULL" offset="126" />
|
||||
<event name="MaliRTURay" title="Ray tracing started rays" description="The number of rays started." units="rays" counter="RT_RAYS_STARTED" offset="84" />
|
||||
<event name="MaliRTUResumeTraceInstr" title="Ray tracing resume trace messages" description="The number of ray tracing messages resuming existing rays." units="requests" counter="RT_TRACE_MSG_RESUME" offset="121" />
|
||||
<event name="MaliRTUResumeTraceRays" title="Ray tracing resumed rays" description="The number of rays that are resumed after an initial hit or intersection shader." units="rays" counter="RT_TRACE_RESUME" offset="123" />
|
||||
<event name="MaliRTUStackOverflows" title="Ray tracing deep traversals" description="The number of rays that are using a deep traversal stack." units="rays" counter="RT_TRAVERSAL_STACK_OVERFLOW" offset="77" />
|
||||
<event name="MaliRTUTLASBoxIssue" title="Ray tracing TLAS box tests" description="The number of boxes from the TLAS issued to the ray tracing unit box test data path." units="issues" counter="RT_RAY_BOX_TLAS" offset="124" />
|
||||
<event name="MaliRTUTriCull" title="Ray tracing triangle primitive tests" description="The number of triangles issued to the ray tracing unit triangle test data path." units="issues" counter="RT_TRI_ISSUE_COUNT" offset="86" />
|
||||
<event name="MaliRTUTriIssueCy" title="Ray tracing triangle tester issue cycles" description="The number of active issue cycles for the ray tracing triangle test unit." units="cycles" counter="RT_RAY_TRI_ISSUED" offset="79" />
|
||||
<event name="MaliRTUUtil" title="Ray tracing unit utilization" description="The percentage utilization of the ray tracing unit." units="percent" equation="((max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" counter="BEATS_WR_LSC" offset="61" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_WR_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="((BEATS_WR_LSC) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusOtherWrBt" title="Miscellaneous write beats to L2 memory system" description="The number of write beats sent by any unit that is not specifically identified." units="beats" counter="BEATS_WR_OTHER" offset="63" />
|
||||
<event name="MaliSCBusOtherWrBy" title="Other unit write bytes to L2 memory system" description="The number of write bytes sent by any unit that is not specifically identified." units="bytes" equation="(BEATS_WR_OTHER) * (16)" />
|
||||
<event name="MaliSCBusRTUExtRdBt" title="Ray tracing unit read beats from external memory" description="The number of read beats received by the ray tracing unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_RTU_EXT" offset="41" />
|
||||
<event name="MaliSCBusRTUExtRdBy" title="Ray tracing unit read bytes from external memory" description="The total number of bytes read from the external memory system by the ray tracing unit." units="bytes" equation="(BEATS_RD_RTU_EXT) * (16)" />
|
||||
<event name="MaliSCBusRTUL2RdBt" title="Ray tracing unit read beats from L2 cache" description="The number of read beats received by the ray tracing unit." units="beats" counter="BEATS_RD_RTU" offset="40" />
|
||||
<event name="MaliSCBusRTUL2RdBy" title="Ray tracing unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the ray tracing unit." units="bytes" equation="(BEATS_RD_RTU) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((ITER_FRAG_TASK_COMPLETED) * (64) * (64))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="(max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))) / ((((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)) * 4)" />
|
||||
<event name="MaliTexCacheComplexLoadCy" title="Complex texture load cycles" description="The number of cycles loading complex texture formats." units="cycles" counter="TEX_CFCH_NUM_RP_OPERATIONS" offset="93" />
|
||||
<event name="MaliTexCacheLookupCy" title="Texture cache lookup cycles" description="The number of cycles returning data from the texture cache." units="cycles" counter="TEX_TFCH_NUM_TCL_OPERATIONS" offset="92" />
|
||||
<event name="MaliTexCacheSimpleLoadCy" title="Simple texture load cycles" description="The number of cycles loading simple texture formats." units="cycles" counter="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" offset="88" />
|
||||
<event name="MaliTexClkActiveCy" title="Texture unit clock active cycles" description="The number of cycles the texture unit was active." units="cycles" counter="TEX_TEXP_CLK_ACTIVE" offset="96" />
|
||||
<event name="MaliTexClkStarvedCy" title="Texture causing starvation cycles" description="The number of cycles the texture unit was active but did not return a texture sample." units="cycles" counter="TEX_MSGI_CLK_STARVED" offset="95" />
|
||||
<event name="MaliTexDataFetchStallCy" title="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles" counter="TEX_TFCH_CLK_STALLED" offset="37" />
|
||||
<event name="MaliTexDescStallCy" title="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles" counter="TEX_DFCH_CLK_STALLED" offset="36" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="39" />
|
||||
<event name="MaliTexFiltStallCy" title="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" offset="38" />
|
||||
<event name="MaliTexInBt" title="Texture message read beats" description="The number of texture request message data beats." units="beats" counter="TEX_MSGI_NUM_FLITS" offset="35" />
|
||||
<event name="MaliTexInBusUtil" title="Texture input bus utilization" description="The percentage load on the texture message input bus." units="percent" equation="((TEX_MSGI_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexIndexCy" title="Texture index calculation cycles" description="The number of cycles computing texel index values." units="cycles" counter="TEX_TIDX_NUM_OPERATIONS" offset="94" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))" />
|
||||
<event name="MaliTexL1CacheLoadCy" title="L1 texture cache load cycles" description="The number of cycles the L1 cache is being loaded." units="cycles" counter="TEX_CFCH_NUM_OUTPUT_OPERATIONS" offset="87" />
|
||||
<event name="MaliTexL1CacheLookupCy" title="L1 texture cache lookup cycles" description="The number of cycles the L1 cache is being accessed." units="cycles" counter="TEX_CFCH_NUM_L1_CT_OPERATIONS" offset="90" />
|
||||
<event name="MaliTexL1CacheOutputCy" title="L1 texture cache output cycles" description="The number of cycles the L1 cache is returning data." units="cycles" counter="TEX_CFCH_NUM_L1_CL_OPERATIONS" offset="89" />
|
||||
<event name="MaliTexOutBt" title="Texture message write beats" description="The number of texture response message data beats." units="beats" counter="TEX_MSGO_NUM_FLITS" offset="43" />
|
||||
<event name="MaliTexOutBusUtil" title="Texture output bus utilization" description="The percentage load on the texture message output bus." units="percent" equation="((TEX_MSGO_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexOutMsg" title="Texture messages" description="The number of output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_MSG" offset="42" />
|
||||
<event name="MaliTexOutSingleMsg" title="Texture messages with single quad" description="The number of single quad output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_SINGLE_QUAD_MSG" offset="91" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" equation="((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)) * 4" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="((max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (4)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (4)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceCullPrim" title="Facing test culled primitives" description="The number of primitives that are culled by facing tests." units="primitives" counter="PRIM_FACE_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceCullRate" title="Facing plane test cull percentage" description="The percentage of primitives culled by the facing test." units="percent" equation="((PRIM_FACE_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED) - (PRIM_SCISSOR_CULLED))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPlaneCullPrim" title="Frustum test culled primitives" description="The number of primitives that are culled by frustum tests." units="primitives" counter="PRIM_FRUSTUM_CULLED" offset="13" />
|
||||
<event name="MaliGeomPlaneCullRate" title="Frustum test cull percentage" description="The percentage of primitives culled by the frustum test." units="percent" equation="((PRIM_FRUSTUM_CULLED) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadPartTask" title="Partial tiler position shading requests" description="The number of partial position shading requests in the tiler geometry flow." units="requests" counter="POS_SHADER_PARTIAL_WARPS" offset="22" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (16)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (16)) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED) - (PRIM_SCISSOR_CULLED) - (PRIM_FACE_CULLED))) * 100" />
|
||||
<event name="MaliGeomScissorCullPrim" title="Scissor test culled primitives" description="The number of primitives that are culled by the scissor test." units="primitives" counter="PRIM_SCISSOR_CULLED" offset="70" />
|
||||
<event name="MaliGeomScissorCullRate" title="Scissor test cull percentage" description="The percentage of primitives culled by the scissor test." units="percent" equation="((PRIM_SCISSOR_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadPartTask" title="Partial tiler varying shading requests" description="The number of partial varying shading requests in the tiler geometry flow." units="requests" counter="VAR_SHADER_PARTIAL_WARPS" offset="37" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="36" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (16)" />
|
||||
<event name="MaliGeomVisibleDVSPrim" title="Visible primitives using DVS" description="The number of primitives using DVS that are visible after culling." units="primitives" counter="PRIM_VISIBLE_DVS" offset="71" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerPrimAsPosShadStallCy" title="Primitive assembly position shading stall cycles" description="The number of cycles when primitive assembly is waiting for position shading." units="cycles" counter="PRIMASSY_POS_SHADER_WAIT" offset="64" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
</category>
|
||||
</metrics>
|
||||
247
src/panfrost/perf/generated/G31.xml
Normal file
247
src/panfrost/perf/generated/G31.xml
Normal file
|
|
@ -0,0 +1,247 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G31">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="(EXEC_INSTR_COUNT)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="(((EXEC_INSTR_COUNT)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="29" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / (EXEC_INSTR_COUNT)) * 100" />
|
||||
<event name="MaliEngInstr" title="Arithmetic instruction issue cycles" description="The number of instructions run per warp." units="instructions" counter="EXEC_INSTR_COUNT" offset="28" />
|
||||
<event name="MaliEngStarveCy" title="Execution engine starvation cycles" description="The number of cycles when no new threads are available to run." units="cycles" counter="EXEC_INSTR_STARVING" offset="30" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (4)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragPartWarp" title="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps" counter="FRAG_PARTIAL_WARPS" offset="10" />
|
||||
<event name="MaliFragPartWarpRate" title="Partial coverage percentage" description="The percentage of warps that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_WARPS) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="(FRAG_WARPS)" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (4)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (4))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (4)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (4))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="63" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="61" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / ((TEX_MSGI_NUM_QUADS) * 4)" />
|
||||
<event name="MaliTexCacheCompressFetch" title="Compressed texture line fetch requests" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" offset="41" />
|
||||
<event name="MaliTexCacheCompressFetchRate" title="Texture data fetches from compressed lines" description="The percentage of texture line fetches that are from block compressed textures." units="percent" equation="((TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED) / (TEX_TFCH_NUM_LINES_FETCHED)) * 100" />
|
||||
<event name="MaliTexCacheFetch" title="Texture line fetch requests" description="The number of texture line fetches from the L2 cache." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED" offset="40" />
|
||||
<event name="MaliTexCacheLookup" title="Texture cache lookup requests" description="The number of texture cache lookup cycles." units="requests" counter="TEX_TFCH_NUM_OPERATIONS" offset="42" />
|
||||
<event name="MaliTexCacheUtil" title="Texture unit cache utilization" description="The percentage utilization of the texturing unit cache lookup path." units="percent" equation="((TEX_TFCH_NUM_OPERATIONS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="43" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexMipInstrRate" title="Texture accesses using mipmapping percentage" description="The percentage of texture operations accessing mipmapped textures." units="percent" equation="((TEX_DFCH_NUM_PASSES_MIP_MAP) / (TEX_DFCH_NUM_PASSES)) * 100" />
|
||||
<event name="MaliTexQuadPass" title="Texture quad issues" description="The number of quad-width filtering passes." units="issues" counter="TEX_DFCH_NUM_PASSES" offset="36" />
|
||||
<event name="MaliTexQuadPassDescMiss" title="Texture quad descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests" counter="TEX_DFCH_NUM_PASSES_MISS" offset="37" />
|
||||
<event name="MaliTexQuadPassMip" title="Mipmapped texture quad issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" offset="38" />
|
||||
<event name="MaliTexQuadPassTri" title="Trilinear filtered texture quad issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" offset="39" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" counter="TEX_MSGI_NUM_QUADS" offset="35" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(TEX_MSGI_NUM_QUADS) * 4" />
|
||||
<event name="MaliTexTriInstrRate" title="Texture accesses using trilinear filter percentage" description="The percentage of texture operations using trilinear filtering." units="percent" equation="((TEX_TIDX_NUM_SPLIT_MIP_MAP) / (TEX_MSGI_NUM_QUADS)) * 100" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
<event name="MaliTilerWrBt" title="Internal write beats" description="The number of internal bus data write cycles made by the tiler." units="beats" counter="BUS_WRITE" offset="19" />
|
||||
</category>
|
||||
</metrics>
|
||||
247
src/panfrost/perf/generated/G51.xml
Normal file
247
src/panfrost/perf/generated/G51.xml
Normal file
|
|
@ -0,0 +1,247 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G51">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="(EXEC_INSTR_COUNT)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="(((EXEC_INSTR_COUNT)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="29" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / (EXEC_INSTR_COUNT)) * 100" />
|
||||
<event name="MaliEngInstr" title="Arithmetic instruction issue cycles" description="The number of instructions run per warp." units="instructions" counter="EXEC_INSTR_COUNT" offset="28" />
|
||||
<event name="MaliEngStarveCy" title="Execution engine starvation cycles" description="The number of cycles when no new threads are available to run." units="cycles" counter="EXEC_INSTR_STARVING" offset="30" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (4)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragPartWarp" title="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps" counter="FRAG_PARTIAL_WARPS" offset="10" />
|
||||
<event name="MaliFragPartWarpRate" title="Partial coverage percentage" description="The percentage of warps that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_WARPS) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="(FRAG_WARPS)" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (4)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (4))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (4)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (4))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / ((TEX_MSGI_NUM_QUADS) * 4)" />
|
||||
<event name="MaliTexCacheCompressFetch" title="Compressed texture line fetch requests" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" offset="41" />
|
||||
<event name="MaliTexCacheCompressFetchRate" title="Texture data fetches from compressed lines" description="The percentage of texture line fetches that are from block compressed textures." units="percent" equation="((TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED) / (TEX_TFCH_NUM_LINES_FETCHED)) * 100" />
|
||||
<event name="MaliTexCacheFetch" title="Texture line fetch requests" description="The number of texture line fetches from the L2 cache." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED" offset="40" />
|
||||
<event name="MaliTexCacheLookup" title="Texture cache lookup requests" description="The number of texture cache lookup cycles." units="requests" counter="TEX_TFCH_NUM_OPERATIONS" offset="42" />
|
||||
<event name="MaliTexCacheUtil" title="Texture unit cache utilization" description="The percentage utilization of the texturing unit cache lookup path." units="percent" equation="((TEX_TFCH_NUM_OPERATIONS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="43" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexMipInstrRate" title="Texture accesses using mipmapping percentage" description="The percentage of texture operations accessing mipmapped textures." units="percent" equation="((TEX_DFCH_NUM_PASSES_MIP_MAP) / (TEX_DFCH_NUM_PASSES)) * 100" />
|
||||
<event name="MaliTexQuadPass" title="Texture quad issues" description="The number of quad-width filtering passes." units="issues" counter="TEX_DFCH_NUM_PASSES" offset="36" />
|
||||
<event name="MaliTexQuadPassDescMiss" title="Texture quad descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests" counter="TEX_DFCH_NUM_PASSES_MISS" offset="37" />
|
||||
<event name="MaliTexQuadPassMip" title="Mipmapped texture quad issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" offset="38" />
|
||||
<event name="MaliTexQuadPassTri" title="Trilinear filtered texture quad issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" offset="39" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" counter="TEX_MSGI_NUM_QUADS" offset="35" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(TEX_MSGI_NUM_QUADS) * 4" />
|
||||
<event name="MaliTexTriInstrRate" title="Texture accesses using trilinear filter percentage" description="The percentage of texture operations using trilinear filtering." units="percent" equation="((TEX_TIDX_NUM_SPLIT_MIP_MAP) / (TEX_MSGI_NUM_QUADS)) * 100" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
<event name="MaliTilerWrBt" title="Internal write beats" description="The number of internal bus data write cycles made by the tiler." units="beats" counter="BUS_WRITE" offset="19" />
|
||||
</category>
|
||||
</metrics>
|
||||
251
src/panfrost/perf/generated/G52.xml
Normal file
251
src/panfrost/perf/generated/G52.xml
Normal file
|
|
@ -0,0 +1,251 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G52">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="(EXEC_INSTR_COUNT)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="(((EXEC_INSTR_COUNT)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="29" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / (EXEC_INSTR_COUNT)) * 100" />
|
||||
<event name="MaliEngInstr" title="Arithmetic instruction issue cycles" description="The number of instructions run per warp." units="instructions" counter="EXEC_INSTR_COUNT" offset="28" />
|
||||
<event name="MaliEngStarveCy" title="Execution engine starvation cycles" description="The number of cycles when no new threads are available to run." units="cycles" counter="EXEC_INSTR_STARVING" offset="30" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (8)) / 4)" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (8)) / 4)) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (8)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragPartWarp" title="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps" counter="FRAG_PARTIAL_WARPS" offset="10" />
|
||||
<event name="MaliFragPartWarpRate" title="Partial coverage percentage" description="The percentage of warps that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_WARPS) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (8)) / 4" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (8)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (8))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (8)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (8))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="63" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="61" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / ((TEX_MSGI_NUM_QUADS) * 4)" />
|
||||
<event name="MaliTexCacheCompressFetch" title="Compressed texture line fetch requests" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" offset="41" />
|
||||
<event name="MaliTexCacheCompressFetchRate" title="Texture data fetches from compressed lines" description="The percentage of texture line fetches that are from block compressed textures." units="percent" equation="((TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED) / (TEX_TFCH_NUM_LINES_FETCHED)) * 100" />
|
||||
<event name="MaliTexCacheFetch" title="Texture line fetch requests" description="The number of texture line fetches from the L2 cache." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED" offset="40" />
|
||||
<event name="MaliTexCacheLookup" title="Texture cache lookup requests" description="The number of texture cache lookup cycles." units="requests" counter="TEX_TFCH_NUM_OPERATIONS" offset="42" />
|
||||
<event name="MaliTexCacheUtil" title="Texture unit cache utilization" description="The percentage utilization of the texturing unit cache lookup path." units="percent" equation="((TEX_TFCH_NUM_OPERATIONS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="43" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexMipInstrRate" title="Texture accesses using mipmapping percentage" description="The percentage of texture operations accessing mipmapped textures." units="percent" equation="((TEX_DFCH_NUM_PASSES_MIP_MAP) / (TEX_DFCH_NUM_PASSES)) * 100" />
|
||||
<event name="MaliTexQuadPass" title="Texture quad issues" description="The number of quad-width filtering passes." units="issues" counter="TEX_DFCH_NUM_PASSES" offset="36" />
|
||||
<event name="MaliTexQuadPassDescMiss" title="Texture quad descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests" counter="TEX_DFCH_NUM_PASSES_MISS" offset="37" />
|
||||
<event name="MaliTexQuadPassMip" title="Mipmapped texture quad issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" offset="38" />
|
||||
<event name="MaliTexQuadPassTri" title="Trilinear filtered texture quad issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" offset="39" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" counter="TEX_MSGI_NUM_QUADS" offset="35" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(TEX_MSGI_NUM_QUADS) * 4" />
|
||||
<event name="MaliTexTriInstrRate" title="Texture accesses using trilinear filter percentage" description="The percentage of texture operations using trilinear filtering." units="percent" equation="((TEX_TIDX_NUM_SPLIT_MIP_MAP) / (TEX_MSGI_NUM_QUADS)) * 100" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
<event name="MaliTilerWrBt" title="Internal write beats" description="The number of internal bus data write cycles made by the tiler." units="beats" counter="BUS_WRITE" offset="19" />
|
||||
</category>
|
||||
</metrics>
|
||||
247
src/panfrost/perf/generated/G71.xml
Normal file
247
src/panfrost/perf/generated/G71.xml
Normal file
|
|
@ -0,0 +1,247 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G71">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="(EXEC_INSTR_COUNT)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="(((EXEC_INSTR_COUNT)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="29" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / (EXEC_INSTR_COUNT)) * 100" />
|
||||
<event name="MaliEngInstr" title="Arithmetic instruction issue cycles" description="The number of instructions run per warp." units="instructions" counter="EXEC_INSTR_COUNT" offset="28" />
|
||||
<event name="MaliEngStarveCy" title="Execution engine starvation cycles" description="The number of cycles when no new threads are available to run." units="cycles" counter="EXEC_INSTR_STARVING" offset="30" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (4)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragPartWarp" title="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps" counter="FRAG_PARTIAL_WARPS" offset="10" />
|
||||
<event name="MaliFragPartWarpRate" title="Partial coverage percentage" description="The percentage of warps that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_WARPS) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="(FRAG_WARPS)" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (4)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (4))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (4)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (4))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" counter="BEATS_WR_LSC" offset="61" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_WR_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="((BEATS_WR_LSC) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusOtherWrBt" title="Miscellaneous write beats to L2 memory system" description="The number of write beats sent by any unit that is not specifically identified." units="beats" counter="BEATS_WR_OTHER" offset="63" />
|
||||
<event name="MaliSCBusOtherWrBy" title="Other unit write bytes to L2 memory system" description="The number of write bytes sent by any unit that is not specifically identified." units="bytes" equation="(BEATS_WR_OTHER) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_COORD_ISSUE)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_COORD_ISSUE)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTex3DInstr" title="3D texture instructions" description="The number of texture operations acting on a 3D texture." units="requests" counter="TEX_INSTR_3D" offset="38" />
|
||||
<event name="MaliTex3DInstrRate" title="Texture samples using 3D texture percentage" description="The percentage of texture operations accessing 3D textures." units="percent" equation="((TEX_INSTR_3D) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_COORD_ISSUE)) / ((TEX_INSTR))" />
|
||||
<event name="MaliTexCompressInstr" title="Compressed texture instructions" description="The number of texture operations acting on a compressed texture." units="requests" counter="TEX_INSTR_COMPRESSED" offset="37" />
|
||||
<event name="MaliTexCompressInstrRate" title="Texture samples using compressed texture percentage" description="The percentage of texture operations accessing compressed textures." units="percent" equation="((TEX_INSTR_COMPRESSED) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexCoordStallCy" title="Texture filtering coordinate stall cycles" description="The number of cycles when threads are stalled at the texel coordinate calculation stage." units="cycles" counter="TEX_COORD_STALL" offset="41" />
|
||||
<event name="MaliTexDataStallCy" title="Texture line fill stall cycles" description="The number of cycles when at least one thread is waiting for data from the texture cache, but no lookup is completed." units="cycles" counter="TEX_STARVE_CACHE" offset="42" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_COORD_ISSUE" offset="40" />
|
||||
<event name="MaliTexInstr" title="Texture instructions" description="The number of thread-width texture operations processed." units="requests" counter="TEX_INSTR" offset="35" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_COORD_ISSUE)" />
|
||||
<event name="MaliTexMipInstr" title="Mipmapped texture instructions" description="The number of texture operations that act on a mipmapped texture." units="requests" counter="TEX_INSTR_MIPMAP" offset="36" />
|
||||
<event name="MaliTexMipInstrRate" title="Texture accesses using mipmapping percentage" description="The percentage of texture operations accessing mipmapped textures." units="percent" equation="((TEX_INSTR_MIPMAP) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexPartDataStallCy" title="Texture filtering partial data stall cycles" description="The number of cycles when at least one thread fetched some data from the texture cache, but no filtering operation is started." units="cycles" counter="TEX_STARVE_FILTER" offset="43" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(TEX_INSTR)" />
|
||||
<event name="MaliTexTriInstr" title="Trilinear filtered texture instructions" description="The number of texture operations using a trilinear texture filter." units="requests" counter="TEX_INSTR_TRILINEAR" offset="39" />
|
||||
<event name="MaliTexTriInstrRate" title="Texture accesses using trilinear filter percentage" description="The percentage of texture operations using trilinear filtering." units="percent" equation="((TEX_INSTR_TRILINEAR) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_COORD_ISSUE)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
<event name="MaliTilerWrBt" title="Internal write beats" description="The number of internal bus data write cycles made by the tiler." units="beats" counter="BUS_WRITE" offset="19" />
|
||||
</category>
|
||||
</metrics>
|
||||
272
src/panfrost/perf/generated/G710.xml
Normal file
272
src/panfrost/perf/generated/G710.xml
Normal file
|
|
@ -0,0 +1,272 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G710">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliCS0WaitStallCy" title="Command stream 0 wait stall cycles" description="The number of cycles that command stream interface 0 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF0_WAIT_BLOCKED" offset="51" />
|
||||
<event name="MaliCS1WaitStallCy" title="Command stream 1 wait stall cycles" description="The number of cycles that command stream interface 1 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF1_WAIT_BLOCKED" offset="55" />
|
||||
<event name="MaliCS2WaitStallCy" title="Command stream 2 wait stall cycles" description="The number of cycles that command stream interface 2 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF2_WAIT_BLOCKED" offset="59" />
|
||||
<event name="MaliCS3WaitStallCy" title="Command stream 3 wait stall cycles" description="The number of cycles that command stream interface 3 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF3_WAIT_BLOCKED" offset="63" />
|
||||
<event name="MaliCSFCEUActiveCy" title="Command execution unit active cycles" description="The number of cycles that the CEU is processing commands." units="cycles" counter="CEU_ACTIVE" offset="40" />
|
||||
<event name="MaliCSFCEUUtil" title="Command execution unit utilization" description="The CSF command execution unit utilization compared against the GPU active cycles." units="percent" equation="((CEU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFCS0ActiveCy" title="Command stream 0 active cycles" description="The number of cycles that command stream interface 0 contained an enabled command stream." units="cycles" counter="CSHWIF0_ENABLED" offset="48" />
|
||||
<event name="MaliCSFCS1ActiveCy" title="Command stream 1 active cycles" description="The number of cycles that command stream interface 1 contained an enabled command stream." units="cycles" counter="CSHWIF1_ENABLED" offset="52" />
|
||||
<event name="MaliCSFCS2ActiveCy" title="Command stream 2 active cycles" description="The number of cycles that command stream interface 2 contained an enabled command stream." units="cycles" counter="CSHWIF2_ENABLED" offset="56" />
|
||||
<event name="MaliCSFCS3ActiveCy" title="Command stream 3 active cycles" description="The number of cycles that command stream interface 3 contained an enabled command stream." units="cycles" counter="CSHWIF3_ENABLED" offset="60" />
|
||||
<event name="MaliCSFLSUActiveCy" title="Command load/store unit active cycles" description="The number of cycles that the load-store unit is processing commands." units="cycles" counter="LSU_ACTIVE" offset="45" />
|
||||
<event name="MaliCSFLSUUtil" title="Command load/store unit utilization" description="The CSF load/store unit utilization compared against the GPU active cycles." units="percent" equation="((LSU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFMCUActiveCy" title="MCU active cycles" description="The number of cycles when the CSF front-end MCU is actively processing." units="cycles" counter="MCU_ACTIVE" offset="5" />
|
||||
<event name="MaliCSFMCUUtil" title="Microcontroller utilization" description="The CSF MCU utilization compared against the GPU active cycles." units="percent" equation="((MCU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueueActiveCy" title="Compute queue active cycles" description="The number of cycles that the compute queue is processing work." units="cycles" equation="(ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)" />
|
||||
<event name="MaliCompQueueAssignStallCy" title="Compute queue endpoint stall cycles" description="The number of cycles the compute queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_COMP_READY_BLOCKED" offset="30" />
|
||||
<event name="MaliCompQueueDrainStallCy" title="Compute queue endpoint drain stall cycles" description="The number of cycles the compute queue is waiting for endpoints to drain." units="cycles" counter="ITER_COMP_EP_DRAIN" offset="31" />
|
||||
<event name="MaliCompQueueIRQActiveCy" title="Compute queue interrupt pending cycles" description="The number of cycles that the compute queue IRQ was pending." units="cycles" counter="ITER_COMP_IRQ_ACTIVE" offset="28" />
|
||||
<event name="MaliCompQueueJob" title="Compute jobs" description="The number of compute jobs processed." units="jobs" counter="ITER_COMP_JOB_COMPLETED" offset="25" />
|
||||
<event name="MaliCompQueueTask" title="Compute tasks" description="The number of compute tasks processed." units="tasks" counter="ITER_COMP_TASK_COMPLETED" offset="26" />
|
||||
<event name="MaliCompQueueUtil" title="Compute queue utilization" description="The compute queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueuedCy" title="Compute work queued cycles" description="The number of cycles that the compute queue has work queued." units="cycles" counter="ITER_COMP_ACTIVE" offset="24" />
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles that the fragment queue is processing work." units="cycles" equation="(ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)" />
|
||||
<event name="MaliFragQueueAssignStallCy" title="Fragment queue endpoint stall cycles" description="The number of cycles the fragment queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_FRAG_READY_BLOCKED" offset="38" />
|
||||
<event name="MaliFragQueueIRQActiveCy" title="Fragment queue interrupt pending cycles" description="The number of cycles that the fragment queue IRQ was pending." units="cycles" counter="ITER_FRAG_IRQ_ACTIVE" offset="36" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of fragment jobs processed." units="jobs" counter="ITER_FRAG_JOB_COMPLETED" offset="33" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="ITER_FRAG_TASK_COMPLETED" offset="34" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueuedCy" title="Fragment work queued cycles" description="The number of cycles that the fragment queue has work queued." units="cycles" counter="ITER_FRAG_ACTIVE" offset="32" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="4" />
|
||||
<event name="MaliGPUAnyQueueActiveCy" title="Any queue active cycles" description="The number of cycles when any GPU queue is active." units="cycles" counter="GPU_ITER_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQ" title="GPU interrupts" description="The number of interrupts raised by the GPU to the CPU." units="interrupts" counter="GPU_IRQ_COUNT" offset="11" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="10" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerQueueDrainStallCy" title="Vertex queue endpoint drain stall cycles" description="The number of cycles the vertex queue is waiting for endpoints to drain." units="cycles" counter="ITER_TILER_EP_DRAIN" offset="23" />
|
||||
<event name="MaliVertQueueActiveCy" title="Vertex queue active cycles" description="The number of cycles that the vertex queue is processing work." units="cycles" equation="(ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)" />
|
||||
<event name="MaliVertQueueAssignStallCy" title="Vertex queue endpoint stall cycles" description="The number of cycles the vertex queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_TILER_READY_BLOCKED" offset="22" />
|
||||
<event name="MaliVertQueueIRQActiveCy" title="Vertex queue interrupt pending cycles" description="The number of cycles that the vertex queue IRQ was pending." units="cycles" counter="ITER_TILER_IRQ_ACTIVE" offset="20" />
|
||||
<event name="MaliVertQueueJob" title="Vertex jobs" description="The number of vertex jobs processed." units="jobs" counter="ITER_TILER_JOB_COMPLETED" offset="17" />
|
||||
<event name="MaliVertQueueTask" title="Vertex tasks" description="The number of vertex tasks processed." units="tasks" counter="ITER_TILER_IDVS_TASK_COMPLETED" offset="18" />
|
||||
<event name="MaliVertQueueUtil" title="Vertex queue utilization" description="The vertex queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliVertQueuedCy" title="Vertex work queued cycles" description="The number of cycles that the vertex shading queue has work queued." units="cycles" counter="ITER_TILER_ACTIVE" offset="16" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheCleanUnique" title="Input internal clean unique requests" description="The number of L2 cache line clean unique requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_CU" offset="13" />
|
||||
<event name="MaliL2CacheEvict" title="Input internal evict requests" description="The number of L2 cache line evict requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_EVICT" offset="12" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="13" />
|
||||
<event name="MaliL2CacheFlushCy" title="L2 cache flush cycles" description="The number of cycles spent flushing GPU L2 caches." units="cycles" counter="CACHE_FLUSH_CYCLES" offset="12" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="max((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU), (EXEC_INSTR_SFU) * 4)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="((max((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU), (EXEC_INSTR_SFU) * 4)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAnyActiveCy" title="Any workload active cycles" description="The number of cycles when the shader core is processing either a non-fragment workload or a fragment workload." units="cycles" counter="SHADER_CORE_ACTIVE" offset="53" />
|
||||
<event name="MaliAnyUtil" title="Shader core clock ratio" description="An estimate of shader core use relative to the GPU top-level clock." units="percent" equation="((SHADER_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngArithInstr" title="Arithmetic instruction issue cycles" description="The total number of instructions issued to the FMA, CVT, and SFU pipes." units="instructions" equation="(EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)" />
|
||||
<event name="MaliEngCVTInstr" title="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions" counter="EXEC_INSTR_CVT" offset="28" />
|
||||
<event name="MaliEngCVTPipeUtil" title="CVT pipe utilization" description="Defines the utilization of the CVT pipe." units="percent" equation="((EXEC_INSTR_CVT) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="31" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngFMAInstr" title="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions" counter="EXEC_INSTR_FMA" offset="27" />
|
||||
<event name="MaliEngFMAPipeUtil" title="FMA pipe utilization" description="The utilization of the FMA pipe." units="percent" equation="((EXEC_INSTR_FMA) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngICacheMiss" title="Instruction cache misses" description="The number of instruction cache misses." units="requests" counter="EXEC_ICACHE_MISS" offset="32" />
|
||||
<event name="MaliEngSFUInstr" title="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions" counter="EXEC_INSTR_SFU" offset="29" />
|
||||
<event name="MaliEngSFUPipeUtil" title="SFU pipe utilization" description="The utilization of the SFU pipe." units="percent" equation="(((EXEC_INSTR_SFU) * 4) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSWBlendInstr" title="Blend shader instructions" description="The number of blend shader invocations run." units="instructions" counter="CALL_BLEND_SHADER" offset="34" />
|
||||
<event name="MaliEngSWBlendRate" title="Shader blend percentage" description="The percentage of fragments that use shader-based blending." units="percent" equation="(((CALL_BLEND_SHADER) * 4) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliEngStarveCy" title="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles" counter="EXEC_STARVE_ARITH" offset="33" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (16)) / ((ITER_FRAG_TASK_COMPLETED) * (32) * (32))" />
|
||||
<event name="MaliFragRastPartQd" title="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads" counter="FRAG_PARTIAL_QUADS_RAST" offset="10" />
|
||||
<event name="MaliFragRastPartQdRate" title="Partial coverage percentage" description="The percentage of rasterized fine quads that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_QUADS_RAST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES_OUT" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (16)) / 4" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (16)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (16))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (4 * (FRAG_PTILES))) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (16)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (16))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((ITER_FRAG_TASK_COMPLETED) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / (((TEX_MSGO_NUM_MSG) * 2) * 4)" />
|
||||
<event name="MaliTexDataFetchStallCy" title="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles" counter="TEX_TFCH_CLK_STALLED" offset="37" />
|
||||
<event name="MaliTexDescStallCy" title="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles" counter="TEX_DFCH_CLK_STALLED" offset="36" />
|
||||
<event name="MaliTexFiltFullRate" title="Texture full speed filtering percentage" description="The percentage of texture filtering cycles using the full width of the texture filtering data path." units="percent" equation="(((TEX_FILT_NUM_FXR_OPERATIONS) + (TEX_FILT_NUM_FST_OPERATIONS)) / (TEX_FILT_NUM_OPERATIONS)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="39" />
|
||||
<event name="MaliTexFiltStallCy" title="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" offset="38" />
|
||||
<event name="MaliTexFullBiFiltCy" title="Texture filtering cycles using full bilinear" description="The number of cycles when the filtering unit is filled with bilinear filtering." units="cycles" counter="TEX_FILT_NUM_FXR_OPERATIONS" offset="40" />
|
||||
<event name="MaliTexFullTriFiltCy" title="Texture filtering cycles using full trilinear" description="The number of cycles when the filtering unit is filled with trilinear filtering." units="cycles" counter="TEX_FILT_NUM_FST_OPERATIONS" offset="41" />
|
||||
<event name="MaliTexInBt" title="Texture message read beats" description="The number of texture request message data beats." units="beats" counter="TEX_MSGI_NUM_FLITS" offset="35" />
|
||||
<event name="MaliTexInBusUtil" title="Texture input bus utilization" description="The percentage load on the texture message input bus." units="percent" equation="((TEX_MSGI_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexOutBt" title="Texture message write beats" description="The number of texture response message data beats." units="beats" counter="TEX_MSGO_NUM_FLITS" offset="43" />
|
||||
<event name="MaliTexOutBusUtil" title="Texture output bus utilization" description="The percentage load on the texture message output bus." units="percent" equation="((TEX_MSGO_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexOutMsg" title="Texture messages" description="The number of output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_MSG" offset="42" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" equation="(TEX_MSGO_NUM_MSG) * 2" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="((TEX_MSGO_NUM_MSG) * 2) * 4" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (2)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (2)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (2)) + ((VARY_SLOT_16) / (2))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (2)) + ((VARY_SLOT_16) / (2))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
</category>
|
||||
</metrics>
|
||||
294
src/panfrost/perf/generated/G715.xml
Normal file
294
src/panfrost/perf/generated/G715.xml
Normal file
|
|
@ -0,0 +1,294 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G715">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliCS0WaitStallCy" title="Command stream 0 wait stall cycles" description="The number of cycles that command stream interface 0 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF0_WAIT_BLOCKED" offset="51" />
|
||||
<event name="MaliCS1WaitStallCy" title="Command stream 1 wait stall cycles" description="The number of cycles that command stream interface 1 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF1_WAIT_BLOCKED" offset="55" />
|
||||
<event name="MaliCS2WaitStallCy" title="Command stream 2 wait stall cycles" description="The number of cycles that command stream interface 2 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF2_WAIT_BLOCKED" offset="59" />
|
||||
<event name="MaliCS3WaitStallCy" title="Command stream 3 wait stall cycles" description="The number of cycles that command stream interface 3 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF3_WAIT_BLOCKED" offset="63" />
|
||||
<event name="MaliCSFCEUActiveCy" title="Command execution unit active cycles" description="The number of cycles that the CEU is processing commands." units="cycles" counter="CEU_ACTIVE" offset="40" />
|
||||
<event name="MaliCSFCEUUtil" title="Command execution unit utilization" description="The CSF command execution unit utilization compared against the GPU active cycles." units="percent" equation="((CEU_ACTIVE) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliCSFCS0ActiveCy" title="Command stream 0 active cycles" description="The number of cycles that command stream interface 0 contained an enabled command stream." units="cycles" counter="CSHWIF0_ENABLED" offset="48" />
|
||||
<event name="MaliCSFCS1ActiveCy" title="Command stream 1 active cycles" description="The number of cycles that command stream interface 1 contained an enabled command stream." units="cycles" counter="CSHWIF1_ENABLED" offset="52" />
|
||||
<event name="MaliCSFCS2ActiveCy" title="Command stream 2 active cycles" description="The number of cycles that command stream interface 2 contained an enabled command stream." units="cycles" counter="CSHWIF2_ENABLED" offset="56" />
|
||||
<event name="MaliCSFCS3ActiveCy" title="Command stream 3 active cycles" description="The number of cycles that command stream interface 3 contained an enabled command stream." units="cycles" counter="CSHWIF3_ENABLED" offset="60" />
|
||||
<event name="MaliCSFLSUActiveCy" title="Command load/store unit active cycles" description="The number of cycles that the load-store unit is processing commands." units="cycles" counter="LSU_ACTIVE" offset="45" />
|
||||
<event name="MaliCSFLSUUtil" title="Command load/store unit utilization" description="The CSF load/store unit utilization compared against the GPU active cycles." units="percent" equation="((LSU_ACTIVE) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliCSFMCUActiveCy" title="MCU active cycles" description="The number of cycles when the CSF front-end MCU is actively processing." units="cycles" counter="MCU_ACTIVE" offset="5" />
|
||||
<event name="MaliCSFMCUUtil" title="Microcontroller utilization" description="The CSF MCU utilization compared against the GPU active cycles." units="percent" equation="((MCU_ACTIVE) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliCompQueueActiveCy" title="Compute queue active cycles" description="The number of cycles that the compute queue is processing work." units="cycles" equation="(ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)" />
|
||||
<event name="MaliCompQueueAssignStallCy" title="Compute queue endpoint stall cycles" description="The number of cycles the compute queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_COMP_READY_BLOCKED" offset="30" />
|
||||
<event name="MaliCompQueueDrainStallCy" title="Compute queue endpoint drain stall cycles" description="The number of cycles the compute queue is waiting for endpoints to drain." units="cycles" counter="ITER_COMP_EP_DRAIN" offset="31" />
|
||||
<event name="MaliCompQueueIRQActiveCy" title="Compute queue interrupt pending cycles" description="The number of cycles that the compute queue IRQ was pending." units="cycles" counter="ITER_COMP_IRQ_ACTIVE" offset="28" />
|
||||
<event name="MaliCompQueueJob" title="Compute jobs" description="The number of compute jobs processed." units="jobs" counter="ITER_COMP_JOB_COMPLETED" offset="25" />
|
||||
<event name="MaliCompQueueTask" title="Compute tasks" description="The number of compute tasks processed." units="tasks" counter="ITER_COMP_TASK_COMPLETED" offset="26" />
|
||||
<event name="MaliCompQueueUtil" title="Compute queue utilization" description="The compute queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliCompQueuedCy" title="Compute work queued cycles" description="The number of cycles that the compute queue has work queued." units="cycles" counter="ITER_COMP_ACTIVE" offset="24" />
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles that the fragment queue is processing work." units="cycles" equation="(ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)" />
|
||||
<event name="MaliFragQueueAssignStallCy" title="Fragment queue endpoint stall cycles" description="The number of cycles the fragment queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_FRAG_READY_BLOCKED" offset="38" />
|
||||
<event name="MaliFragQueueIRQActiveCy" title="Fragment queue interrupt pending cycles" description="The number of cycles that the fragment queue IRQ was pending." units="cycles" counter="ITER_FRAG_IRQ_ACTIVE" offset="36" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of fragment jobs processed." units="jobs" counter="ITER_FRAG_JOB_COMPLETED" offset="33" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="ITER_FRAG_TASK_COMPLETED" offset="34" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliFragQueuedCy" title="Fragment work queued cycles" description="The number of cycles that the fragment queue has work queued." units="cycles" counter="ITER_FRAG_ACTIVE" offset="32" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" equation="(GPU_ITER_ACTIVE)" />
|
||||
<event name="MaliGPUActiveRawCy" title="GPU active raw cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="4" />
|
||||
<event name="MaliGPUAnyQueueActiveCy" title="Any queue active cycles" description="The number of cycles when any GPU queue is active." units="cycles" counter="GPU_ITER_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQ" title="GPU interrupts" description="The number of interrupts raised by the GPU to the CPU." units="interrupts" counter="GPU_IRQ_COUNT" offset="11" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="10" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliTilerQueueDrainStallCy" title="Vertex queue endpoint drain stall cycles" description="The number of cycles the vertex queue is waiting for endpoints to drain." units="cycles" counter="ITER_TILER_EP_DRAIN" offset="23" />
|
||||
<event name="MaliVertQueueActiveCy" title="Vertex queue active cycles" description="The number of cycles that the vertex queue is processing work." units="cycles" equation="(ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)" />
|
||||
<event name="MaliVertQueueAssignStallCy" title="Vertex queue endpoint stall cycles" description="The number of cycles the vertex queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_TILER_READY_BLOCKED" offset="22" />
|
||||
<event name="MaliVertQueueIRQActiveCy" title="Vertex queue interrupt pending cycles" description="The number of cycles that the vertex queue IRQ was pending." units="cycles" counter="ITER_TILER_IRQ_ACTIVE" offset="20" />
|
||||
<event name="MaliVertQueueJob" title="Vertex jobs" description="The number of vertex jobs processed." units="jobs" counter="ITER_TILER_JOB_COMPLETED" offset="17" />
|
||||
<event name="MaliVertQueueTask" title="Vertex tasks" description="The number of vertex tasks processed." units="tasks" counter="ITER_TILER_IDVS_TASK_COMPLETED" offset="18" />
|
||||
<event name="MaliVertQueueUtil" title="Vertex queue utilization" description="The vertex queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliVertQueuedCy" title="Vertex work queued cycles" description="The number of cycles that the vertex shading queue has work queued." units="cycles" counter="ITER_TILER_ACTIVE" offset="16" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliL2CacheCleanUnique" title="Input internal clean unique requests" description="The number of L2 cache line clean unique requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_CU" offset="13" />
|
||||
<event name="MaliL2CacheEvict" title="Input internal evict requests" description="The number of L2 cache line evict requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_EVICT" offset="12" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="13" />
|
||||
<event name="MaliL2CacheFlushCy" title="L2 cache flush cycles" description="The number of cycles spent flushing GPU L2 caches." units="cycles" counter="CACHE_FLUSH_CYCLES" offset="12" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="max((EXEC_INSTR_CVT) + (EXEC_INSTR_SFU) + (((EXEC_INSTR_FMA) - min((EXEC_INSTR_FMA), (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) / 2), (EXEC_INSTR_SFU) * 4)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="((max((EXEC_INSTR_CVT) + (EXEC_INSTR_SFU) + (((EXEC_INSTR_FMA) - min((EXEC_INSTR_FMA), (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) / 2), (EXEC_INSTR_SFU) * 4)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAnyActiveCy" title="Any workload active cycles" description="The number of cycles when the shader core is processing either a non-fragment workload or a fragment workload." units="cycles" counter="SHADER_CORE_ACTIVE" offset="53" />
|
||||
<event name="MaliAnyUtil" title="Shader core clock ratio" description="An estimate of shader core use relative to the GPU top-level clock." units="percent" equation="((SHADER_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFragWarpOcc" title="Fragment warp occupancy" description="The thread occupancy of the fragment warps." units="percent" equation="((FRAG_SHADER_THREADS) / ((FRAG_WARPS) * (16))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngArithInstr" title="Arithmetic instruction issue cycles" description="The total number of instructions issued to the FMA, CVT, and SFU pipes." units="instructions" equation="(EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)" />
|
||||
<event name="MaliEngCVTInstr" title="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions" counter="EXEC_INSTR_CVT" offset="28" />
|
||||
<event name="MaliEngCVTPipeUtil" title="CVT pipe utilization" description="Defines the utilization of the CVT pipe." units="percent" equation="((EXEC_INSTR_CVT) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="31" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngFMAInstr" title="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions" counter="EXEC_INSTR_FMA" offset="27" />
|
||||
<event name="MaliEngFMAPipeUtil" title="FMA pipe utilization" description="The utilization of the FMA pipes." units="percent" equation="((EXEC_INSTR_FMA) / (2 * (EXEC_CORE_ACTIVE))) * 100" />
|
||||
<event name="MaliEngICacheMiss" title="Instruction cache misses" description="The number of instruction cache misses." units="requests" counter="EXEC_ICACHE_MISS" offset="32" />
|
||||
<event name="MaliEngNarrowInstr" title="Narrow arithmetic instructions" description="The number of narrow arithmetic instructions." units="instructions" counter="EXEC_INSTR_NARROW" offset="5" />
|
||||
<event name="MaliEngNarrowInstrRate" title="Narrow arithmetic percentage" description="The percentage of arithmetic instructions that operate on 8/16-bit types." units="percent" equation="((EXEC_INSTR_NARROW) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngSFUInstr" title="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions" counter="EXEC_INSTR_SFU" offset="29" />
|
||||
<event name="MaliEngSFUPipeUtil" title="SFU pipe utilization" description="The utilization of the SFU pipe." units="percent" equation="(((EXEC_INSTR_SFU) * 4) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSWBlendInstr" title="Blend shader instructions" description="The number of blend shader invocations run." units="instructions" counter="CALL_BLEND_SHADER" offset="34" />
|
||||
<event name="MaliEngSWBlendRate" title="Shader blend percentage" description="The percentage of fragments that use shader-based blending." units="percent" equation="(((CALL_BLEND_SHADER) * 4) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliEngStarveCy" title="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles" counter="EXEC_STARVE_ARITH" offset="33" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="(FRAG_SHADER_THREADS) / ((ITER_FRAG_TASK_COMPLETED) * (32) * (32))" />
|
||||
<event name="MaliFragRastCoarseQd" title="Rasterized coarse quads" description="The number of coarse quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_COARSE" offset="68" />
|
||||
<event name="MaliFragRastPartQd" title="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads" counter="FRAG_PARTIAL_QUADS_RAST" offset="10" />
|
||||
<event name="MaliFragRastPartQdRate" title="Partial coverage percentage" description="The percentage of rasterized fine quads that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_QUADS_RAST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragShadRate" title="Fragment shading rate" description="The percentage of coarse quads generated relative to fine quads rasterized." units="percent" equation="((FRAG_QUADS_COARSE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (16)) / 4" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" counter="FRAG_SHADER_THREADS" offset="69" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / (FRAG_SHADER_THREADS)" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (4 * (FRAG_PTILES))) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (16)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (16))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliRTUBox" title="Ray tracing box tests" description="The number of acceleration structure bounding boxes tested." units="boxes" counter="RT_RAY_BOX" offset="71" />
|
||||
<event name="MaliRTUBoxBin1" title="Ray tracing box nodes with 1-4 rays" description="The number of acceleration structure box nodes with 1 to 4 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_1_4" offset="76" />
|
||||
<event name="MaliRTUBoxBin13" title="Ray tracing box nodes with 13-16 rays" description="The number of acceleration structure box nodes with 13 to 16 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_13_16" offset="79" />
|
||||
<event name="MaliRTUBoxBin5" title="Ray tracing box nodes with 5-8 rays" description="The number of acceleration structure box nodes with 5 to 8 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_5_8" offset="77" />
|
||||
<event name="MaliRTUBoxBin9" title="Ray tracing box nodes with 9-12 rays" description="The number of acceleration structure box nodes with 9 to 12 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_9_12" offset="78" />
|
||||
<event name="MaliRTUBoxIssueCy" title="Ray tracing box tester issue cycles" description="The number of active issue cycles for the ray tracing box test unit." units="cycles" counter="RT_RAY_BOX_ISSUED" offset="85" />
|
||||
<event name="MaliRTUFirstHitTerm" title="Ray tracing first hit terminations" description="The number of rays that terminate on their first hit." units="rays" counter="RT_TERM_FIRST_HIT" offset="82" />
|
||||
<event name="MaliRTUIssueCy" title="Ray tracing unit issue cycles" description="The number of cycles the ray tracing unit was issuing work." units="cycles" equation="max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))" />
|
||||
<event name="MaliRTUMiss" title="Ray tracing triangle test misses" description="The number of triangle intersection tests that do not intersect." units="rays" counter="RT_MISS" offset="83" />
|
||||
<event name="MaliRTUNonOpaqueHit" title="Ray tracing non-opaque triangle hits" description="The number of non-opaque triangle hits." units="tests" counter="RT_NON_OPAQUE_HIT" offset="81" />
|
||||
<event name="MaliRTUOpaqueHit" title="Ray tracing opaque triangle hits" description="The number of opaque triangle hits." units="tests" counter="RT_OPAQUE_HIT" offset="80" />
|
||||
<event name="MaliRTURay" title="Ray tracing started rays" description="The number of rays started." units="rays" counter="RT_RAYS_STARTED" offset="84" />
|
||||
<event name="MaliRTUTri" title="Ray tracing triangle nodes tested" description="The number of triangle nodes tested." units="nodes" counter="RT_RAY_TRI" offset="70" />
|
||||
<event name="MaliRTUTriBin1" title="Ray tracing triangle nodes with 1-4 rays" description="The number of triangle nodes with 1 to 4 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_1_4" offset="72" />
|
||||
<event name="MaliRTUTriBin13" title="Ray tracing triangle nodes with 13-16 rays" description="The number of triangle nodes with 13 to 16 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_13_16" offset="75" />
|
||||
<event name="MaliRTUTriBin5" title="Ray tracing triangle nodes with 5-8 rays" description="The number of triangle nodes with 5 to 8 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_5_8" offset="73" />
|
||||
<event name="MaliRTUTriBin9" title="Ray tracing triangle nodes with 9-12 rays" description="The number of triangle nodes with 9 to 12 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_9_12" offset="74" />
|
||||
<event name="MaliRTUTriIssueCy" title="Ray tracing triangle tester issue cycles" description="The number of active issue cycles for the ray tracing triangle test unit." units="cycles" counter="RT_RAY_TRI_ISSUED" offset="86" />
|
||||
<event name="MaliRTUUtil" title="Ray tracing unit utilization" description="The percentage utilization of the ray tracing unit." units="percent" equation="((max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((ITER_FRAG_TASK_COMPLETED) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / (((TEX_MSGO_NUM_MSG) * 2) * 4)" />
|
||||
<event name="MaliTexDataFetchStallCy" title="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles" counter="TEX_TFCH_CLK_STALLED" offset="37" />
|
||||
<event name="MaliTexDescStallCy" title="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles" counter="TEX_DFCH_CLK_STALLED" offset="36" />
|
||||
<event name="MaliTexFiltFullRate" title="Texture full speed filtering percentage" description="The percentage of texture filtering cycles using the full width of the texture filtering data path." units="percent" equation="(((TEX_FILT_NUM_FXR_OPERATIONS) + (TEX_FILT_NUM_FST_OPERATIONS)) / (TEX_FILT_NUM_OPERATIONS)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="39" />
|
||||
<event name="MaliTexFiltStallCy" title="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" offset="38" />
|
||||
<event name="MaliTexFullBiFiltCy" title="Texture filtering cycles using full bilinear" description="The number of cycles when the filtering unit is filled with bilinear filtering." units="cycles" counter="TEX_FILT_NUM_FXR_OPERATIONS" offset="40" />
|
||||
<event name="MaliTexFullTriFiltCy" title="Texture filtering cycles using full trilinear" description="The number of cycles when the filtering unit is filled with trilinear filtering." units="cycles" counter="TEX_FILT_NUM_FST_OPERATIONS" offset="41" />
|
||||
<event name="MaliTexInBt" title="Texture message read beats" description="The number of texture request message data beats." units="beats" counter="TEX_MSGI_NUM_FLITS" offset="35" />
|
||||
<event name="MaliTexInBusUtil" title="Texture input bus utilization" description="The percentage load on the texture message input bus." units="percent" equation="((TEX_MSGI_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexOutBt" title="Texture message write beats" description="The number of texture response message data beats." units="beats" counter="TEX_MSGO_NUM_FLITS" offset="43" />
|
||||
<event name="MaliTexOutBusUtil" title="Texture output bus utilization" description="The percentage load on the texture message output bus." units="percent" equation="((TEX_MSGO_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexOutMsg" title="Texture messages" description="The number of output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_MSG" offset="42" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" equation="(TEX_MSGO_NUM_MSG) * 2" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="((TEX_MSGO_NUM_MSG) * 2) * 4" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (4)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (4)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceCullPrim" title="Facing test culled primitives" description="The number of primitives that are culled by facing tests." units="primitives" counter="PRIM_FACE_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceCullRate" title="Facing plane test cull percentage" description="The percentage of primitives culled by the facing test." units="percent" equation="((PRIM_FACE_CULLED) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPlaneCullPrim" title="Frustum test culled primitives" description="The number of primitives that are culled by frustum tests." units="primitives" counter="PRIM_FRUSTUM_CULLED" offset="13" />
|
||||
<event name="MaliGeomPlaneCullRate" title="Frustum test cull percentage" description="The percentage of primitives culled by the frustum test." units="percent" equation="((PRIM_FRUSTUM_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FACE_CULLED))) * 100" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FACE_CULLED) - (PRIM_FRUSTUM_CULLED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / ((GPU_ITER_ACTIVE))) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
</category>
|
||||
</metrics>
|
||||
247
src/panfrost/perf/generated/G72.xml
Normal file
247
src/panfrost/perf/generated/G72.xml
Normal file
|
|
@ -0,0 +1,247 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G72">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="(EXEC_INSTR_COUNT)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="(((EXEC_INSTR_COUNT)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="29" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / (EXEC_INSTR_COUNT)) * 100" />
|
||||
<event name="MaliEngInstr" title="Arithmetic instruction issue cycles" description="The number of instructions run per warp." units="instructions" counter="EXEC_INSTR_COUNT" offset="28" />
|
||||
<event name="MaliEngStarveCy" title="Execution engine starvation cycles" description="The number of cycles when no new threads are available to run." units="cycles" counter="EXEC_INSTR_STARVING" offset="30" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - ((FRAG_WARPS))) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (4)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragPartWarp" title="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps" counter="FRAG_PARTIAL_WARPS" offset="10" />
|
||||
<event name="MaliFragPartWarpRate" title="Partial coverage percentage" description="The percentage of warps that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_WARPS) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="(FRAG_WARPS)" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (4)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (4))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (4)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (4))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" counter="BEATS_WR_LSC" offset="61" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_WR_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="((BEATS_WR_LSC) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusOtherWrBt" title="Miscellaneous write beats to L2 memory system" description="The number of write beats sent by any unit that is not specifically identified." units="beats" counter="BEATS_WR_OTHER" offset="63" />
|
||||
<event name="MaliSCBusOtherWrBy" title="Other unit write bytes to L2 memory system" description="The number of write bytes sent by any unit that is not specifically identified." units="bytes" equation="(BEATS_WR_OTHER) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_COORD_ISSUE)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_COORD_ISSUE)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTex3DInstr" title="3D texture instructions" description="The number of texture operations acting on a 3D texture." units="requests" counter="TEX_INSTR_3D" offset="38" />
|
||||
<event name="MaliTex3DInstrRate" title="Texture samples using 3D texture percentage" description="The percentage of texture operations accessing 3D textures." units="percent" equation="((TEX_INSTR_3D) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_COORD_ISSUE)) / ((TEX_INSTR))" />
|
||||
<event name="MaliTexCompressInstr" title="Compressed texture instructions" description="The number of texture operations acting on a compressed texture." units="requests" counter="TEX_INSTR_COMPRESSED" offset="37" />
|
||||
<event name="MaliTexCompressInstrRate" title="Texture samples using compressed texture percentage" description="The percentage of texture operations accessing compressed textures." units="percent" equation="((TEX_INSTR_COMPRESSED) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexCoordStallCy" title="Texture filtering coordinate stall cycles" description="The number of cycles when threads are stalled at the texel coordinate calculation stage." units="cycles" counter="TEX_COORD_STALL" offset="41" />
|
||||
<event name="MaliTexDataStallCy" title="Texture line fill stall cycles" description="The number of cycles when at least one thread is waiting for data from the texture cache, but no lookup is completed." units="cycles" counter="TEX_STARVE_CACHE" offset="42" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_COORD_ISSUE" offset="40" />
|
||||
<event name="MaliTexInstr" title="Texture instructions" description="The number of thread-width texture operations processed." units="requests" counter="TEX_INSTR" offset="35" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_COORD_ISSUE)" />
|
||||
<event name="MaliTexMipInstr" title="Mipmapped texture instructions" description="The number of texture operations that act on a mipmapped texture." units="requests" counter="TEX_INSTR_MIPMAP" offset="36" />
|
||||
<event name="MaliTexMipInstrRate" title="Texture accesses using mipmapping percentage" description="The percentage of texture operations accessing mipmapped textures." units="percent" equation="((TEX_INSTR_MIPMAP) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexPartDataStallCy" title="Texture filtering partial data stall cycles" description="The number of cycles when at least one thread fetched some data from the texture cache, but no filtering operation is started." units="cycles" counter="TEX_STARVE_FILTER" offset="43" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(TEX_INSTR)" />
|
||||
<event name="MaliTexTriInstr" title="Trilinear filtered texture instructions" description="The number of texture operations using a trilinear texture filter." units="requests" counter="TEX_INSTR_TRILINEAR" offset="39" />
|
||||
<event name="MaliTexTriInstrRate" title="Texture accesses using trilinear filter percentage" description="The percentage of texture operations using trilinear filtering." units="percent" equation="((TEX_INSTR_TRILINEAR) / (TEX_INSTR)) * 100" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_COORD_ISSUE)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
<event name="MaliTilerWrBt" title="Internal write beats" description="The number of internal bus data write cycles made by the tiler." units="beats" counter="BUS_WRITE" offset="19" />
|
||||
</category>
|
||||
</metrics>
|
||||
303
src/panfrost/perf/generated/G720.xml
Normal file
303
src/panfrost/perf/generated/G720.xml
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G720">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliBinningQueueActiveCy" title="Binning phase queue active cycles" description="The number of cycles that the binning phase queue is processing work. The binning phase includes position shading, culling, and binning." units="cycles" equation="(ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)" />
|
||||
<event name="MaliBinningQueueAssignStallCy" title="Binning phase queue endpoint stall cycles" description="The number of cycles the binning phase queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_TILER_READY_BLOCKED" offset="22" />
|
||||
<event name="MaliBinningQueueIRQActiveCy" title="Binning phase queue interrupt pending cycles" description="The number of cycles that the binning phase queue IRQ was pending." units="cycles" counter="ITER_TILER_IRQ_ACTIVE" offset="20" />
|
||||
<event name="MaliBinningQueueJob" title="Binning phase jobs" description="The number of binning phase jobs processed." units="jobs" counter="ITER_TILER_JOB_COMPLETED" offset="17" />
|
||||
<event name="MaliBinningQueueTask" title="Binning phase tasks" description="The number of binning phase tasks processed." units="tasks" counter="ITER_TILER_IDVS_TASK_COMPLETED" offset="18" />
|
||||
<event name="MaliBinningQueueUtil" title="Binning phase queue utilization" description="The binning phase queue utilization compared against the GPU active cycles. The binning phase includes position shading, culling, and binning." units="percent" equation="(((ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliBinningQueuedCy" title="Binning phase work queued cycles" description="The number of cycles that the binning phase queue has work queued. The binning phase includes position shading, culling, and binning." units="cycles" counter="ITER_TILER_ACTIVE" offset="16" />
|
||||
<event name="MaliCS0WaitStallCy" title="Command stream 0 wait stall cycles" description="The number of cycles that command stream interface 0 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF0_WAIT_BLOCKED" offset="51" />
|
||||
<event name="MaliCS1WaitStallCy" title="Command stream 1 wait stall cycles" description="The number of cycles that command stream interface 1 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF1_WAIT_BLOCKED" offset="55" />
|
||||
<event name="MaliCS2WaitStallCy" title="Command stream 2 wait stall cycles" description="The number of cycles that command stream interface 2 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF2_WAIT_BLOCKED" offset="59" />
|
||||
<event name="MaliCS3WaitStallCy" title="Command stream 3 wait stall cycles" description="The number of cycles that command stream interface 3 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF3_WAIT_BLOCKED" offset="63" />
|
||||
<event name="MaliCSFCEUActiveCy" title="Command execution unit active cycles" description="The number of cycles that the CEU is processing commands." units="cycles" counter="CEU_ACTIVE" offset="40" />
|
||||
<event name="MaliCSFCEUUtil" title="Command execution unit utilization" description="The CSF command execution unit utilization compared against the GPU active cycles." units="percent" equation="((CEU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFCS0ActiveCy" title="Command stream 0 active cycles" description="The number of cycles that command stream interface 0 contained an enabled command stream." units="cycles" counter="CSHWIF0_ENABLED" offset="48" />
|
||||
<event name="MaliCSFCS1ActiveCy" title="Command stream 1 active cycles" description="The number of cycles that command stream interface 1 contained an enabled command stream." units="cycles" counter="CSHWIF1_ENABLED" offset="52" />
|
||||
<event name="MaliCSFCS2ActiveCy" title="Command stream 2 active cycles" description="The number of cycles that command stream interface 2 contained an enabled command stream." units="cycles" counter="CSHWIF2_ENABLED" offset="56" />
|
||||
<event name="MaliCSFCS3ActiveCy" title="Command stream 3 active cycles" description="The number of cycles that command stream interface 3 contained an enabled command stream." units="cycles" counter="CSHWIF3_ENABLED" offset="60" />
|
||||
<event name="MaliCSFLSUActiveCy" title="Command load/store unit active cycles" description="The number of cycles that the load-store unit is processing commands." units="cycles" counter="LSU_ACTIVE" offset="45" />
|
||||
<event name="MaliCSFLSUUtil" title="Command load/store unit utilization" description="The CSF load/store unit utilization compared against the GPU active cycles." units="percent" equation="((LSU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFMCUActiveCy" title="MCU active cycles" description="The number of cycles when the CSF front-end MCU is actively processing." units="cycles" counter="MCU_ACTIVE" offset="5" />
|
||||
<event name="MaliCSFMCUUtil" title="Microcontroller utilization" description="The CSF MCU utilization compared against the GPU active cycles." units="percent" equation="((MCU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueueActiveCy" title="Compute queue active cycles" description="The number of cycles that the compute queue is processing work." units="cycles" equation="(ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)" />
|
||||
<event name="MaliCompQueueAssignStallCy" title="Compute queue endpoint stall cycles" description="The number of cycles the compute queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_COMP_READY_BLOCKED" offset="30" />
|
||||
<event name="MaliCompQueueDrainStallCy" title="Compute queue endpoint drain stall cycles" description="The number of cycles the compute queue is waiting for endpoints to drain." units="cycles" counter="ITER_COMP_EP_DRAIN" offset="31" />
|
||||
<event name="MaliCompQueueIRQActiveCy" title="Compute queue interrupt pending cycles" description="The number of cycles that the compute queue IRQ was pending." units="cycles" counter="ITER_COMP_IRQ_ACTIVE" offset="28" />
|
||||
<event name="MaliCompQueueJob" title="Compute jobs" description="The number of compute jobs processed." units="jobs" counter="ITER_COMP_JOB_COMPLETED" offset="25" />
|
||||
<event name="MaliCompQueueTask" title="Compute tasks" description="The number of compute tasks processed." units="tasks" counter="ITER_COMP_TASK_COMPLETED" offset="26" />
|
||||
<event name="MaliCompQueueUtil" title="Compute queue utilization" description="The compute queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueuedCy" title="Compute work queued cycles" description="The number of cycles that the compute queue has work queued." units="cycles" counter="ITER_COMP_ACTIVE" offset="24" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="4" />
|
||||
<event name="MaliGPUAnyQueueActiveCy" title="Any queue active cycles" description="The number of cycles when any GPU queue is active." units="cycles" counter="GPU_ITER_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQ" title="GPU interrupts" description="The number of interrupts raised by the GPU to the CPU." units="interrupts" counter="GPU_IRQ_COUNT" offset="11" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="10" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliMainQueueActiveCy" title="Main phase queue active cycles" description="The number of cycles that the main phase queue is processing work. The main phase includes deferred vertex shading and all fragment shading." units="cycles" equation="(ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)" />
|
||||
<event name="MaliMainQueueAssignStallCy" title="Main phase queue endpoint stall cycles" description="The number of cycles the main phase queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_FRAG_READY_BLOCKED" offset="38" />
|
||||
<event name="MaliMainQueueIRQActiveCy" title="Main phase queue interrupt pending cycles" description="The number of cycles that the main phase queue IRQ was pending." units="cycles" counter="ITER_FRAG_IRQ_ACTIVE" offset="36" />
|
||||
<event name="MaliMainQueueJob" title="Main phase jobs" description="The number of main phase jobs processed." units="jobs" counter="ITER_FRAG_JOB_COMPLETED" offset="33" />
|
||||
<event name="MaliMainQueueTask" title="Main phase tasks" description="The number of fragment tasks processed." units="tasks" counter="ITER_FRAG_TASK_COMPLETED" offset="34" />
|
||||
<event name="MaliMainQueueUtil" title="Main phase queue utilization" description="The main phase queue utilization compared against the GPU active cycles. The main phase includes deferred vertex shading and all fragment shading." units="percent" equation="(((ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliMainQueuedCy" title="Main phase work queued cycles" description="The number of cycles that the main phase queue has work queued. The main phase includes deferred vertex shading and all fragment shading." units="cycles" counter="ITER_FRAG_ACTIVE" offset="32" />
|
||||
<event name="MaliTilerQueueDrainStallCy" title="Binning phase queue endpoint drain stall cycles" description="The number of cycles the binning phase queue is waiting for endpoints to drain." units="cycles" counter="ITER_TILER_EP_DRAIN" offset="23" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheCleanUnique" title="Input internal clean unique requests" description="The number of L2 cache line clean unique requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_CU" offset="13" />
|
||||
<event name="MaliL2CacheEvict" title="Input internal evict requests" description="The number of L2 cache line evict requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_EVICT" offset="12" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="13" />
|
||||
<event name="MaliL2CacheFlushCy" title="L2 cache flush cycles" description="The number of cycles spent flushing GPU L2 caches." units="cycles" counter="CACHE_FLUSH_CYCLES" offset="12" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="max((EXEC_INSTR_CVT) + (EXEC_INSTR_SFU) + (((EXEC_INSTR_FMA) - min((EXEC_INSTR_FMA), (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) / 2), (EXEC_INSTR_SFU) * 4)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="((max((EXEC_INSTR_CVT) + (EXEC_INSTR_SFU) + (((EXEC_INSTR_FMA) - min((EXEC_INSTR_FMA), (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) / 2), (EXEC_INSTR_SFU) * 4)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAnyActiveCy" title="Any workload active cycles" description="The number of cycles when the shader core is processing either a non-fragment workload or a fragment workload." units="cycles" counter="SHADER_CORE_ACTIVE" offset="53" />
|
||||
<event name="MaliAnyUtil" title="Shader core clock ratio" description="An estimate of shader core use relative to the GPU top-level clock." units="percent" equation="((SHADER_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCompOrBinningActiveCy" title="Compute or binning phase active cycles" description="The number of cycles when the shader core is processing some compute or binning phase workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliCompOrBinningUtil" title="Compute or binning phase utilization" description="The utilization of the shader core compute or binning phase path." units="percent" equation="((COMPUTE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFragWarpOcc" title="Fragment warp occupancy" description="The thread occupancy of the fragment warps." units="percent" equation="((FRAG_SHADER_THREADS) / ((FRAG_WARPS) * (16))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngArithInstr" title="Arithmetic instruction issue cycles" description="The total number of instructions issued to the FMA, CVT, and SFU pipes." units="instructions" equation="(EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)" />
|
||||
<event name="MaliEngCVTInstr" title="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions" counter="EXEC_INSTR_CVT" offset="28" />
|
||||
<event name="MaliEngCVTPipeUtil" title="CVT pipe utilization" description="Defines the utilization of the CVT pipe." units="percent" equation="((EXEC_INSTR_CVT) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="31" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngFMAInstr" title="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions" counter="EXEC_INSTR_FMA" offset="27" />
|
||||
<event name="MaliEngFMAPipeUtil" title="FMA pipe utilization" description="The utilization of the FMA pipes." units="percent" equation="((EXEC_INSTR_FMA) / (2 * (EXEC_CORE_ACTIVE))) * 100" />
|
||||
<event name="MaliEngICacheMiss" title="Instruction cache misses" description="The number of instruction cache misses." units="requests" counter="EXEC_ICACHE_MISS" offset="32" />
|
||||
<event name="MaliEngNarrowInstr" title="Narrow arithmetic instructions" description="The number of narrow arithmetic instructions." units="instructions" counter="EXEC_INSTR_NARROW" offset="5" />
|
||||
<event name="MaliEngNarrowInstrRate" title="Narrow arithmetic percentage" description="The percentage of arithmetic instructions that operate on 8/16-bit types." units="percent" equation="((EXEC_INSTR_NARROW) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngSFUInstr" title="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions" counter="EXEC_INSTR_SFU" offset="29" />
|
||||
<event name="MaliEngSFUPipeUtil" title="SFU pipe utilization" description="The utilization of the SFU pipe." units="percent" equation="(((EXEC_INSTR_SFU) * 4) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSWBlendInstr" title="Blend shader instructions" description="The number of blend shader invocations run." units="instructions" counter="CALL_BLEND_SHADER" offset="34" />
|
||||
<event name="MaliEngSWBlendRate" title="Shader blend percentage" description="The percentage of fragments that use shader-based blending." units="percent" equation="(((CALL_BLEND_SHADER) * 4) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliEngStarveCy" title="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles" counter="EXEC_STARVE_ARITH" offset="33" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="(FRAG_SHADER_THREADS) / ((ITER_FRAG_TASK_COMPLETED) * (64) * (64))" />
|
||||
<event name="MaliFragRastCoarseQd" title="Rasterized coarse quads" description="The number of coarse quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_COARSE" offset="68" />
|
||||
<event name="MaliFragRastPartQd" title="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads" counter="FRAG_PARTIAL_QUADS_RAST" offset="10" />
|
||||
<event name="MaliFragRastPartQdRate" title="Partial coverage percentage" description="The percentage of rasterized fine quads that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_QUADS_RAST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragShadRate" title="Fragment shading rate" description="The percentage of coarse quads generated relative to fine quads rasterized." units="percent" equation="((FRAG_QUADS_COARSE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (16)) / 4" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" counter="FRAG_SHADER_THREADS" offset="69" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / (FRAG_SHADER_THREADS)" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (4 * (FRAG_PTILES))) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliMainActiveCy" title="Main phase active cycles" description="The number of cycles when the shader core is processing a main phase workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliMainUtil" title="Main phase utilization" description="The utilization of the shader core main phase path." units="percent" equation="((FRAG_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragTask" title="Non-main phase core tasks" description="The number of non-main phase tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (16)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (16))" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliRTUBox" title="Ray tracing box tests" description="The number of acceleration structure bounding boxes tested." units="boxes" counter="RT_RAY_BOX" offset="71" />
|
||||
<event name="MaliRTUBoxBin1" title="Ray tracing box nodes with 1-4 rays" description="The number of acceleration structure box nodes with 1 to 4 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_1_4" offset="76" />
|
||||
<event name="MaliRTUBoxBin13" title="Ray tracing box nodes with 13-16 rays" description="The number of acceleration structure box nodes with 13 to 16 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_13_16" offset="79" />
|
||||
<event name="MaliRTUBoxBin5" title="Ray tracing box nodes with 5-8 rays" description="The number of acceleration structure box nodes with 5 to 8 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_5_8" offset="77" />
|
||||
<event name="MaliRTUBoxBin9" title="Ray tracing box nodes with 9-12 rays" description="The number of acceleration structure box nodes with 9 to 12 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_9_12" offset="78" />
|
||||
<event name="MaliRTUBoxIssueCy" title="Ray tracing box tester issue cycles" description="The number of active issue cycles for the ray tracing box test unit." units="cycles" counter="RT_RAY_BOX_ISSUED" offset="85" />
|
||||
<event name="MaliRTUFirstHitTerm" title="Ray tracing first hit terminations" description="The number of rays that terminate on their first hit." units="rays" counter="RT_TERM_FIRST_HIT" offset="82" />
|
||||
<event name="MaliRTUIssueCy" title="Ray tracing unit issue cycles" description="The number of cycles the ray tracing unit was issuing work." units="cycles" equation="max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))" />
|
||||
<event name="MaliRTUMiss" title="Ray tracing triangle test misses" description="The number of triangle intersection tests that do not intersect." units="rays" counter="RT_MISS" offset="83" />
|
||||
<event name="MaliRTUNonOpaqueHit" title="Ray tracing non-opaque triangle hits" description="The number of non-opaque triangle hits." units="tests" counter="RT_NON_OPAQUE_HIT" offset="81" />
|
||||
<event name="MaliRTUOpaqueHit" title="Ray tracing opaque triangle hits" description="The number of opaque triangle hits." units="tests" counter="RT_OPAQUE_HIT" offset="80" />
|
||||
<event name="MaliRTURay" title="Ray tracing started rays" description="The number of rays started." units="rays" counter="RT_RAYS_STARTED" offset="84" />
|
||||
<event name="MaliRTUTri" title="Ray tracing triangle nodes tested" description="The number of triangle nodes tested." units="nodes" counter="RT_RAY_TRI" offset="70" />
|
||||
<event name="MaliRTUTriBin1" title="Ray tracing triangle nodes with 1-4 rays" description="The number of triangle nodes with 1 to 4 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_1_4" offset="72" />
|
||||
<event name="MaliRTUTriBin13" title="Ray tracing triangle nodes with 13-16 rays" description="The number of triangle nodes with 13 to 16 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_13_16" offset="75" />
|
||||
<event name="MaliRTUTriBin5" title="Ray tracing triangle nodes with 5-8 rays" description="The number of triangle nodes with 5 to 8 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_5_8" offset="73" />
|
||||
<event name="MaliRTUTriBin9" title="Ray tracing triangle nodes with 9-12 rays" description="The number of triangle nodes with 9 to 12 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_9_12" offset="74" />
|
||||
<event name="MaliRTUTriIssueCy" title="Ray tracing triangle tester issue cycles" description="The number of active issue cycles for the ray tracing triangle test unit." units="cycles" counter="RT_RAY_TRI_ISSUED" offset="86" />
|
||||
<event name="MaliRTUUtil" title="Ray tracing unit utilization" description="The percentage utilization of the ray tracing unit." units="percent" equation="((max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((ITER_FRAG_TASK_COMPLETED) * (64) * (64))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="(max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))) / ((((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)) * 4)" />
|
||||
<event name="MaliTexCacheComplexLoadCy" title="Complex texture load cycles" description="The number of cycles loading complex texture formats." units="cycles" counter="TEX_CFCH_NUM_RP_OPERATIONS" offset="93" />
|
||||
<event name="MaliTexCacheLookupCy" title="Texture cache lookup cycles" description="The number of cycles returning data from the texture cache." units="cycles" counter="TEX_TFCH_NUM_TCL_OPERATIONS" offset="92" />
|
||||
<event name="MaliTexCacheSimpleLoadCy" title="Simple texture load cycles" description="The number of cycles loading simple texture formats." units="cycles" counter="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" offset="88" />
|
||||
<event name="MaliTexClkActiveCy" title="Texture unit clock active cycles" description="The number of cycles the texture unit was active." units="cycles" counter="TEX_TEXP_CLK_ACTIVE" offset="96" />
|
||||
<event name="MaliTexClkStarvedCy" title="Texture causing starvation cycles" description="The number of cycles the texture unit was active but did not return a texture sample." units="cycles" counter="TEX_MSGI_CLK_STARVED" offset="95" />
|
||||
<event name="MaliTexDataFetchStallCy" title="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles" counter="TEX_TFCH_CLK_STALLED" offset="37" />
|
||||
<event name="MaliTexDescStallCy" title="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles" counter="TEX_DFCH_CLK_STALLED" offset="36" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="39" />
|
||||
<event name="MaliTexFiltStallCy" title="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" offset="38" />
|
||||
<event name="MaliTexInBt" title="Texture message read beats" description="The number of texture request message data beats." units="beats" counter="TEX_MSGI_NUM_FLITS" offset="35" />
|
||||
<event name="MaliTexInBusUtil" title="Texture input bus utilization" description="The percentage load on the texture message input bus." units="percent" equation="((TEX_MSGI_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexIndexCy" title="Texture index calculation cycles" description="The number of cycles computing texel index values." units="cycles" counter="TEX_TIDX_NUM_OPERATIONS" offset="94" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))" />
|
||||
<event name="MaliTexL1CacheLoadCy" title="L1 texture cache load cycles" description="The number of cycles the L1 cache is being loaded." units="cycles" counter="TEX_CFCH_NUM_OUTPUT_OPERATIONS" offset="87" />
|
||||
<event name="MaliTexL1CacheLookupCy" title="L1 texture cache lookup cycles" description="The number of cycles the L1 cache is being accessed." units="cycles" counter="TEX_CFCH_NUM_L1_CT_OPERATIONS" offset="90" />
|
||||
<event name="MaliTexL1CacheOutputCy" title="L1 texture cache output cycles" description="The number of cycles the L1 cache is returning data." units="cycles" counter="TEX_CFCH_NUM_L1_CL_OPERATIONS" offset="89" />
|
||||
<event name="MaliTexOutBt" title="Texture message write beats" description="The number of texture response message data beats." units="beats" counter="TEX_MSGO_NUM_FLITS" offset="43" />
|
||||
<event name="MaliTexOutBusUtil" title="Texture output bus utilization" description="The percentage load on the texture message output bus." units="percent" equation="((TEX_MSGO_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexOutMsg" title="Texture messages" description="The number of output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_MSG" offset="42" />
|
||||
<event name="MaliTexOutSingleMsg" title="Texture messages with single quad" description="The number of single quad output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_SINGLE_QUAD_MSG" offset="91" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" equation="((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)) * 4" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="((max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (4)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (4)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceCullPrim" title="Facing test culled primitives" description="The number of primitives that are culled by facing tests." units="primitives" counter="PRIM_FACE_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceCullRate" title="Facing plane test cull percentage" description="The percentage of primitives culled by the facing test." units="percent" equation="((PRIM_FACE_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED) - (PRIM_SCISSOR_CULLED))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPlaneCullPrim" title="Frustum test culled primitives" description="The number of primitives that are culled by frustum tests." units="primitives" counter="PRIM_FRUSTUM_CULLED" offset="13" />
|
||||
<event name="MaliGeomPlaneCullRate" title="Frustum test cull percentage" description="The percentage of primitives culled by the frustum test." units="percent" equation="((PRIM_FRUSTUM_CULLED) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED) - (PRIM_SCISSOR_CULLED) - (PRIM_FACE_CULLED))) * 100" />
|
||||
<event name="MaliGeomScissorCullPrim" title="Scissor test culled primitives" description="The number of primitives that are culled by the scissor test." units="primitives" counter="PRIM_SCISSOR_CULLED" offset="70" />
|
||||
<event name="MaliGeomScissorCullRate" title="Scissor test cull percentage" description="The percentage of primitives culled by the scissor test." units="percent" equation="((PRIM_SCISSOR_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVisibleDVSPrim" title="Visible primitives using DVS" description="The number of primitives using DVS that are visible after culling." units="primitives" counter="PRIM_VISIBLE_DVS" offset="71" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerPrimAsPosShadStallCy" title="Primitive assembly position shading stall cycles" description="The number of cycles when primitive assembly is waiting for position shading." units="cycles" counter="PRIMASSY_POS_SHADER_WAIT" offset="64" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
</category>
|
||||
</metrics>
|
||||
335
src/panfrost/perf/generated/G725.xml
Normal file
335
src/panfrost/perf/generated/G725.xml
Normal file
|
|
@ -0,0 +1,335 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G725">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliBinningQueueActiveCy" title="Binning phase queue active cycles" description="The number of cycles that the binning phase queue is processing work. The binning phase includes position shading, culling, and binning." units="cycles" equation="(ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)" />
|
||||
<event name="MaliBinningQueueAssignStallCy" title="Binning phase queue endpoint stall cycles" description="The number of cycles the binning phase queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_TILER_READY_BLOCKED" offset="70" />
|
||||
<event name="MaliBinningQueueIRQActiveCy" title="Binning phase queue interrupt pending cycles" description="The number of cycles that the binning phase queue IRQ was pending." units="cycles" counter="ITER_TILER_IRQ_ACTIVE" offset="68" />
|
||||
<event name="MaliBinningQueueJob" title="Binning phase jobs" description="The number of binning phase jobs processed." units="jobs" counter="ITER_TILER_JOB_COMPLETED" offset="65" />
|
||||
<event name="MaliBinningQueueTask" title="Binning phase tasks" description="The number of binning phase tasks processed." units="tasks" counter="ITER_TILER_IDVS_TASK_COMPLETED" offset="66" />
|
||||
<event name="MaliBinningQueueUtil" title="Binning phase queue utilization" description="The binning phase queue utilization compared against the GPU active cycles. The binning phase includes position shading, culling, and binning." units="percent" equation="(((ITER_TILER_ACTIVE) - (ITER_TILER_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliBinningQueuedCy" title="Binning phase work queued cycles" description="The number of cycles that the binning phase queue has work queued. The binning phase includes position shading, culling, and binning." units="cycles" counter="ITER_TILER_ACTIVE" offset="64" />
|
||||
<event name="MaliCS0WaitStallCy" title="Command stream 0 wait stall cycles" description="The number of cycles that command stream interface 0 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF0_WAIT_BLOCKED" offset="84" />
|
||||
<event name="MaliCS1WaitStallCy" title="Command stream 1 wait stall cycles" description="The number of cycles that command stream interface 1 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF1_WAIT_BLOCKED" offset="90" />
|
||||
<event name="MaliCS2WaitStallCy" title="Command stream 2 wait stall cycles" description="The number of cycles that command stream interface 2 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF2_WAIT_BLOCKED" offset="96" />
|
||||
<event name="MaliCS3WaitStallCy" title="Command stream 3 wait stall cycles" description="The number of cycles that command stream interface 3 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF3_WAIT_BLOCKED" offset="102" />
|
||||
<event name="MaliCS4WaitStallCy" title="Command stream 4 wait stall cycles" description="The number of cycles that command stream interface 4 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF4_WAIT_BLOCKED" offset="108" />
|
||||
<event name="MaliCS5WaitStallCy" title="Command stream 5 wait stall cycles" description="The number of cycles that command stream interface 5 was blocked because of a scheduling dependency." units="cycles" counter="CSHWIF5_WAIT_BLOCKED" offset="114" />
|
||||
<event name="MaliCSDoorbellIRQCy" title="Command stream doorbell interrupt pending cycles" description="The number of cycles that command stream doorbell has an IRQ pending." units="cycles" counter="DOORBELL_IRQ_ACTIVE" offset="14" />
|
||||
<event name="MaliCSFCEUActiveCy" title="Command execution unit active cycles" description="The number of cycles that the CEU is processing commands." units="cycles" counter="CEU_ACTIVE" offset="16" />
|
||||
<event name="MaliCSFCEUUtil" title="Command execution unit utilization" description="The CSF command execution unit utilization compared against the GPU active cycles." units="percent" equation="((CEU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFCS0ActiveCy" title="Command stream 0 active cycles" description="The number of cycles that command stream interface 0 contained an enabled command stream." units="cycles" counter="CSHWIF0_ENABLED" offset="80" />
|
||||
<event name="MaliCSFCS1ActiveCy" title="Command stream 1 active cycles" description="The number of cycles that command stream interface 1 contained an enabled command stream." units="cycles" counter="CSHWIF1_ENABLED" offset="86" />
|
||||
<event name="MaliCSFCS2ActiveCy" title="Command stream 2 active cycles" description="The number of cycles that command stream interface 2 contained an enabled command stream." units="cycles" counter="CSHWIF2_ENABLED" offset="92" />
|
||||
<event name="MaliCSFCS3ActiveCy" title="Command stream 3 active cycles" description="The number of cycles that command stream interface 3 contained an enabled command stream." units="cycles" counter="CSHWIF3_ENABLED" offset="98" />
|
||||
<event name="MaliCSFCS4ActiveCy" title="Command stream 4 active cycles" description="The number of cycles that command stream interface 4 contained an enabled command stream." units="cycles" counter="CSHWIF4_ENABLED" offset="104" />
|
||||
<event name="MaliCSFCS5ActiveCy" title="Command stream 5 active cycles" description="The number of cycles that command stream interface 5 contained an enabled command stream." units="cycles" counter="CSHWIF5_ENABLED" offset="110" />
|
||||
<event name="MaliCSFLSUActiveCy" title="Command load/store unit active cycles" description="The number of cycles that the load-store unit is processing commands." units="cycles" counter="LSU_ACTIVE" offset="21" />
|
||||
<event name="MaliCSFLSUUtil" title="Command load/store unit utilization" description="The CSF load/store unit utilization compared against the GPU active cycles." units="percent" equation="((LSU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCSFMCUActiveCy" title="MCU active cycles" description="The number of cycles when the CSF front-end MCU is actively processing." units="cycles" counter="MCU_ACTIVE" offset="5" />
|
||||
<event name="MaliCSFMCUUtil" title="Microcontroller utilization" description="The CSF MCU utilization compared against the GPU active cycles." units="percent" equation="((MCU_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueueActiveCy" title="Compute queue active cycles" description="The number of cycles that the compute queue is processing work." units="cycles" equation="(ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)" />
|
||||
<event name="MaliCompQueueAssignStallCy" title="Compute queue endpoint stall cycles" description="The number of cycles the compute queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_COMP_READY_BLOCKED" offset="38" />
|
||||
<event name="MaliCompQueueDrainStallCy" title="Compute queue endpoint drain stall cycles" description="The number of cycles the compute queue is waiting for endpoints to drain." units="cycles" counter="ITER_COMP_EP_DRAIN" offset="39" />
|
||||
<event name="MaliCompQueueIRQActiveCy" title="Compute queue interrupt pending cycles" description="The number of cycles that the compute queue IRQ was pending." units="cycles" counter="ITER_COMP_IRQ_ACTIVE" offset="36" />
|
||||
<event name="MaliCompQueueJob" title="Compute jobs" description="The number of compute jobs processed." units="jobs" counter="ITER_COMP_JOB_COMPLETED" offset="33" />
|
||||
<event name="MaliCompQueueTask" title="Compute tasks" description="The number of compute tasks processed." units="tasks" counter="ITER_COMP_TASK_COMPLETED" offset="34" />
|
||||
<event name="MaliCompQueueUtil" title="Compute queue utilization" description="The compute queue utilization compared against the GPU active cycles." units="percent" equation="(((ITER_COMP_ACTIVE) - (ITER_COMP_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliCompQueuedCy" title="Compute work queued cycles" description="The number of cycles that the compute queue has work queued." units="cycles" counter="ITER_COMP_ACTIVE" offset="32" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="4" />
|
||||
<event name="MaliGPUAnyQueueActiveCy" title="Any queue active cycles" description="The number of cycles when any GPU queue is active." units="cycles" counter="GPU_ITER_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQ" title="GPU interrupts" description="The number of interrupts raised by the GPU to the CPU." units="interrupts" counter="GPU_IRQ_COUNT" offset="11" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="10" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliMainQueueActiveCy" title="Main phase queue active cycles" description="The number of cycles that the main phase queue is processing work. The main phase includes deferred vertex shading and all fragment shading." units="cycles" equation="(ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)" />
|
||||
<event name="MaliMainQueueAssignStallCy" title="Main phase queue endpoint stall cycles" description="The number of cycles the main phase queue is waiting for endpoints to be assigned." units="cycles" counter="ITER_FRAG_READY_BLOCKED" offset="54" />
|
||||
<event name="MaliMainQueueIRQActiveCy" title="Main phase queue interrupt pending cycles" description="The number of cycles that the main phase queue IRQ was pending." units="cycles" counter="ITER_FRAG_IRQ_ACTIVE" offset="52" />
|
||||
<event name="MaliMainQueueJob" title="Main phase jobs" description="The number of main phase jobs processed." units="jobs" counter="ITER_FRAG_JOB_COMPLETED" offset="49" />
|
||||
<event name="MaliMainQueueTask" title="Main phase tasks" description="The number of fragment tasks processed." units="tasks" counter="ITER_FRAG_TASK_COMPLETED" offset="50" />
|
||||
<event name="MaliMainQueueUtil" title="Main phase queue utilization" description="The main phase queue utilization compared against the GPU active cycles. The main phase includes deferred vertex shading and all fragment shading." units="percent" equation="(((ITER_FRAG_ACTIVE) - (ITER_FRAG_READY_BLOCKED)) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliMainQueuedCy" title="Main phase work queued cycles" description="The number of cycles that the main phase queue has work queued. The main phase includes deferred vertex shading and all fragment shading." units="cycles" counter="ITER_FRAG_ACTIVE" offset="48" />
|
||||
<event name="MaliTilerQueueDrainStallCy" title="Binning phase queue endpoint drain stall cycles" description="The number of cycles the binning phase queue is waiting for endpoints to drain." units="cycles" counter="ITER_TILER_EP_DRAIN" offset="71" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheCleanUnique" title="Input internal clean unique requests" description="The number of L2 cache line clean unique requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_CU" offset="13" />
|
||||
<event name="MaliL2CacheEvict" title="Input internal evict requests" description="The number of L2 cache line evict requests from internal requesters." units="requests" counter="L2_RD_MSG_IN_EVICT" offset="12" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="13" />
|
||||
<event name="MaliL2CacheFlushCy" title="L2 cache flush cycles" description="The number of cycles spent flushing GPU L2 caches." units="cycles" counter="CACHE_FLUSH_CYCLES" offset="12" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="max((((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)) - (EXEC_INSTR_SLOT_1)), (EXEC_INSTR_SLOT_1), (EXEC_INSTR_SFU) * 4)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="((max((((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)) - (EXEC_INSTR_SLOT_1)), (EXEC_INSTR_SLOT_1), (EXEC_INSTR_SFU) * 4)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAnyActiveCy" title="Any workload active cycles" description="The number of cycles when the shader core is processing either a non-fragment workload or a fragment workload." units="cycles" counter="SHADER_CORE_ACTIVE" offset="53" />
|
||||
<event name="MaliAnyUtil" title="Shader core clock ratio" description="An estimate of shader core use relative to the GPU top-level clock." units="percent" equation="((SHADER_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCompOrBinningActiveCy" title="Compute or binning phase active cycles" description="The number of cycles when the shader core is processing some compute or binning phase workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliCompOrBinningUtil" title="Compute or binning phase utilization" description="The utilization of the shader core compute or binning phase path." units="percent" equation="((COMPUTE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFragWarpOcc" title="Fragment warp occupancy" description="The thread occupancy of the fragment warps." units="percent" equation="((FRAG_SHADER_THREADS) / ((FRAG_WARPS) * (16))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliDefVertWarp" title="Deferred vertex warps" description="The number of deferred vertex warps created." units="warps" counter="DVS_WARPS" offset="106" />
|
||||
<event name="MaliEngArithInstr" title="Arithmetic instruction issue cycles" description="The total number of instructions issued to the FMA, CVT, and SFU pipes." units="instructions" equation="(EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)" />
|
||||
<event name="MaliEngAttrBackpressureCy" title="Attribute unit backpressure cycles" description="The number of cycles new work could not be sent to the attribute unit." units="cycles" counter="EXEC_MSG_STALLED_ATTR" offset="117" />
|
||||
<event name="MaliEngAttrBackpressureRate" title="Attribute unit backpressure percentage" description="The percentage of cycles new work could not be sent to the attribute unit." units="percent" equation="((EXEC_MSG_STALLED_ATTR) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngBlendBackpressureCy" title="Blend unit backpressure cycles" description="The number of cycles new work could not be sent to the blend unit." units="cycles" counter="EXEC_MSG_STALLED_BLEND" offset="114" />
|
||||
<event name="MaliEngBlendBackpressureRate" title="Blend unit backpressure percentage" description="The percentage of cycles new work could not be sent to the blend unit." units="percent" equation="((EXEC_MSG_STALLED_BLEND) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngCVTInstr" title="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions" counter="EXEC_INSTR_CVT" offset="28" />
|
||||
<event name="MaliEngCVTPipeUtil" title="CVT pipe utilization" description="Defines the utilization of the CVT pipes." units="percent" equation="((EXEC_INSTR_CVT) / (2 * (EXEC_CORE_ACTIVE))) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="31" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngFMAInstr" title="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions" counter="EXEC_INSTR_FMA" offset="27" />
|
||||
<event name="MaliEngFMAPipeUtil" title="FMA pipe utilization" description="The utilization of the FMA pipes." units="percent" equation="((EXEC_INSTR_FMA) / (2 * (EXEC_CORE_ACTIVE))) * 100" />
|
||||
<event name="MaliEngICacheMiss" title="Instruction cache misses" description="The number of instruction cache misses." units="requests" counter="EXEC_ICACHE_MISS" offset="32" />
|
||||
<event name="MaliEngLSBackpressureCy" title="Load/store unit backpressure cycles" description="The number of cycles new work could not be sent to the load/store unit." units="cycles" counter="EXEC_MSG_STALLED_LSC" offset="116" />
|
||||
<event name="MaliEngLSBackpressureRate" title="Load/store unit backpressure percentage" description="The percentage of cycles new work could not be sent to the load/store unit." units="percent" equation="((EXEC_MSG_STALLED_LSC) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngNarrowInstr" title="Narrow arithmetic instructions" description="The number of narrow arithmetic instructions." units="instructions" counter="EXEC_INSTR_NARROW" offset="5" />
|
||||
<event name="MaliEngNarrowInstrRate" title="Narrow arithmetic percentage" description="The percentage of arithmetic instructions that operate on 8/16-bit types." units="percent" equation="((EXEC_INSTR_NARROW) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngSFUInstr" title="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions" counter="EXEC_INSTR_SFU" offset="29" />
|
||||
<event name="MaliEngSFUPipeUtil" title="SFU pipe utilization" description="The utilization of the SFU pipe." units="percent" equation="(((EXEC_INSTR_SFU) * 4) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSWBlendInstr" title="Blend shader instructions" description="The number of blend shader invocations run." units="instructions" counter="CALL_BLEND_SHADER" offset="34" />
|
||||
<event name="MaliEngSWBlendRate" title="Shader blend percentage" description="The percentage of fragments that use shader-based blending." units="percent" equation="(((CALL_BLEND_SHADER) * 4) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliEngSlot0IssueCy" title="Slot 0 arithmetic issue cycles" description="The number of arithmetic issue cycles to slot 0." units="cycles" equation="((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)) - (EXEC_INSTR_SLOT_1)" />
|
||||
<event name="MaliEngSlot1IssueCy" title="Slot 1 arithmetic issue cycles" description="The number of arithmetic issue cycles to slot 1." units="cycles" counter="EXEC_INSTR_SLOT_1" offset="118" />
|
||||
<event name="MaliEngSlotAnyIssueCy" title="Any slot arithmetic issue cycles" description="The number of arithmetic issue cycles that issue to either issue slot." units="cycles" counter="EXEC_ISSUE_SLOT_ANY" offset="119" />
|
||||
<event name="MaliEngStarveCy" title="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles" counter="EXEC_STARVE_ARITH" offset="33" />
|
||||
<event name="MaliEngTexBackpressureCy" title="Texture unit backpressure cycles" description="The number of cycles new work could not be sent to the texture unit." units="cycles" counter="EXEC_MSG_STALLED_TEX" offset="112" />
|
||||
<event name="MaliEngTexBackpressureRate" title="Texture unit backpressure percentage" description="The percentage of cycles new work could not be sent to the texture unit." units="percent" equation="((EXEC_MSG_STALLED_TEX) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngVarBackpressureCy" title="Varying unit backpressure cycles" description="The number of cycles new work could not be sent to the varying unit." units="cycles" counter="EXEC_MSG_STALLED_VARY" offset="113" />
|
||||
<event name="MaliEngVarBackpressureRate" title="Varying unit backpressure percentage" description="The percentage of cycles new work could not be sent to the varying unit." units="percent" equation="((EXEC_MSG_STALLED_VARY) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngZSBackpressureCy" title="ZS unit backpressure cycles" description="The number of cycles new work could not be sent to the depth/stencil test unit." units="cycles" counter="EXEC_MSG_STALLED_ZS" offset="115" />
|
||||
<event name="MaliEngZSBackpressureRate" title="ZS unit backpressure percentage" description="The percentage of cycles new work could not be sent to the depth/stencil test unit." units="percent" equation="((EXEC_MSG_STALLED_ZS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragInputPrim" title="Input fragment primitives" description="The number of unique primitives loaded by the fragment front-end." units="primitives" equation="((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS)" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (4 * (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (4 * (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliFragMainPassStallCy" title="Fragment main pass stall cycles" description="The number of cycles when the fragment main pass is stalled waiting for prepass results." units="cycles" counter="FRAG_MAIN_PASS_STALLED_BY_PRE_PASS" offset="105" />
|
||||
<event name="MaliFragMainPassStallRate" title="Fragment main pass stall percentage" description="The percentage of cycles when the fragment main pass is stalled by the fragment prepass." units="percent" equation="((FRAG_MAIN_PASS_STALLED_BY_PRE_PASS) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragMainThread" title="Fragment main pass threads" description="The number of fragment threads started in the main pass." units="threads" equation="((FRAG_WARPS) - (FRAG_WARPS_PRE_PASS)) * (16)" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="(FRAG_SHADER_THREADS) / ((ITER_FRAG_TASK_COMPLETED) * (64) * (64))" />
|
||||
<event name="MaliFragPrepassCullPrim" title="Fragment prepass culled primitives" description="The number of primitives culled by the fragment prepass." units="primitives" counter="FRAG_PRIMITIVES_HSR_CULLED" offset="98" />
|
||||
<event name="MaliFragPrepassCullPrimRate" title="Fragment prepass primitive culling percentage" description="The percentage of primitives culled by the fragment prepass." units="percent" equation="((FRAG_PRIMITIVES_HSR_CULLED) / (((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrepassEZSUpdateQd" title="Fragment prepass early ZS updated quads" description="The number of quads that update the fragment prepass using early ZS." units="quads" counter="FRAG_QUADS_HSR_BUF_EZS_UPDATE" offset="101" />
|
||||
<event name="MaliFragPrepassKillQd" title="Fragment prepass killed quads" description="The number of quads that are killed by the fragment prepass." units="quads" counter="FRAG_QUADS_HSR_BUF_KILLED" offset="103" />
|
||||
<event name="MaliFragPrepassKillRate" title="Fragment prepass killed quad percentage" description="The percentage of tested quads that are killed by the fragment prepass." units="percent" equation="((FRAG_QUADS_HSR_BUF_KILLED) / (FRAG_QUADS_HSR_BUF_TEST)) * 100" />
|
||||
<event name="MaliFragPrepassPrim" title="Loaded fragment prepass primitives" description="The number of primitives loaded by the fragment front-end for the fragment prepass." units="primitives" counter="FRAG_PRIMITIVES_OUT_PRE_PASS" offset="99" />
|
||||
<event name="MaliFragPrepassPrimRate" title="Fragment prepass primitive percentage" description="The percentage of primitives processed by fragment prepass hidden surface removal." units="percent" equation="((FRAG_PRIMITIVES_OUT_PRE_PASS) / (((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrepassSkipPrimRate" title="Fragment prepass skipped primitive percentage" description="The percentage of primitives that are skipped by the fragment prepass." units="percent" equation="((FRAG_PRIMITIVES_HSR_DISABLED) / (((FRAG_PRIMITIVES_OUT) + (FRAG_PRIMITIVES_HSR_CULLED)) - (FRAG_PRIMITIVES_OUT_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrepassSkippedPrim" title="Fragment prepass skipped primitives" description="The number of primitives that are skipped by the fragment prepass." units="primitives" counter="FRAG_PRIMITIVES_HSR_DISABLED" offset="100" />
|
||||
<event name="MaliFragPrepassTestQd" title="Fragment prepass tested quads" description="The number of quads that are tested by the fragment prepass." units="quads" counter="FRAG_QUADS_HSR_BUF_TEST" offset="102" />
|
||||
<event name="MaliFragPrepassThread" title="Fragment prepass threads" description="The number of fragment threads started in the prepass." units="threads" equation="(FRAG_WARPS_PRE_PASS) * (16)" />
|
||||
<event name="MaliFragPrepassWarp" title="Fragment prepass warps" description="The number of fragment prepass warps created." units="warps" counter="FRAG_WARPS_PRE_PASS" offset="104" />
|
||||
<event name="MaliFragPrepassWarpRate" title="Fragment prepass warp percentage" description="The percentage of warps being processed by the fragment prepass." units="percent" equation="((FRAG_WARPS_PRE_PASS) / ((FRAG_WARPS) - (FRAG_WARPS_PRE_PASS))) * 100" />
|
||||
<event name="MaliFragPrim" title="Loaded fragment primitives" description="The number of primitives loaded by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES_OUT" offset="97" />
|
||||
<event name="MaliFragRastCoarseQd" title="Rasterized coarse quads" description="The number of coarse quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_COARSE" offset="68" />
|
||||
<event name="MaliFragRastPartQd" title="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads" counter="FRAG_PARTIAL_QUADS_RAST" offset="10" />
|
||||
<event name="MaliFragRastPartQdRate" title="Partial coverage percentage" description="The percentage of rasterized fine quads that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_QUADS_RAST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragShadRate" title="Fragment shading rate" description="The percentage of coarse quads generated relative to fine quads rasterized." units="percent" equation="((FRAG_QUADS_COARSE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (16)) / 4" />
|
||||
<event name="MaliFragThread" title="All fragment threads" description="The number of fragment threads started in the prepass and main pass." units="threads" counter="FRAG_SHADER_THREADS" offset="69" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / (((FRAG_WARPS) - (FRAG_WARPS_PRE_PASS)) * (16))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (4 * (FRAG_PTILES))) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliMainActiveCy" title="Main phase active cycles" description="The number of cycles when the shader core is processing a main phase workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliMainUtil" title="Main phase utilization" description="The utilization of the shader core main phase path." units="percent" equation="((FRAG_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragTask" title="Non-main phase core tasks" description="The number of non-main phase tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (16)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (16))" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliRTUBox" title="Ray tracing box tests" description="The number of acceleration structure bounding boxes tested." units="boxes" counter="RT_RAY_BOX" offset="71" />
|
||||
<event name="MaliRTUBoxBin1" title="Ray tracing box nodes with 1-4 rays" description="The number of acceleration structure box nodes with 1 to 4 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_1_4" offset="76" />
|
||||
<event name="MaliRTUBoxBin13" title="Ray tracing box nodes with 13-16 rays" description="The number of acceleration structure box nodes with 13 to 16 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_13_16" offset="79" />
|
||||
<event name="MaliRTUBoxBin5" title="Ray tracing box nodes with 5-8 rays" description="The number of acceleration structure box nodes with 5 to 8 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_5_8" offset="77" />
|
||||
<event name="MaliRTUBoxBin9" title="Ray tracing box nodes with 9-12 rays" description="The number of acceleration structure box nodes with 9 to 12 active rays in the warp." units="nodes" counter="RT_RAY_BOX_BIN_9_12" offset="78" />
|
||||
<event name="MaliRTUBoxIssueCy" title="Ray tracing box tester issue cycles" description="The number of active issue cycles for the ray tracing box test unit." units="cycles" counter="RT_RAY_BOX_ISSUED" offset="85" />
|
||||
<event name="MaliRTUFirstHitTerm" title="Ray tracing first hit terminations" description="The number of rays that terminate on their first hit." units="rays" counter="RT_TERM_FIRST_HIT" offset="82" />
|
||||
<event name="MaliRTUIssueCy" title="Ray tracing unit issue cycles" description="The number of cycles the ray tracing unit was issuing work." units="cycles" equation="max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))" />
|
||||
<event name="MaliRTUMiss" title="Ray tracing triangle test misses" description="The number of triangle intersection tests that do not intersect." units="rays" counter="RT_MISS" offset="83" />
|
||||
<event name="MaliRTUNonOpaqueHit" title="Ray tracing non-opaque triangle hits" description="The number of non-opaque triangle hits." units="tests" counter="RT_NON_OPAQUE_HIT" offset="81" />
|
||||
<event name="MaliRTUOpaqueHit" title="Ray tracing opaque triangle hits" description="The number of opaque triangle hits." units="tests" counter="RT_OPAQUE_HIT" offset="80" />
|
||||
<event name="MaliRTURay" title="Ray tracing started rays" description="The number of rays started." units="rays" counter="RT_RAYS_STARTED" offset="84" />
|
||||
<event name="MaliRTUTri" title="Ray tracing triangle nodes tested" description="The number of triangle nodes tested." units="nodes" counter="RT_RAY_TRI" offset="70" />
|
||||
<event name="MaliRTUTriBin1" title="Ray tracing triangle nodes with 1-4 rays" description="The number of triangle nodes with 1 to 4 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_1_4" offset="72" />
|
||||
<event name="MaliRTUTriBin13" title="Ray tracing triangle nodes with 13-16 rays" description="The number of triangle nodes with 13 to 16 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_13_16" offset="75" />
|
||||
<event name="MaliRTUTriBin5" title="Ray tracing triangle nodes with 5-8 rays" description="The number of triangle nodes with 5 to 8 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_5_8" offset="73" />
|
||||
<event name="MaliRTUTriBin9" title="Ray tracing triangle nodes with 9-12 rays" description="The number of triangle nodes with 9 to 12 active rays in the warp." units="nodes" counter="RT_RAY_TRI_BIN_9_12" offset="74" />
|
||||
<event name="MaliRTUTriIssueCy" title="Ray tracing triangle tester issue cycles" description="The number of active issue cycles for the ray tracing triangle test unit." units="cycles" counter="RT_RAY_TRI_ISSUED" offset="86" />
|
||||
<event name="MaliRTUUtil" title="Ray tracing unit utilization" description="The percentage utilization of the ray tracing unit." units="percent" equation="((max((RT_RAY_BOX_ISSUED), (RT_RAY_TRI_ISSUED))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((ITER_FRAG_TASK_COMPLETED) * (64) * (64))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="(max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))) / ((((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)) * 4)" />
|
||||
<event name="MaliTexCacheComplexLoadCy" title="Complex texture load cycles" description="The number of cycles loading complex texture formats." units="cycles" counter="TEX_CFCH_NUM_RP_OPERATIONS" offset="93" />
|
||||
<event name="MaliTexCacheLookupCy" title="Texture cache lookup cycles" description="The number of cycles returning data from the texture cache." units="cycles" counter="TEX_TFCH_NUM_TCL_OPERATIONS" offset="92" />
|
||||
<event name="MaliTexCacheSimpleLoadCy" title="Simple texture load cycles" description="The number of cycles loading simple texture formats." units="cycles" counter="TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS" offset="88" />
|
||||
<event name="MaliTexClkActiveCy" title="Texture unit clock active cycles" description="The number of cycles the texture unit was active." units="cycles" counter="TEX_TEXP_CLK_ACTIVE" offset="96" />
|
||||
<event name="MaliTexClkStarvedCy" title="Texture causing starvation cycles" description="The number of cycles the texture unit was active but did not return a texture sample." units="cycles" counter="TEX_MSGI_CLK_STARVED" offset="95" />
|
||||
<event name="MaliTexDataFetchStallCy" title="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles" counter="TEX_TFCH_CLK_STALLED" offset="37" />
|
||||
<event name="MaliTexDescStallCy" title="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles" counter="TEX_DFCH_CLK_STALLED" offset="36" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="39" />
|
||||
<event name="MaliTexFiltStallCy" title="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" offset="38" />
|
||||
<event name="MaliTexInBt" title="Texture message read beats" description="The number of texture request message data beats." units="beats" counter="TEX_MSGI_NUM_FLITS" offset="35" />
|
||||
<event name="MaliTexInBusUtil" title="Texture input bus utilization" description="The percentage load on the texture message input bus." units="percent" equation="((TEX_MSGI_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexIndexCy" title="Texture index calculation cycles" description="The number of cycles computing texel index values." units="cycles" counter="TEX_TIDX_NUM_OPERATIONS" offset="94" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))" />
|
||||
<event name="MaliTexL1CacheLoadCy" title="L1 texture cache load cycles" description="The number of cycles the L1 cache is being loaded." units="cycles" counter="TEX_CFCH_NUM_OUTPUT_OPERATIONS" offset="87" />
|
||||
<event name="MaliTexL1CacheLookupCy" title="L1 texture cache lookup cycles" description="The number of cycles the L1 cache is being accessed." units="cycles" counter="TEX_CFCH_NUM_L1_CT_OPERATIONS" offset="90" />
|
||||
<event name="MaliTexL1CacheOutputCy" title="L1 texture cache output cycles" description="The number of cycles the L1 cache is returning data." units="cycles" counter="TEX_CFCH_NUM_L1_CL_OPERATIONS" offset="89" />
|
||||
<event name="MaliTexOutBt" title="Texture message write beats" description="The number of texture response message data beats." units="beats" counter="TEX_MSGO_NUM_FLITS" offset="43" />
|
||||
<event name="MaliTexOutBusUtil" title="Texture output bus utilization" description="The percentage load on the texture message output bus." units="percent" equation="((TEX_MSGO_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexOutMsg" title="Texture messages" description="The number of output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_MSG" offset="42" />
|
||||
<event name="MaliTexOutSingleMsg" title="Texture messages with single quad" description="The number of single quad output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_SINGLE_QUAD_MSG" offset="91" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" equation="((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(((TEX_MSGO_NUM_MSG) * 2) - (TEX_MSGO_NUM_SINGLE_QUAD_MSG)) * 4" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="((max((TEX_FILT_NUM_OPERATIONS), (TEX_TFCH_NUM_TCL_OPERATIONS), (TEX_CFCH_NUM_DIRECT_PATH_OPERATIONS), (TEX_CFCH_NUM_RP_OPERATIONS), (TEX_MSGI_NUM_FLITS), (TEX_MSGO_NUM_FLITS), (TEX_CFCH_NUM_L1_CL_OPERATIONS), (TEX_CFCH_NUM_L1_CT_OPERATIONS), (TEX_TIDX_NUM_OPERATIONS))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (4)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (4)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (4)) + ((VARY_SLOT_16) / (4))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceCullPrim" title="Facing test culled primitives" description="The number of primitives that are culled by facing tests." units="primitives" counter="PRIM_FACE_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceCullRate" title="Facing plane test cull percentage" description="The percentage of primitives culled by the facing test." units="percent" equation="((PRIM_FACE_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED) - (PRIM_SCISSOR_CULLED))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPlaneCullPrim" title="Frustum test culled primitives" description="The number of primitives that are culled by frustum tests." units="primitives" counter="PRIM_FRUSTUM_CULLED" offset="13" />
|
||||
<event name="MaliGeomPlaneCullRate" title="Frustum test cull percentage" description="The percentage of primitives culled by the frustum test." units="percent" equation="((PRIM_FRUSTUM_CULLED) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadPartTask" title="Partial tiler position shading requests" description="The number of partial position shading requests in the tiler geometry flow." units="requests" counter="POS_SHADER_PARTIAL_WARPS" offset="22" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (16)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (16)) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED) - (PRIM_SCISSOR_CULLED) - (PRIM_FACE_CULLED))) * 100" />
|
||||
<event name="MaliGeomScissorCullPrim" title="Scissor test culled primitives" description="The number of primitives that are culled by the scissor test." units="primitives" counter="PRIM_SCISSOR_CULLED" offset="70" />
|
||||
<event name="MaliGeomScissorCullRate" title="Scissor test cull percentage" description="The percentage of primitives culled by the scissor test." units="percent" equation="((PRIM_SCISSOR_CULLED) / ((((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)) - (PRIM_FRUSTUM_CULLED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadPartTask" title="Partial tiler varying shading requests" description="The number of partial varying shading requests in the tiler geometry flow." units="requests" counter="VAR_SHADER_PARTIAL_WARPS" offset="37" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="36" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (16)" />
|
||||
<event name="MaliGeomVisibleDVSPrim" title="Visible primitives using DVS" description="The number of primitives using DVS that are visible after culling." units="primitives" counter="PRIM_VISIBLE_DVS" offset="71" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_FACE_CULLED) + (PRIM_FRUSTUM_CULLED) + (PRIM_SAT_CULLED) + (PRIM_SCISSOR_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerPrimAsPosShadStallCy" title="Primitive assembly position shading stall cycles" description="The number of cycles when primitive assembly is waiting for position shading." units="cycles" counter="PRIMASSY_POS_SHADER_WAIT" offset="64" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
</category>
|
||||
</metrics>
|
||||
251
src/panfrost/perf/generated/G76.xml
Normal file
251
src/panfrost/perf/generated/G76.xml
Normal file
|
|
@ -0,0 +1,251 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G76">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="(EXEC_INSTR_COUNT)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="(((EXEC_INSTR_COUNT)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="29" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / (EXEC_INSTR_COUNT)) * 100" />
|
||||
<event name="MaliEngInstr" title="Arithmetic instruction issue cycles" description="The number of instructions run per warp." units="instructions" counter="EXEC_INSTR_COUNT" offset="28" />
|
||||
<event name="MaliEngStarveCy" title="Execution engine starvation cycles" description="The number of cycles when no new threads are available to run." units="cycles" counter="EXEC_INSTR_STARVING" offset="30" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (8)) / 4)" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (8)) / 4)) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (8)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragPartWarp" title="Partial fragment warps" description="The number of fragment warps containing helper threads that do not correspond to a hit sample point." units="warps" counter="FRAG_PARTIAL_WARPS" offset="10" />
|
||||
<event name="MaliFragPartWarpRate" title="Partial coverage percentage" description="The percentage of warps that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_WARPS) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (8)) / 4" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (8)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (8))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (8)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (8))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / ((TEX_MSGI_NUM_QUADS) * 4)" />
|
||||
<event name="MaliTexCacheCompressFetch" title="Compressed texture line fetch requests" description="The number of texture line fetches from the L2 cache that are block compressed textures." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED" offset="41" />
|
||||
<event name="MaliTexCacheCompressFetchRate" title="Texture data fetches from compressed lines" description="The percentage of texture line fetches that are from block compressed textures." units="percent" equation="((TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED) / (TEX_TFCH_NUM_LINES_FETCHED)) * 100" />
|
||||
<event name="MaliTexCacheFetch" title="Texture line fetch requests" description="The number of texture line fetches from the L2 cache." units="issues" counter="TEX_TFCH_NUM_LINES_FETCHED" offset="40" />
|
||||
<event name="MaliTexCacheLookup" title="Texture cache lookup requests" description="The number of texture cache lookup cycles." units="requests" counter="TEX_TFCH_NUM_OPERATIONS" offset="42" />
|
||||
<event name="MaliTexCacheUtil" title="Texture unit cache utilization" description="The percentage utilization of the texturing unit cache lookup path." units="percent" equation="((TEX_TFCH_NUM_OPERATIONS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="43" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexMipInstrRate" title="Texture accesses using mipmapping percentage" description="The percentage of texture operations accessing mipmapped textures." units="percent" equation="((TEX_DFCH_NUM_PASSES_MIP_MAP) / (TEX_DFCH_NUM_PASSES)) * 100" />
|
||||
<event name="MaliTexQuadPass" title="Texture quad issues" description="The number of quad-width filtering passes." units="issues" counter="TEX_DFCH_NUM_PASSES" offset="36" />
|
||||
<event name="MaliTexQuadPassDescMiss" title="Texture quad descriptor misses" description="The number of quad-width filtering passes that miss in the resource or sampler descriptor cache." units="requests" counter="TEX_DFCH_NUM_PASSES_MISS" offset="37" />
|
||||
<event name="MaliTexQuadPassMip" title="Mipmapped texture quad issues" description="The number of quad-width filtering passes that use a mipmapped texture." units="issues" counter="TEX_DFCH_NUM_PASSES_MIP_MAP" offset="38" />
|
||||
<event name="MaliTexQuadPassTri" title="Trilinear filtered texture quad issues" description="The number of quad-width filtering passes that use a trilinear filter." units="issues" counter="TEX_TIDX_NUM_SPLIT_MIP_MAP" offset="39" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" counter="TEX_MSGI_NUM_QUADS" offset="35" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="(TEX_MSGI_NUM_QUADS) * 4" />
|
||||
<event name="MaliTexTriInstrRate" title="Texture accesses using trilinear filter percentage" description="The percentage of texture operations using trilinear filtering." units="percent" equation="((TEX_TIDX_NUM_SPLIT_MIP_MAP) / (TEX_MSGI_NUM_QUADS)) * 100" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
<event name="MaliTilerWrBt" title="Internal write beats" description="The number of internal bus data write cycles made by the tiler." units="beats" counter="BUS_WRITE" offset="19" />
|
||||
</category>
|
||||
</metrics>
|
||||
259
src/panfrost/perf/generated/G77.xml
Normal file
259
src/panfrost/perf/generated/G77.xml
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G77">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="max((EXEC_INSTR_FMA), (EXEC_INSTR_CVT), (EXEC_INSTR_SFU) * 4)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="((max((EXEC_INSTR_FMA), (EXEC_INSTR_CVT), (EXEC_INSTR_SFU) * 4)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliEngArithInstr" title="Arithmetic instruction issue cycles" description="The total number of instructions issued to the FMA, CVT, and SFU pipes." units="instructions" equation="(EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)" />
|
||||
<event name="MaliEngCVTInstr" title="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions" counter="EXEC_INSTR_CVT" offset="28" />
|
||||
<event name="MaliEngCVTPipeUtil" title="CVT pipe utilization" description="Defines the utilization of the CVT pipe." units="percent" equation="((EXEC_INSTR_CVT) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="31" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngFMAInstr" title="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions" counter="EXEC_INSTR_FMA" offset="27" />
|
||||
<event name="MaliEngFMAPipeUtil" title="FMA pipe utilization" description="The utilization of the FMA pipe." units="percent" equation="((EXEC_INSTR_FMA) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngICacheMiss" title="Instruction cache misses" description="The number of instruction cache misses." units="requests" counter="EXEC_ICACHE_MISS" offset="32" />
|
||||
<event name="MaliEngSFUInstr" title="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions" counter="EXEC_INSTR_SFU" offset="29" />
|
||||
<event name="MaliEngSFUPipeUtil" title="SFU pipe utilization" description="The utilization of the SFU pipe." units="percent" equation="(((EXEC_INSTR_SFU) * 4) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSWBlendInstr" title="Blend shader instructions" description="The number of blend shader invocations run." units="instructions" counter="CALL_BLEND_SHADER" offset="34" />
|
||||
<event name="MaliEngSWBlendRate" title="Shader blend percentage" description="The percentage of fragments that use shader-based blending." units="percent" equation="(((CALL_BLEND_SHADER) * 2) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliEngStarveCy" title="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles" counter="EXEC_STARVE_ARITH" offset="33" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragRastPartQd" title="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads" counter="FRAG_PARTIAL_QUADS_RAST" offset="10" />
|
||||
<event name="MaliFragRastPartQdRate" title="Partial coverage percentage" description="The percentage of rasterized fine quads that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_QUADS_RAST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES_OUT" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (16)) / 4" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (16)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (16))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (16)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (16))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / (((TEX_MSGO_NUM_MSG)) * 4)" />
|
||||
<event name="MaliTexDataFetchStallCy" title="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles" counter="TEX_TFCH_CLK_STALLED" offset="37" />
|
||||
<event name="MaliTexDescStallCy" title="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles" counter="TEX_DFCH_CLK_STALLED" offset="36" />
|
||||
<event name="MaliTexFiltFullRate" title="Texture full speed filtering percentage" description="The percentage of texture filtering cycles using the full width of the texture filtering data path." units="percent" equation="(((TEX_FILT_NUM_FXR_OPERATIONS) + (TEX_FILT_NUM_FST_OPERATIONS)) / (TEX_FILT_NUM_OPERATIONS)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="39" />
|
||||
<event name="MaliTexFiltStallCy" title="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" offset="38" />
|
||||
<event name="MaliTexFullBiFiltCy" title="Texture filtering cycles using full bilinear" description="The number of cycles when the filtering unit is filled with bilinear filtering." units="cycles" counter="TEX_FILT_NUM_FXR_OPERATIONS" offset="40" />
|
||||
<event name="MaliTexFullTriFiltCy" title="Texture filtering cycles using full trilinear" description="The number of cycles when the filtering unit is filled with trilinear filtering." units="cycles" counter="TEX_FILT_NUM_FST_OPERATIONS" offset="41" />
|
||||
<event name="MaliTexInBt" title="Texture message read beats" description="The number of texture request message data beats." units="beats" counter="TEX_MSGI_NUM_FLITS" offset="35" />
|
||||
<event name="MaliTexInBusUtil" title="Texture input bus utilization" description="The percentage load on the texture message input bus." units="percent" equation="((TEX_MSGI_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexOutBt" title="Texture message write beats" description="The number of texture response message data beats." units="beats" counter="TEX_MSGO_NUM_FLITS" offset="43" />
|
||||
<event name="MaliTexOutBusUtil" title="Texture output bus utilization" description="The percentage load on the texture message output bus." units="percent" equation="((TEX_MSGO_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexOutMsg" title="Texture messages" description="The number of output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_MSG" offset="42" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" equation="(TEX_MSGO_NUM_MSG)" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="((TEX_MSGO_NUM_MSG)) * 4" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
</category>
|
||||
</metrics>
|
||||
261
src/panfrost/perf/generated/G78.xml
Normal file
261
src/panfrost/perf/generated/G78.xml
Normal file
|
|
@ -0,0 +1,261 @@
|
|||
<!--
|
||||
Copyright (c) 2026 Arm, Ltd.
|
||||
SPDX-License-Identifier: MIT
|
||||
|
||||
Generated from libGPUCounters @ 4ea7c0127fe2942a00e4a1123bb62c625a401f93.
|
||||
https://github.com/ARM-software/libGPUCounters
|
||||
which is:
|
||||
Copyright (c) 2023-2025 Arm Limited
|
||||
SPDX-License-Identifier: MIT
|
||||
-->
|
||||
|
||||
<metrics id="G78">
|
||||
<category name="GPU Front-end">
|
||||
<event name="MaliFragQueueActiveCy" title="Fragment queue active cycles" description="The number of cycles when work is queued for processing in the GPU fragment queue." units="cycles" counter="JS0_ACTIVE" offset="10" />
|
||||
<event name="MaliFragQueueJob" title="Fragment jobs" description="The number of jobs processed by the GPU fragment queue." units="jobs" counter="JS0_JOBS" offset="8" />
|
||||
<event name="MaliFragQueueTask" title="Fragment tasks" description="The number of fragment tasks processed." units="tasks" counter="JS0_TASKS" offset="9" />
|
||||
<event name="MaliFragQueueUtil" title="Fragment queue utilization" description="The fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS0_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliFragQueueWaitDepCy" title="Fragment queue job dependency wait cycles" description="The number of cycles when queued fragment work is waiting for dependent work to complete." units="cycles" counter="JS0_WAIT_DEPEND" offset="14" />
|
||||
<event name="MaliFragQueueWaitFinishCy" title="Fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued fragment work to complete." units="cycles" counter="JS0_WAIT_FINISH" offset="15" />
|
||||
<event name="MaliFragQueueWaitFlushCy" title="Fragment queue cache flush wait cycles" description="The number of cycles when queued fragment work is waiting for a cache flush." units="cycles" counter="JS0_WAIT_FLUSH" offset="11" />
|
||||
<event name="MaliFragQueueWaitIssueCy" title="Fragment queue job issue wait cycles" description="The number of cycles when queued fragment work is waiting for an available processor." units="cycles" counter="JS0_WAIT_ISSUE" offset="13" />
|
||||
<event name="MaliFragQueueWaitRdCy" title="Fragment queue job descriptor read wait cycles" description="The number of cycles when queued fragment work is waiting for a descriptor load." units="cycles" counter="JS0_WAIT_READ" offset="12" />
|
||||
<event name="MaliGPUActiveCy" title="GPU active cycles" description="The number of cycles when the GPU has a workload of any type queued for processing." units="cycles" counter="GPU_ACTIVE" offset="6" />
|
||||
<event name="MaliGPUIRQActiveCy" title="GPU interrupt pending cycles" description="The number of cycles when the GPU has a pending interrupt." units="cycles" counter="IRQ_ACTIVE" offset="7" />
|
||||
<event name="MaliGPUIRQUtil" title="Interrupt pending utilization" description="The IRQ pending utilization compared against the GPU active cycles." units="percent" equation="((IRQ_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueActiveCy" title="Non-fragment queue active cycles" description="The number of cycles when work is queued in the GPU non-fragment queue." units="cycles" counter="JS1_ACTIVE" offset="18" />
|
||||
<event name="MaliNonFragQueueJob" title="Non-fragment jobs" description="The number of jobs processed by the GPU non-fragment queue." units="jobs" counter="JS1_JOBS" offset="16" />
|
||||
<event name="MaliNonFragQueueTask" title="Non-fragment tasks" description="The number of non-fragment tasks processed." units="tasks" counter="JS1_TASKS" offset="17" />
|
||||
<event name="MaliNonFragQueueUtil" title="Non-fragment queue utilization" description="The non-fragment queue utilization compared against the GPU active cycles." units="percent" equation="((JS1_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragQueueWaitDepCy" title="Non-fragment queue job dependency wait cycles" description="The number of cycles when queued non-fragment work is waiting for dependent work to complete." units="cycles" counter="JS1_WAIT_DEPEND" offset="22" />
|
||||
<event name="MaliNonFragQueueWaitFinishCy" title="Non-fragment queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued non-fragment work to complete." units="cycles" counter="JS1_WAIT_FINISH" offset="23" />
|
||||
<event name="MaliNonFragQueueWaitFlushCy" title="Non-fragment queue cache flush wait cycles" description="The number of cycles when queued non-fragment work is waiting for a cache flush." units="cycles" counter="JS1_WAIT_FLUSH" offset="19" />
|
||||
<event name="MaliNonFragQueueWaitIssueCy" title="Non-fragment queue job issue wait cycles" description="The number of cycles when queued non-fragment work is waiting for an available processor." units="cycles" counter="JS1_WAIT_ISSUE" offset="21" />
|
||||
<event name="MaliNonFragQueueWaitRdCy" title="Non-fragment queue job descriptor read wait cycles" description="The number number of cycles when queued non-fragment work is waiting for a descriptor load." units="cycles" counter="JS1_WAIT_READ" offset="20" />
|
||||
<event name="MaliResQueueActiveCy" title="Reserved active cycles" description="The number of cycles when work is queued in the GPU reserved queue." units="cycles" counter="JS2_ACTIVE" offset="26" />
|
||||
<event name="MaliResQueueJob" title="Reserved queue jobs" description="The number of jobs processed by the GPU reserved queue." units="jobs" counter="JS2_JOBS" offset="24" />
|
||||
<event name="MaliResQueueTask" title="Reserved queue tasks" description="The number of reserved tasks processed." units="tasks" counter="JS2_TASKS" offset="25" />
|
||||
<event name="MaliResQueueWaitDepCy" title="Reserved queue job dependency wait cycles" description="The number of cycles when queued reserved work is waiting for dependent work to complete." units="cycles" counter="JS2_WAIT_DEPEND" offset="30" />
|
||||
<event name="MaliResQueueWaitFinishCy" title="Reserved queue job finish wait cycles" description="The number of cycles when the GPU is waiting for issued reserved work to complete." units="cycles" counter="JS2_WAIT_FINISH" offset="31" />
|
||||
<event name="MaliResQueueWaitFlushCy" title="Reserved queue cache flush wait cycles" description="The number of cycles when queued reserved work is waiting for a cache flush." units="cycles" counter="JS2_WAIT_FLUSH" offset="27" />
|
||||
<event name="MaliResQueueWaitIssueCy" title="Reserved queue job issue wait cycles" description="The number of cycles when queued reserved work is waiting for an available processor." units="cycles" counter="JS2_WAIT_ISSUE" offset="29" />
|
||||
<event name="MaliResQueueWaitRdCy" title="Reserved queue job descriptor read wait cycles" description="The number of cycles when queued reserved work is waiting for a descriptor load." units="cycles" counter="JS2_WAIT_READ" offset="28" />
|
||||
</category>
|
||||
<category name="Memory System">
|
||||
<event name="MaliExtBusRd" title="Output external read transactions" description="The number of external read transactions." units="transactions" counter="L2_EXT_READ" offset="29" />
|
||||
<event name="MaliExtBusRdBt" title="Output external read beats" description="The number of external bus data read cycles." units="beats" counter="L2_EXT_READ_BEATS" offset="32" />
|
||||
<event name="MaliExtBusRdBy" title="Output external read bytes" description="The total output read bandwidth for the GPU." units="bytes" equation="(L2_EXT_READ_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusRdLat0" title="Output external read latency 0-127 cycles" description="The number of data beats returned 0-127 cycles after the read request." units="beats" counter="L2_EXT_RRESP_0_127" offset="37" />
|
||||
<event name="MaliExtBusRdLat128" title="Output external read latency 128-191 cycles" description="The number of data beats returned 128-191 cycles after the read request." units="beats" counter="L2_EXT_RRESP_128_191" offset="38" />
|
||||
<event name="MaliExtBusRdLat192" title="Output external read latency 192-255 cycles" description="The number of data beats returned 192-255 cycles after the read request." units="beats" counter="L2_EXT_RRESP_192_255" offset="39" />
|
||||
<event name="MaliExtBusRdLat256" title="Output external read latency 256-319 cycles" description="The number of data beats returned 256-319 cycles after the read request." units="beats" counter="L2_EXT_RRESP_256_319" offset="40" />
|
||||
<event name="MaliExtBusRdLat320" title="Output external read latency 320-383 cycles" description="The number of data beats returned 320-383 cycles after the read request." units="beats" counter="L2_EXT_RRESP_320_383" offset="41" />
|
||||
<event name="MaliExtBusRdLat384" title="Output external read latency 384+ cycles" description="The number of read beats that are returned at least 384 cycles after the transaction started." units="beats" equation="(L2_EXT_READ_BEATS) - (L2_EXT_RRESP_0_127) - (L2_EXT_RRESP_128_191) - (L2_EXT_RRESP_192_255) - (L2_EXT_RRESP_256_319) - (L2_EXT_RRESP_320_383)" />
|
||||
<event name="MaliExtBusRdNoSnoop" title="Output external ReadNoSnoop transactions" description="The number of external non-coherent read transactions." units="transactions" counter="L2_EXT_READ_NOSNP" offset="30" />
|
||||
<event name="MaliExtBusRdOTQ1" title="Output external outstanding reads 0-25%" description="The number of read transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q1" offset="34" />
|
||||
<event name="MaliExtBusRdOTQ2" title="Output external outstanding reads 25-50%" description="The number of read transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q2" offset="35" />
|
||||
<event name="MaliExtBusRdOTQ3" title="Output external outstanding reads 50-75%" description="The number of read transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AR_CNT_Q3" offset="36" />
|
||||
<event name="MaliExtBusRdOTQ4" title="Output external outstanding reads 75-100%" description="The number of read transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_READ) - (L2_EXT_AR_CNT_Q1) - (L2_EXT_AR_CNT_Q2) - (L2_EXT_AR_CNT_Q3)" />
|
||||
<event name="MaliExtBusRdStallCy" title="Output external read stall cycles" description="The number of cycles when a read is stalled waiting for the external bus." units="cycles" counter="L2_EXT_AR_STALL" offset="33" />
|
||||
<event name="MaliExtBusRdStallRate" title="Output external read stall percentage" description="The percentage of cycles with an external read transaction stalled." units="percent" equation="((L2_EXT_AR_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliExtBusRdUnique" title="Output external ReadUnique transactions" description="The number of external coherent read unique transactions." units="transactions" counter="L2_EXT_READ_UNIQUE" offset="31" />
|
||||
<event name="MaliExtBusWr" title="Output external write transactions" description="The number of external write transactions." units="transactions" counter="L2_EXT_WRITE" offset="42" />
|
||||
<event name="MaliExtBusWrBt" title="Output external write beats" description="The number of external bus data write cycles." units="beats" counter="L2_EXT_WRITE_BEATS" offset="47" />
|
||||
<event name="MaliExtBusWrBy" title="Output external write bytes" description="The total output write bandwidth for the GPU." units="bytes" equation="(L2_EXT_WRITE_BEATS) * (MALI_CONFIG_EXT_BUS_BYTE_SIZE)" />
|
||||
<event name="MaliExtBusWrNoSnoopFull" title="Output external WriteNoSnoopFull transactions" description="The number of external non-coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_FULL" offset="43" />
|
||||
<event name="MaliExtBusWrNoSnoopPart" title="Output external WriteNoSnoopPartial transactions" description="The number of external non-coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_NOSNP_PTL" offset="44" />
|
||||
<event name="MaliExtBusWrOTQ1" title="Output external outstanding writes 0-25%" description="The number of write transactions initiated when 0-25% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q1" offset="49" />
|
||||
<event name="MaliExtBusWrOTQ2" title="Output external outstanding writes 25-50%" description="The number of write transactions initiated when 25-50% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q2" offset="50" />
|
||||
<event name="MaliExtBusWrOTQ3" title="Output external outstanding writes 50-75%" description="The number of write transactions initiated when 50-75% of the maximum are in use." units="transactions" counter="L2_EXT_AW_CNT_Q3" offset="51" />
|
||||
<event name="MaliExtBusWrOTQ4" title="Output external outstanding writes 75-100%" description="The number of write transactions initiated when 75-100% of transaction IDs are in use." units="transactions" equation="(L2_EXT_WRITE) - (L2_EXT_AW_CNT_Q1) - (L2_EXT_AW_CNT_Q2) - (L2_EXT_AW_CNT_Q3)" />
|
||||
<event name="MaliExtBusWrSnoopFull" title="Output external WriteSnoopFull transactions" description="The number of external coherent full write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_FULL" offset="45" />
|
||||
<event name="MaliExtBusWrSnoopPart" title="Output external WriteSnoopPartial transactions" description="The number of external coherent partial write transactions." units="transactions" counter="L2_EXT_WRITE_SNP_PTL" offset="46" />
|
||||
<event name="MaliExtBusWrStallCy" title="Output external write stall cycles" description="The number of cycles when a write is stalled waiting for the external bus." units="cycles" counter="L2_EXT_W_STALL" offset="48" />
|
||||
<event name="MaliExtBusWrStallRate" title="Output external write stall percentage" description="The percentage of cycles with an external write transaction stalled." units="percent" equation="((L2_EXT_W_STALL) / (MALI_CONFIG_L2_CACHE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliL2CacheFlush" title="L2 cache flush requests" description="The number of GPU L2 cache flushes performed." units="requests" counter="CACHE_FLUSH" offset="63" />
|
||||
<event name="MaliL2CacheIncSnp" title="Input external snoop transactions" description="The number of coherency snoops triggered by external requesters." units="transactions" counter="L2_EXT_SNOOP" offset="52" />
|
||||
<event name="MaliL2CacheIncSnpStallCy" title="Input external snoop stall cycles" description="The number of cycles when a coherency snoop triggered by external requester is stalled." units="cycles" counter="L2_EXT_SNOOP_STALL" offset="53" />
|
||||
<event name="MaliL2CacheL1Rd" title="Output internal read requests" description="The number of L1 cache read requests sent by the L2 cache to an internal requester." units="requests" counter="L2_RD_MSG_OUT" offset="22" />
|
||||
<event name="MaliL2CacheL1RdStallCy" title="Output internal read stall cycles" description="The number of cycles when L1 cache read requests sent by the L2 cache to an internal requester are stalled." units="cycles" counter="L2_RD_MSG_OUT_STALL" offset="23" />
|
||||
<event name="MaliL2CacheL1Wr" title="Output internal write requests" description="The number of L1 cache write responses sent by the L2 cache to an internal requester." units="requests" counter="L2_WR_MSG_OUT" offset="24" />
|
||||
<event name="MaliL2CacheLookup" title="Any lookup requests" description="The number of L2 cache lookups performed." units="requests" counter="L2_ANY_LOOKUP" offset="25" />
|
||||
<event name="MaliL2CacheRd" title="Input internal read requests" description="The number of L2 cache read requests from internal requesters." units="requests" counter="L2_RD_MSG_IN" offset="16" />
|
||||
<event name="MaliL2CacheRdLookup" title="Read lookup requests" description="The number of L2 cache read lookups performed." units="requests" counter="L2_READ_LOOKUP" offset="26" />
|
||||
<event name="MaliL2CacheRdMissRate" title="L2 cache read miss percentage" description="The percentage of internal L2 cache reads that result in an external read." units="percent" equation="((L2_EXT_READ) / (L2_READ_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheRdStallCy" title="Input internal read stall cycles" description="The number of cycles L2 cache read requests from internal requesters are stalled." units="cycles" counter="L2_RD_MSG_IN_STALL" offset="17" />
|
||||
<event name="MaliL2CacheSnp" title="Input internal snoop requests" description="The number of L2 snoop requests from internal requesters." units="requests" counter="L2_SNP_MSG_IN" offset="20" />
|
||||
<event name="MaliL2CacheSnpLookup" title="Input external snoop lookup requests" description="The number of coherency snoop lookups performed that were triggered by an external requester." units="requests" counter="L2_EXT_SNOOP_LOOKUP" offset="28" />
|
||||
<event name="MaliL2CacheSnpStallCy" title="Input internal snoop stall cycles" description="The number of cycles when L2 cache snoop requests from internal requesters are stalled." units="cycles" counter="L2_SNP_MSG_IN_STALL" offset="21" />
|
||||
<event name="MaliL2CacheWr" title="Input internal write requests" description="The number of L2 cache write requests from internal requesters." units="requests" counter="L2_WR_MSG_IN" offset="18" />
|
||||
<event name="MaliL2CacheWrLookup" title="Write lookup requests" description="The number of L2 cache write lookups performed." units="requests" counter="L2_WRITE_LOOKUP" offset="27" />
|
||||
<event name="MaliL2CacheWrMissRate" title="L2 cache write miss percentage" description="The percentage of internal L2 cache writes that result in an external write." units="percent" equation="((L2_EXT_WRITE) / (L2_WRITE_LOOKUP)) * 100" />
|
||||
<event name="MaliL2CacheWrStallCy" title="Input internal write stall cycles" description="The number of cycles when L2 cache write requests from internal requesters are stalled." units="cycles" counter="L2_WR_MSG_IN_STALL" offset="19" />
|
||||
<event name="MaliMMUL2Hit" title="MMU L2 lookup TLB hits" description="The number of level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L2" offset="8" />
|
||||
<event name="MaliMMUL2Rd" title="MMU L2 table read requests" description="The number of level 2 translation table reads." units="requests" counter="MMU_TABLE_READS_L2" offset="6" />
|
||||
<event name="MaliMMUL3Hit" title="MMU L3 lookup TLB hits" description="The number of level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_HIT_L3" offset="7" />
|
||||
<event name="MaliMMUL3Rd" title="MMU L3 table read requests" description="The number of level 3 translation table reads." units="requests" counter="MMU_TABLE_READS_L3" offset="5" />
|
||||
<event name="MaliMMULookup" title="MMU lookup requests" description="The number of main MMU address translations performed." units="requests" counter="MMU_REQUESTS" offset="4" />
|
||||
<event name="MaliMMUS2L2Hit" title="MMU stage 2 L2 lookup TLB hits" description="The number of stage 2 level 2 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L2" offset="13" />
|
||||
<event name="MaliMMUS2L2Rd" title="MMU stage 2 L2 lookup requests" description="The number of stage 2 level 2 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L2" offset="11" />
|
||||
<event name="MaliMMUS2L3Hit" title="MMU stage 2 L3 lookup TLB hits" description="The number of stage 2 level 3 translation table reads that hit in the main MMU TLB." units="requests" counter="MMU_S2_HIT_L3" offset="12" />
|
||||
<event name="MaliMMUS2L3Rd" title="MMU stage 2 L3 lookup requests" description="The number of stage 2 level 3 translation table reads." units="requests" counter="MMU_S2_TABLE_READS_L3" offset="10" />
|
||||
<event name="MaliMMUS2Lookup" title="MMU stage 2 lookup requests" description="The number of main MMU stage 2 address translations performed." units="requests" counter="MMU_S2_REQUESTS" offset="9" />
|
||||
</category>
|
||||
<category name="Shader Core">
|
||||
<event name="MaliALUIssueCy" title="Arithmetic unit issue cycles" description="The number of cycles the arithmetic unit was busy." units="cycles" equation="max((EXEC_INSTR_FMA), (EXEC_INSTR_CVT), (EXEC_INSTR_SFU) * 4)" />
|
||||
<event name="MaliALUUtil" title="Arithmetic unit utilization" description="The percentage utilization of the arithmetic unit." units="percent" equation="((max((EXEC_INSTR_FMA), (EXEC_INSTR_CVT), (EXEC_INSTR_SFU) * 4)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliAnyActiveCy" title="Any workload active cycles" description="The number of cycles when the shader core is processing either a non-fragment workload or a fragment workload." units="cycles" counter="SHADER_CORE_ACTIVE" offset="53" />
|
||||
<event name="MaliAnyUtil" title="Shader core clock ratio" description="An estimate of shader core use relative to the GPU top-level clock." units="percent" equation="((SHADER_CORE_ACTIVE) / (MALI_CONFIG_SHADER_CORE_COUNT) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliAttrInstr" title="Attribute instructions" description="The number of instructions run by the attribute unit." units="instructions" counter="ATTR_INSTR" offset="52" />
|
||||
<event name="MaliCoreActiveCy" title="Execution core active cycles" description="The number of cycles when the shader core is processing at least one warp." units="cycles" counter="EXEC_CORE_ACTIVE" offset="26" />
|
||||
<event name="MaliCoreAllRegsWarp" title="Warps using more than 32 registers" description="The number of warps that require more than 32 registers." units="warps" counter="WARP_REG_SIZE_64" offset="17" />
|
||||
<event name="MaliCoreAllRegsWarpRate" title="All registers warp percentage" description="The percentage of warps that require more than 32 registers." units="percent" equation="((WARP_REG_SIZE_64) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreFullWarp" title="Full warps" description="The number of warps that have a full thread slot allocation." units="warps" counter="FULL_QUAD_WARPS" offset="21" />
|
||||
<event name="MaliCoreFullWarpRate" title="Full warp percentage" description="The percentage of warps that have a full thread slot allocation." units="percent" equation="((FULL_QUAD_WARPS) / ((COMPUTE_WARPS) + (FRAG_WARPS))) * 100" />
|
||||
<event name="MaliCoreUtil" title="Execution core utilization" description="The utilization of the programmable shader core." units="percent" equation="((EXEC_CORE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngArithInstr" title="Arithmetic instruction issue cycles" description="The total number of instructions issued to the FMA, CVT, and SFU pipes." units="instructions" equation="(EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU)" />
|
||||
<event name="MaliEngCVTInstr" title="Arithmetic CVT pipe instructions" description="The number of instructions issued to the CVT pipe." units="instructions" counter="EXEC_INSTR_CVT" offset="28" />
|
||||
<event name="MaliEngCVTPipeUtil" title="CVT pipe utilization" description="Defines the utilization of the CVT pipe." units="percent" equation="((EXEC_INSTR_CVT) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngDivergedInstr" title="Diverged instructions" description="The number of instructions run per warp that have control flow divergence." units="instructions" counter="EXEC_INSTR_DIVERGED" offset="31" />
|
||||
<event name="MaliEngDivergedInstrRate" title="Warp divergence percentage" description="The percentage of instructions that have control flow divergence across the warp." units="percent" equation="((EXEC_INSTR_DIVERGED) / ((EXEC_INSTR_FMA) + (EXEC_INSTR_CVT) + (EXEC_INSTR_SFU))) * 100" />
|
||||
<event name="MaliEngFMAInstr" title="Arithmetic FMA pipe instructions" description="The number of instructions issued to the FMA pipe." units="instructions" counter="EXEC_INSTR_FMA" offset="27" />
|
||||
<event name="MaliEngFMAPipeUtil" title="FMA pipe utilization" description="The utilization of the FMA pipe." units="percent" equation="((EXEC_INSTR_FMA) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngICacheMiss" title="Instruction cache misses" description="The number of instruction cache misses." units="requests" counter="EXEC_ICACHE_MISS" offset="32" />
|
||||
<event name="MaliEngSFUInstr" title="Arithmetic SFU pipe instructions" description="The number of instructions issued to the SFU pipe." units="instructions" counter="EXEC_INSTR_SFU" offset="29" />
|
||||
<event name="MaliEngSFUPipeUtil" title="SFU pipe utilization" description="The utilization of the SFU pipe." units="percent" equation="(((EXEC_INSTR_SFU) * 4) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliEngSWBlendInstr" title="Blend shader instructions" description="The number of blend shader invocations run." units="instructions" counter="CALL_BLEND_SHADER" offset="34" />
|
||||
<event name="MaliEngSWBlendRate" title="Shader blend percentage" description="The percentage of fragments that use shader-based blending." units="percent" equation="(((CALL_BLEND_SHADER) * 2) / (FRAG_WARPS)) * 100" />
|
||||
<event name="MaliEngStarveCy" title="Processing unit starvation cycles" description="The number of cycles when the processing unit is starved of work." units="cycles" counter="EXEC_STARVE_ARITH" offset="33" />
|
||||
<event name="MaliFragActiveCy" title="Fragment active cycles" description="The number of cycles when the shader core is processing a fragment workload." units="cycles" counter="FRAG_ACTIVE" offset="4" />
|
||||
<event name="MaliFragEZSKillQd" title="Early ZS killed quads" description="The number of quads killed by early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_KILL" offset="14" />
|
||||
<event name="MaliFragEZSKillRate" title="Early ZS killed quad percentage" description="The percentage of rasterized quads that are killed by early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSTestQd" title="Early ZS tested quads" description="The number of quads that are undergoing early depth and stencil testing." units="quads" counter="FRAG_QUADS_EZS_TEST" offset="12" />
|
||||
<event name="MaliFragEZSTestRate" title="Early ZS tested quad percentage" description="The percentage of rasterized quads that were subjected to early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragEZSUpdateQd" title="Early ZS updated quads" description="The number of quads undergoing early depth and stencil testing, that are capable of updating the framebuffer." units="quads" counter="FRAG_QUADS_EZS_UPDATE" offset="13" />
|
||||
<event name="MaliFragEZSUpdateRate" title="Early ZS updated quad percentage" description="The percentage of rasterized quads that update the framebuffer during early depth and stencil testing." units="percent" equation="((FRAG_QUADS_EZS_UPDATE) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragFPKActiveCy" title="Fragment pre-pipe buffer active cycles" description="The number of cycles when at least one quad is present in the pre-pipe quad queue." units="cycles" counter="FRAG_FPK_ACTIVE" offset="7" />
|
||||
<event name="MaliFragFPKBUtil" title="Fragment pre-pipe buffer utilization" description="The percentage of cycles when at least one quad is buffered for fragment shading." units="percent" equation="((FRAG_FPK_ACTIVE) / (FRAG_ACTIVE)) * 100" />
|
||||
<event name="MaliFragFPKKillQd" title="FPK HSR killed quads" description="The number of quads that are killed by hidden surface removal." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)" />
|
||||
<event name="MaliFragFPKKillRate" title="FPK HSR killed quad percentage" description="The percentage of rasterized quads that are killed by hidden surface removal." units="percent" equation="(((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (((FRAG_WARPS) * (16)) / 4)) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSKillQd" title="Late ZS killed quads" description="The number of quads killed by late depth and stencil testing." units="quads" counter="FRAG_LZS_KILL" offset="16" />
|
||||
<event name="MaliFragLZSKillRate" title="Late ZS killed quad percentage" description="The percentage of rasterized quads that are killed by late depth and stencil testing." units="percent" equation="((FRAG_LZS_KILL) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragLZSTestQd" title="Late ZS tested quads" description="The number of quads undergoing late depth and stencil testing." units="quads" counter="FRAG_LZS_TEST" offset="15" />
|
||||
<event name="MaliFragLZSTestRate" title="Late ZS tested quad percentage" description="The percentage of rasterized quads that are tested by late depth and stencil testing." units="percent" equation="((FRAG_LZS_TEST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragOpaqueQd" title="Occluding quads" description="The number of quads that are valid occluders for hidden surface removal." units="quads" counter="QUAD_FPK_KILLER" offset="20" />
|
||||
<event name="MaliFragOpaqueQdRate" title="Occluding quad percentage" description="The percentage of quads that are valid occluders for hidden surface removal." units="percent" equation="((QUAD_FPK_KILLER) / ((FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL))) * 100" />
|
||||
<event name="MaliFragOverdraw" title="Fragments per pixel" description="The number of fragments shaded per output pixel." units="threads" equation="((FRAG_WARPS) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliFragRastPartQd" title="Partial rasterized fine quads" description="The number of rasterized fine quads created with partial coverage." units="quads" counter="FRAG_PARTIAL_QUADS_RAST" offset="10" />
|
||||
<event name="MaliFragRastPartQdRate" title="Partial coverage percentage" description="The percentage of rasterized fine quads that contain samples with no coverage." units="percent" equation="((FRAG_PARTIAL_QUADS_RAST) / (FRAG_QUADS_RAST)) * 100" />
|
||||
<event name="MaliFragRastPrim" title="Rasterized primitives" description="The number of primitives being rasterized." units="primitives" counter="FRAG_PRIM_RAST" offset="6" />
|
||||
<event name="MaliFragRastQd" title="Rasterized fine quads" description="The number of fine quads generated by the rasterization phase." units="quads" counter="FRAG_QUADS_RAST" offset="11" />
|
||||
<event name="MaliFragRdPrim" title="Fragment primitives loaded" description="The number of primitives loaded from the tile list by the fragment front-end." units="primitives" counter="FRAG_PRIMITIVES_OUT" offset="5" />
|
||||
<event name="MaliFragShadedQd" title="Shaded coarse quads" description="The number of 2x2 fragment quads that are fragment shaded." units="quads" equation="((FRAG_WARPS) * (16)) / 4" />
|
||||
<event name="MaliFragThread" title="Fragment threads" description="The number of fragment threads started." units="threads" equation="(FRAG_WARPS) * (16)" />
|
||||
<event name="MaliFragThroughputCy" title="Average cycles per fragment thread" description="The average number of shader core cycles per fragment thread." units="cycles" equation="(FRAG_ACTIVE) / ((FRAG_WARPS) * (16))" />
|
||||
<event name="MaliFragTile" title="Tiles" description="The number of tiles processed by the shader core." units="tiles" counter="FRAG_PTILES" offset="18" />
|
||||
<event name="MaliFragTileKill" title="Killed unchanged tiles" description="The number of tiles killed by transaction elimination." units="tiles" counter="FRAG_TRANS_ELIM" offset="19" />
|
||||
<event name="MaliFragTileKillRate" title="Unchanged tile kill percentage" description="The percentage of tiles that are killed by transaction elimination." units="percent" equation="((FRAG_TRANS_ELIM) / (FRAG_PTILES)) * 100" />
|
||||
<event name="MaliFragTransparentQd" title="Non-occluding quads" description="The number of quads that are not eligible to be a hidden surface removal occluder." units="quads" equation="(FRAG_QUADS_RAST) - (FRAG_QUADS_EZS_KILL) - (QUAD_FPK_KILLER)" />
|
||||
<event name="MaliFragUtil" title="Fragment utilization" description="The utilization of the shader core fragment path." units="percent" equation="((FRAG_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliFragWarp" title="Fragment warps" description="The number of fragment warps created." units="warps" counter="FRAG_WARPS" offset="9" />
|
||||
<event name="MaliLSAtomic" title="Load/store unit atomic issues" description="The number of load/store atomic accesses." units="cycles" counter="LS_MEM_ATOMIC" offset="48" />
|
||||
<event name="MaliLSFullRd" title="Load/store unit full read issues" description="The number of full-width load/store cache reads." units="cycles" counter="LS_MEM_READ_FULL" offset="44" />
|
||||
<event name="MaliLSFullWr" title="Load/store unit full write issues" description="The number of full-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_FULL" offset="46" />
|
||||
<event name="MaliLSIssueCy" title="Load/store unit issue cycles" description="The total number of load/store issue cycles." units="cycles" equation="((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)" />
|
||||
<event name="MaliLSPartRd" title="Load/store unit partial read issues" description="The number of partial-width load/store cache reads." units="cycles" counter="LS_MEM_READ_SHORT" offset="45" />
|
||||
<event name="MaliLSPartWr" title="Load/store unit partial write issues" description="The number of partial-width load/store cache writes." units="cycles" counter="LS_MEM_WRITE_SHORT" offset="47" />
|
||||
<event name="MaliLSRdCy" title="Load/store unit read issues" description="The total number of load/store read cycles." units="cycles" equation="(LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)" />
|
||||
<event name="MaliLSUtil" title="Load/store unit utilization" description="The percentage utilization of the load/store unit." units="percent" equation="((((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT)) + ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)) + (LS_MEM_ATOMIC)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliLSWrCy" title="Load/store unit write issues" description="The total number of load/store write cycles." units="cycles" equation="(LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT)" />
|
||||
<event name="MaliNonFragActiveCy" title="Non-fragment active cycles" description="The number of cycles when the shader core is processing some non-fragment workload." units="cycles" counter="COMPUTE_ACTIVE" offset="22" />
|
||||
<event name="MaliNonFragTask" title="Non-fragment core tasks" description="The number of non-fragment tasks issued to the shader core." units="tasks" counter="COMPUTE_TASKS" offset="23" />
|
||||
<event name="MaliNonFragThread" title="Non-fragment threads" description="The number of non-fragment threads started." units="threads" equation="(COMPUTE_WARPS) * (16)" />
|
||||
<event name="MaliNonFragThroughputCy" title="Average cycles per non-fragment thread" description="The average number of shader core cycles per non-fragment thread." units="cycles" equation="(COMPUTE_ACTIVE) / ((COMPUTE_WARPS) * (16))" />
|
||||
<event name="MaliNonFragUtil" title="Non-fragment utilization" description="The utilization of the shader core non-fragment path." units="percent" equation="((COMPUTE_ACTIVE) / (SHADER_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliNonFragWarp" title="Non-fragment warps" description="The number of non-fragment warps created." units="warps" counter="COMPUTE_WARPS" offset="24" />
|
||||
<event name="MaliSCBusFFEExtRdBt" title="Fragment front-end read beats from external memory" description="The number of read beats received by the fixed-function fragment front-end that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_FTC_EXT" offset="55" />
|
||||
<event name="MaliSCBusFFEExtRdBy" title="Fragment front-end read bytes from external memory" description="The total number of bytes read from the external memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC_EXT) * (16)" />
|
||||
<event name="MaliSCBusFFEL2RdBt" title="Fragment front-end read beats from L2 cache" description="The number of read beats received by the fixed-function fragment front-end." units="beats" counter="BEATS_RD_FTC" offset="54" />
|
||||
<event name="MaliSCBusFFEL2RdBy" title="Fragment front-end read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the shader core fragment front-end." units="bytes" equation="(BEATS_RD_FTC) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdBt" title="Load/store unit read beats from external memory" description="The number of read beats received by the load/store unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_LSC_EXT" offset="57" />
|
||||
<event name="MaliSCBusLSExtRdBy" title="Load/store unit read bytes from external memory" description="The total number of bytes read from the external memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC_EXT) * (16)" />
|
||||
<event name="MaliSCBusLSExtRdByPerRd" title="Load/store unit bytes read from external memory per access cycle" description="The average number of bytes read from the external memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC_EXT) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSL2RdBt" title="Load/store unit read beats from L2 cache" description="The number of read beats received by the load/store unit." units="beats" counter="BEATS_RD_LSC" offset="56" />
|
||||
<event name="MaliSCBusLSL2RdBy" title="Load/store unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the load/store unit." units="bytes" equation="(BEATS_RD_LSC) * (16)" />
|
||||
<event name="MaliSCBusLSL2RdByPerRd" title="Load/store unit bytes read from L2 per access cycle" description="The average number of bytes read from the L2 memory system by the load/store unit per read cycle." units="bytes" equation="((BEATS_RD_LSC) * (16)) / ((LS_MEM_READ_FULL) + (LS_MEM_READ_SHORT))" />
|
||||
<event name="MaliSCBusLSOtherWrBt" title="Load/store unit other write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of any reason other than write-back." units="beats" counter="BEATS_WR_LSC_OTHER" offset="61" />
|
||||
<event name="MaliSCBusLSWBWrBt" title="Load/store unit write-back write beats to L2 memory system" description="The number of write beats by the load/store unit that are because of write-back." units="beats" counter="BEATS_WR_LSC_WB" offset="63" />
|
||||
<event name="MaliSCBusLSWrBt" title="Load/store unit write beats to L2 memory system" description="The number of write beats sent by the load/store unit." units="beats" equation="(BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)" />
|
||||
<event name="MaliSCBusLSWrBy" title="Load/store unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the load/store unit." units="bytes" equation="((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)" />
|
||||
<event name="MaliSCBusLSWrByPerWr" title="Load/store unit bytes written to L2 per access cycle" description="The average number of bytes written to the L2 memory system by the load/store unit per write cycle." units="bytes" equation="(((BEATS_WR_LSC_WB) + (BEATS_WR_LSC_OTHER)) * (16)) / ((LS_MEM_WRITE_FULL) + (LS_MEM_WRITE_SHORT))" />
|
||||
<event name="MaliSCBusOtherL2RdBt" title="Miscellaneous read beats from L2 cache" description="The number of read beats received by a unit that is not specifically identified." units="beats" counter="BEATS_RD_OTHER" offset="60" />
|
||||
<event name="MaliSCBusTexExtRdBt" title="Texture unit read beats from external memory" description="The number of read beats received by the texture unit that required an external memory access because of an L2 cache miss." units="beats" counter="BEATS_RD_TEX_EXT" offset="59" />
|
||||
<event name="MaliSCBusTexExtRdBy" title="Texture unit read bytes from external memory" description="The total number of bytes read from the external memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX_EXT) * (16)" />
|
||||
<event name="MaliSCBusTexExtRdByPerRd" title="Texture unit bytes read from external memory per texture cycle" description="The average number of bytes read from the external memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX_EXT) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTexL2RdBt" title="Texture unit read beats from L2 cache" description="The number of read beats received by the texture unit." units="beats" counter="BEATS_RD_TEX" offset="58" />
|
||||
<event name="MaliSCBusTexL2RdBy" title="Texture unit read bytes from L2 cache" description="The total number of bytes read from the L2 memory system by the texture unit." units="bytes" equation="(BEATS_RD_TEX) * (16)" />
|
||||
<event name="MaliSCBusTexL2RdByPerRd" title="Texture unit bytes read from L2 per texture cycle" description="The average number of bytes read from the L2 memory system by the texture unit per filtering cycle." units="bytes" equation="((BEATS_RD_TEX) * (16)) / (TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliSCBusTileWrBPerPx" title="Tile unit bytes written to L2 per pixel" description="The average number of bytes written to the L2 memory system by the tile unit per output pixel." units="bytes" equation="((BEATS_WR_TIB) * (16)) / ((JS0_TASKS) * (32) * (32))" />
|
||||
<event name="MaliSCBusTileWrBt" title="Tile unit write beats to L2 memory system" description="The number of write beats sent by the tile write-back unit." units="beats" counter="BEATS_WR_TIB" offset="62" />
|
||||
<event name="MaliSCBusTileWrBy" title="Tile unit write bytes to L2 memory system" description="The total number of bytes written to the L2 memory system by the tile write-back unit." units="bytes" equation="(BEATS_WR_TIB) * (16)" />
|
||||
<event name="MaliTexCPI" title="Texture filtering cycles per instruction" description="The average number of texture filtering cycles per instruction." units="cycles" equation="((TEX_FILT_NUM_OPERATIONS)) / (((TEX_MSGO_NUM_MSG)) * 4)" />
|
||||
<event name="MaliTexDataFetchStallCy" title="Texture fetch stall cycles" description="The number of cycles when a quad is stalled on entering texture fetch because the fetch queue is full." units="cycles" counter="TEX_TFCH_CLK_STALLED" offset="37" />
|
||||
<event name="MaliTexDescStallCy" title="Texture descriptor stall cycles" description="The number of cycles when a quad is stalled on texture descriptor fetch." units="cycles" counter="TEX_DFCH_CLK_STALLED" offset="36" />
|
||||
<event name="MaliTexFiltFullRate" title="Texture full speed filtering percentage" description="The percentage of texture filtering cycles using the full width of the texture filtering data path." units="percent" equation="(((TEX_FILT_NUM_FXR_OPERATIONS) + (TEX_FILT_NUM_FST_OPERATIONS)) / (TEX_FILT_NUM_OPERATIONS)) * 100" />
|
||||
<event name="MaliTexFiltIssueCy" title="Texture filtering cycles" description="The number of texture filtering issue cycles." units="cycles" counter="TEX_FILT_NUM_OPERATIONS" offset="39" />
|
||||
<event name="MaliTexFiltStallCy" title="Texture filtering stall cycles" description="The number of cycles when the filtering unit is idle and there is at least one quad present in the texture data fetch queue." units="cycles" counter="TEX_TFCH_STARVED_PENDING_DATA_FETCH" offset="38" />
|
||||
<event name="MaliTexFullBiFiltCy" title="Texture filtering cycles using full bilinear" description="The number of cycles when the filtering unit is filled with bilinear filtering." units="cycles" counter="TEX_FILT_NUM_FXR_OPERATIONS" offset="40" />
|
||||
<event name="MaliTexFullTriFiltCy" title="Texture filtering cycles using full trilinear" description="The number of cycles when the filtering unit is filled with trilinear filtering." units="cycles" counter="TEX_FILT_NUM_FST_OPERATIONS" offset="41" />
|
||||
<event name="MaliTexInBt" title="Texture message read beats" description="The number of texture request message data beats." units="beats" counter="TEX_MSGI_NUM_FLITS" offset="35" />
|
||||
<event name="MaliTexInBusUtil" title="Texture input bus utilization" description="The percentage load on the texture message input bus." units="percent" equation="((TEX_MSGI_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexIssueCy" title="Texture unit issue cycles" description="The number of cycles the texture unit was busy." units="cycles" equation="(TEX_FILT_NUM_OPERATIONS)" />
|
||||
<event name="MaliTexOutBt" title="Texture message write beats" description="The number of texture response message data beats." units="beats" counter="TEX_MSGO_NUM_FLITS" offset="43" />
|
||||
<event name="MaliTexOutBusUtil" title="Texture output bus utilization" description="The percentage load on the texture message output bus." units="percent" equation="((TEX_MSGO_NUM_FLITS) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliTexOutMsg" title="Texture messages" description="The number of output texture messages from the texture unit." units="issues" counter="TEX_MSGO_NUM_MSG" offset="42" />
|
||||
<event name="MaliTexQuads" title="Texture quads" description="The number of quad-width texture operations processed by the texture unit." units="quads" equation="(TEX_MSGO_NUM_MSG)" />
|
||||
<event name="MaliTexSample" title="Texture samples" description="The number of texture samples made." units="requests" equation="((TEX_MSGO_NUM_MSG)) * 4" />
|
||||
<event name="MaliTexUtil" title="Texture unit utilization" description="The percentage utilization of the texturing unit." units="percent" equation="(((TEX_FILT_NUM_OPERATIONS)) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
<event name="MaliVar16IssueCy" title="16-bit interpolation issue cycles" description="The number of 16-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_16) / (1)" />
|
||||
<event name="MaliVar16IssueSlot" title="16-bit interpolation slots" description="The number of 16-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_16" offset="51" />
|
||||
<event name="MaliVar32IssueCy" title="32-bit interpolation issue cycles" description="The number of 32-bit interpolation cycles used by the varying unit." units="cycles" equation="(VARY_SLOT_32) / (1)" />
|
||||
<event name="MaliVar32IssueSlot" title="32-bit interpolation slots" description="The number of 32-bit interpolation slots issued by the varying unit." units="issues" counter="VARY_SLOT_32" offset="50" />
|
||||
<event name="MaliVarInstr" title="Varying unit instructions" description="The number of warp-width interpolation operations processed by the varying unit." units="requests" counter="VARY_INSTR" offset="49" />
|
||||
<event name="MaliVarIssueCy" title="Varying unit issue cycles" description="The total number of varying unit issue cycles." units="cycles" equation="((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))" />
|
||||
<event name="MaliVarUtil" title="Varying unit utilization" description="The percentage utilization of the varying unit." units="percent" equation="((((VARY_SLOT_32) / (1)) + ((VARY_SLOT_16) / (1))) / (EXEC_CORE_ACTIVE)) * 100" />
|
||||
</category>
|
||||
<category name="Tiler">
|
||||
<event name="MaliGeomBackFacePrim" title="Visible back-facing primitives" description="The number of back-facing triangles that are visible after culling." units="primitives" counter="BACK_FACING" offset="10" />
|
||||
<event name="MaliGeomFaceXYPlaneCullPrim" title="Facing or XY plane test culled primitives" description="The number of primitives that are culled by facing or frustum XY plane tests." units="primitives" counter="PRIM_CULLED" offset="12" />
|
||||
<event name="MaliGeomFaceXYPlaneCullRate" title="Facing or XY plane test cull percentage" description="The percentage of primitives culled by the facing or frustum XY plane tests." units="percent" equation="((PRIM_CULLED) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomFrontFacePrim" title="Visible front-facing primitives" description="The number of front-facing triangles that are visible after culling." units="primitives" counter="FRONT_FACING" offset="9" />
|
||||
<event name="MaliGeomLinePrim" title="Line primitives" description="The number of input line primitives." units="primitives" counter="LINES" offset="7" />
|
||||
<event name="MaliGeomPointPrim" title="Point primitives" description="The number of input point primitives." units="primitives" counter="POINTS" offset="8" />
|
||||
<event name="MaliGeomPosShadTask" title="Tiler position shading requests" description="The number of position shading requests in the tiler geometry flow." units="requests" counter="IDVS_POS_SHAD_REQ" offset="21" />
|
||||
<event name="MaliGeomPosShadThread" title="Position shader thread invocations" description="The number of position shader thread invocations." units="threads" equation="(IDVS_POS_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomPosShadThreadPerPrim" title="Position threads per input primitive" description="The number of position shader invocations per input primitive." units="threads" equation="((IDVS_POS_SHAD_REQ) * (4)) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))" />
|
||||
<event name="MaliGeomSampleCullPrim" title="Sample test culled primitives" description="The number of primitives culled by the sample coverage test." units="primitives" counter="PRIM_SAT_CULLED" offset="14" />
|
||||
<event name="MaliGeomSampleCullRate" title="Sample test cull percentage" description="The percentage of primitives culled by the sample coverage test." units="percent" equation="((PRIM_SAT_CULLED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED) - (PRIM_CLIPPED))) * 100" />
|
||||
<event name="MaliGeomTotalCullPrim" title="Culled primitives" description="The number of primitives that were culled during the rendering process." units="primitives" equation="(PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)" />
|
||||
<event name="MaliGeomTotalPrim" title="Total input primitives" description="The total number of input primitives to the rendering process." units="primitives" equation="((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomTrianglePrim" title="Triangle primitives" description="The number of input triangle primitives." units="primitives" counter="TRIANGLES" offset="6" />
|
||||
<event name="MaliGeomVarShadTask" title="Tiler varying shading requests" description="The number of varying shading requests in the tiler geometry flow." units="requests" counter="IDVS_VAR_SHAD_REQ" offset="37" />
|
||||
<event name="MaliGeomVarShadThread" title="Varying shader thread invocations" description="The number of varying shader thread invocations." units="threads" equation="(IDVS_VAR_SHAD_REQ) * (4)" />
|
||||
<event name="MaliGeomVarShadThreadPerPrim" title="Varying threads per input primitive" description="The number of varying shader invocations per visible primitive." units="threads" equation="((IDVS_VAR_SHAD_REQ) * (4)) / (PRIM_VISIBLE)" />
|
||||
<event name="MaliGeomVisiblePrim" title="Visible primitives" description="The number of primitives that are visible after culling." units="primitives" counter="PRIM_VISIBLE" offset="11" />
|
||||
<event name="MaliGeomVisibleRate" title="Visible primitive percentage" description="The percentage of primitives that are visible after culling." units="percent" equation="((PRIM_VISIBLE) / (((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE))) * 100" />
|
||||
<event name="MaliGeomZPlaneCullPrim" title="Z plane culled primitives" description="The number of primitives that are culled by frustum Z plane tests." units="primitives" counter="PRIM_CLIPPED" offset="13" />
|
||||
<event name="MaliGeomZPlaneCullRate" title="Z plane test cull percentage" description="The percentage of primitives culled by the frustum Z plane test." units="percent" equation="((PRIM_CLIPPED) / ((((PRIM_CULLED) + (PRIM_CLIPPED) + (PRIM_SAT_CULLED)) + (PRIM_VISIBLE)) - (PRIM_CULLED))) * 100" />
|
||||
<event name="MaliTilerActiveCy" title="Tiler active cycles" description="The number of cycles when the tiler has a workload queued for processing." units="cycles" counter="TILER_ACTIVE" offset="4" />
|
||||
<event name="MaliTilerPosCacheHit" title="Position cache hit requests" description="The number of position lookups that result in a hit in the vertex cache." units="requests" counter="VCACHE_HIT" offset="26" />
|
||||
<event name="MaliTilerPosCacheHitRate" title="Position cache hit percentage" description="The percentage hit rate of the tiler position cache." units="percent" equation="((VCACHE_HIT) / ((VCACHE_HIT) + (VCACHE_MISS))) * 100" />
|
||||
<event name="MaliTilerPosCacheMiss" title="Position cache miss requests" description="The number of position lookups that miss in the vertex cache." units="requests" counter="VCACHE_MISS" offset="27" />
|
||||
<event name="MaliTilerPosShadFIFOFullCy" title="Tiler position FIFO full cycles" description="The number of cycles when the tiler has a stalled position shading buffer." units="cycles" counter="IDVS_POS_FIFO_FULL" offset="24" />
|
||||
<event name="MaliTilerPosShadStallCy" title="Tiler position shading stall cycles" description="The number of cycles when the tiler has a stalled position shading request." units="cycles" counter="IDVS_POS_SHAD_STALL" offset="23" />
|
||||
<event name="MaliTilerRdBt" title="Output internal read beats" description="The number of internal bus data read cycles made by the tiler." units="beats" counter="BUS_READ" offset="17" />
|
||||
<event name="MaliTilerUtil" title="Tiler utilization" description="The percentage of GPU active cycles when the tiler has a workload queued for processing." units="percent" equation="((TILER_ACTIVE) / (GPU_ACTIVE)) * 100" />
|
||||
<event name="MaliTilerVarCacheHit" title="Varying cache hits" description="The number of varying lookups that result in a hit in the vertex cache." units="requests" counter="IDVS_VBU_HIT" offset="34" />
|
||||
<event name="MaliTilerVarCacheHitRate" title="Varying cache hit percentage" description="The percentage hit rate of the tiler varying cache." units="percent" equation="((IDVS_VBU_HIT) / ((IDVS_VBU_HIT) + (IDVS_VBU_MISS))) * 100" />
|
||||
<event name="MaliTilerVarCacheMiss" title="Varying cache misses" description="The number of varying lookups that miss in the vertex cache." units="requests" counter="IDVS_VBU_MISS" offset="35" />
|
||||
<event name="MaliTilerVarShadStallCy" title="Tiler varying shading stall cycles" description="The number of cycles when the tiler has a stalled varying shading request." units="cycles" counter="IDVS_VAR_SHAD_STALL" offset="38" />
|
||||
</category>
|
||||
</metrics>
|
||||
|
|
@ -3,8 +3,20 @@
|
|||
# SPDX-License-Identifier: MIT
|
||||
|
||||
pan_hw_metrics = [
|
||||
'G31', 'G51', 'G52', 'G57', 'G68', 'G71', 'G72', 'G76', 'G77',
|
||||
'Gx10', 'Gx25', 'G78', 'T72x', 'T76x', 'T82x', 'T83x', 'T86x', 'T88x',
|
||||
'T72x', 'T76x', 'T82x', 'T83x', 'T86x', 'T88x',
|
||||
'generated/G31',
|
||||
'generated/G51',
|
||||
'generated/G52',
|
||||
'generated/G71',
|
||||
'generated/G72',
|
||||
'generated/G76',
|
||||
'generated/G77',
|
||||
'generated/G78',
|
||||
'generated/G710',
|
||||
'generated/G715',
|
||||
'generated/G720',
|
||||
'generated/G725',
|
||||
'generated/G1',
|
||||
]
|
||||
|
||||
pan_hw_metrics_xml_files = []
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue