diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 9f6f3621e1f..4c89a24c333 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -110,7 +110,7 @@ struct ac_llvm_compiler;
 #define SI_RESOURCE_FLAG_32BIT             (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
 #define SI_RESOURCE_FLAG_CLEAR             (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
 
-#define SI_SQTT_STATE_DIRTY_BIT            BITFIELD_BIT(MESA_SHADER_COMPUTE + 1)
+#define SI_SQTT_STATE_DIRTY_BIT            BITFIELD_BIT(MESA_SHADER_MESH + 1)
 
 enum si_has_gs {
    GS_OFF,
@@ -1120,10 +1120,10 @@ struct si_context {
    unsigned num_vertex_elements;  /* 0 if the VS uses blit SGPRs to compute VS inputs */
    unsigned cs_max_waves_per_sh;
    uint32_t compute_tmpring_size;
+   uint16_t dirty_shaders_mask; /* 0: vs, 1: tcs, 2: tes, 3: gs, 4: ps, 5: cs, 6: ts, 7: ms, 8: misc (e.g. sqtt) */
    bool vertex_elements_but_no_buffers;
    bool uses_nontrivial_vs_inputs;
    bool force_trivial_vs_inputs;
-   uint8_t dirty_shaders_mask; /* 0: vs, 1: tcs, 2: tes, 3: gs, 4: ps, 5: cs, 6: misc (e.g. sqtt) */
    bool compute_shaderbuf_sgprs_dirty;
    bool compute_image_sgprs_dirty;
    bool vs_uses_base_instance;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index c857d759147..f36360bbf02 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1417,7 +1417,8 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
       sctx->dirty_shaders_mask |=
          BITFIELD_BIT(MESA_SHADER_VERTEX) |
          BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
-         BITFIELD_BIT(MESA_SHADER_GEOMETRY);
+         BITFIELD_BIT(MESA_SHADER_GEOMETRY) |
+         BITFIELD_BIT(MESA_SHADER_MESH);
    }
 
    if (old_rs->line_smooth != rs->line_smooth ||
@@ -1763,7 +1764,8 @@ static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
          BITFIELD_BIT(MESA_SHADER_VERTEX) |
          BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
          BITFIELD_BIT(MESA_SHADER_GEOMETRY) |
-         BITFIELD_BIT(MESA_SHADER_FRAGMENT);
+         BITFIELD_BIT(MESA_SHADER_FRAGMENT) |
+         BITFIELD_BIT(MESA_SHADER_MESH);
    }
 
    if (old_dsa->depth_enabled != dsa->depth_enabled ||
@@ -2805,7 +2807,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
       BITFIELD_BIT(MESA_SHADER_VERTEX) |
       BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
       BITFIELD_BIT(MESA_SHADER_GEOMETRY) |
-      BITFIELD_BIT(MESA_SHADER_FRAGMENT);
+      BITFIELD_BIT(MESA_SHADER_FRAGMENT) |
+      BITFIELD_BIT(MESA_SHADER_MESH);
 
    if (sctx->gfx_level < GFX12 && !sctx->decompression_enabled) {
       /* Prevent textures decompression when the framebuffer state
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp
index 6a66e472ffa..e8b725a39eb 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -39,6 +39,9 @@
 #error "Unknown gfx level"
 #endif
 
+#define SI_VERTEX_PIPELINE_STATE_DIRTY_MASK \
+   (BITFIELD_MASK(MESA_SHADER_FRAGMENT + 1) | SI_SQTT_STATE_DIRTY_BIT)
+
 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
 static bool si_update_shaders(struct si_context *sctx)
 {
@@ -515,7 +518,7 @@ static bool si_update_shaders(struct si_context *sctx)
    if (GFX_VERSION >= GFX10 && NGG)
       sctx->ngg_culling = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->key.ge.opt.ngg_culling;
 
-   sctx->dirty_shaders_mask = 0u;
+   sctx->dirty_shaders_mask &= ~SI_VERTEX_PIPELINE_STATE_DIRTY_MASK;
    return true;
 }
 
@@ -2344,7 +2347,7 @@ static void si_draw(struct pipe_context *ctx,
     */
    assert(!sctx->ms_shader_state.cso);
 
-   if (unlikely(sctx->dirty_shaders_mask)) {
+   if (unlikely(sctx->dirty_shaders_mask & SI_VERTEX_PIPELINE_STATE_DIRTY_MASK)) {
       if (unlikely(!(si_update_shaders<GFX_VERSION, HAS_TESS, HAS_GS, NGG>(sctx)))) {
          DRAW_CLEANUP;
          return;
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index 1e68cf0586e..e9492f479c3 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -2483,9 +2483,9 @@ void si_update_ps_inputs_read_or_disabled(struct si_context *sctx)
 
    if (sctx->ps_inputs_read_or_disabled != ps_inputs_read_or_disabled) {
       sctx->ps_inputs_read_or_disabled = ps_inputs_read_or_disabled;
-      sctx->dirty_shaders_mask |=
-         (sctx->shader.gs.cso ? BITFIELD_BIT(MESA_SHADER_GEOMETRY) :
-            (sctx->shader.tes.cso ? BITFIELD_BIT(MESA_SHADER_TESS_EVAL) : BITFIELD_BIT(MESA_SHADER_VERTEX)));
+      struct si_shader_selector *cso = si_get_vs(sctx)->cso;
+      if (cso)
+         sctx->dirty_shaders_mask |= BITFIELD_BIT(cso->stage);
    }
 }
 
@@ -2537,7 +2537,8 @@ void si_vs_ps_key_update_rast_prim_smooth_stipple(struct si_context *sctx)
       sctx->dirty_shaders_mask |=
          BITFIELD_BIT(MESA_SHADER_VERTEX) |
          BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
-         BITFIELD_BIT(MESA_SHADER_GEOMETRY);
+         BITFIELD_BIT(MESA_SHADER_GEOMETRY) |
+         BITFIELD_BIT(MESA_SHADER_MESH);
    }
 
    if (ps_key->ps.part.prolog.color_two_side != old_color_two_side ||