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Merge remote branch 'origin/master' into pipe-video

Browse source 
Conflicts:
	src/gallium/drivers/r600/r600_shader.c
This commit is contained in:
Christian König 2011-01-12 00:48:10 +01:00
commit a96fe679e2
193 changed files with 3584 additions and 15581 deletions
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2
configs/autoconf.in
View file

@ -15,7 +15,6 @@ ASM_FLAGS = @ASM_FLAGS@
PIC_FLAGS = @PIC_FLAGS@
DEFINES = @DEFINES@
API_DEFINES = @API_DEFINES@
GLES_OVERLAY = @GLES_OVERLAY@
CFLAGS = @CPPFLAGS@ @CFLAGS@ \
$(OPT_FLAGS) $(PIC_FLAGS) $(ARCH_FLAGS) $(ASM_FLAGS) $(DEFINES)
CXXFLAGS = @CPPFLAGS@ @CXXFLAGS@ \
@ -33,6 +32,7 @@ LLVM_LDFLAGS = @LLVM_LDFLAGS@
LLVM_LIBS = @LLVM_LIBS@
GLW_CFLAGS = @GLW_CFLAGS@
GLUT_CFLAGS = @GLUT_CFLAGS@
GLX_TLS = @GLX_TLS@
TALLOC_LIBS = @TALLOC_LIBS@
TALLOC_CFLAGS = @TALLOC_CFLAGS@

3
configs/default
View file

@ -25,6 +25,7 @@ CXXFLAGS = -O
LDFLAGS =
HOST_CFLAGS = $(CFLAGS)
GLU_CFLAGS =
GLX_TLS = no
# Compiler for building demos/tests/etc
APP_CC = $(CC)
@ -107,7 +108,7 @@ EGL_DRIVERS_DIRS = glx
# Gallium directories and
GALLIUM_DIRS = auxiliary drivers state_trackers
GALLIUM_AUXILIARIES = $(TOP)/src/gallium/auxiliary/libgallium.a
GALLIUM_DRIVERS_DIRS = softpipe trace rbug identity galahad i915 i965 svga r300 nvfx nv50 failover
GALLIUM_DRIVERS_DIRS = softpipe trace rbug noop identity galahad i915 i965 svga r300 nvfx nv50 failover
GALLIUM_DRIVERS = $(foreach DIR,$(GALLIUM_DRIVERS_DIRS),$(TOP)/src/gallium/drivers/$(DIR)/lib$(DIR).a)
GALLIUM_WINSYS_DIRS = sw sw/xlib
GALLIUM_TARGET_DIRS = libgl-xlib

64
configure.ac
View file

@ -18,11 +18,11 @@ AC_CONFIG_AUX_DIR([bin])
AC_CANONICAL_HOST
dnl Versions for external dependencies
LIBDRM_REQUIRED=2.4.15
LIBDRM_RADEON_REQUIRED=2.4.17
LIBDRM_REQUIRED=2.4.23
LIBDRM_RADEON_REQUIRED=2.4.23
DRI2PROTO_REQUIRED=2.1
GLPROTO_REQUIRED=1.4.11
LIBDRM_XORG_REQUIRED=2.4.17
LIBDRM_XORG_REQUIRED=2.4.23
LIBKMS_XORG_REQUIRED=1.0.0
dnl Check for progs
@ -483,9 +483,9 @@ AC_ARG_ENABLE([gles2],
[enable_gles2=no])
AC_ARG_ENABLE([gles-overlay],
[AS_HELP_STRING([--enable-gles-overlay],
[build separate OpenGL ES only libraries @<:@default=no@:>@])],
[enable_gles_overlay="$enableval"],
[enable_gles_overlay=no])
[DEPRECATED. Same as --enable-gles1 and --enable-gles2])],
[enable_gles1="$enableval"; enable_gles2="$enableval"],
[])
AC_ARG_ENABLE([openvg],
[AS_HELP_STRING([--enable-openvg],
@ -506,13 +506,11 @@ fi
if test "x$enable_opengl" = xno -a \
"x$enable_gles1" = xno -a \
"x$enable_gles2" = xno -a \
"x$enable_gles_overlay" = xno -a \
"x$enable_openvg" = xno; then
AC_MSG_ERROR([at least one API should be enabled])
fi
API_DEFINES=""
GLES_OVERLAY=0
if test "x$enable_opengl" = xno; then
API_DEFINES="$API_DEFINES -DFEATURE_GL=0"
else
@ -524,11 +522,7 @@ fi
if test "x$enable_gles2" = xyes; then
API_DEFINES="$API_DEFINES -DFEATURE_ES2=1"
fi
if test "x$enable_gles_overlay" = xyes; then
GLES_OVERLAY=1
fi
AC_SUBST([API_DEFINES])
AC_SUBST([GLES_OVERLAY])
dnl
dnl Driver configuration. Options are xlib, dri and osmesa right now.
@ -588,7 +582,7 @@ GLU_DIRS="sgi"
GALLIUM_DIRS="auxiliary drivers state_trackers"
GALLIUM_TARGET_DIRS=""
GALLIUM_WINSYS_DIRS="sw"
GALLIUM_DRIVERS_DIRS="softpipe failover galahad trace rbug identity"
GALLIUM_DRIVERS_DIRS="softpipe failover galahad trace rbug noop identity"
GALLIUM_STATE_TRACKERS_DIRS=""
# build glapi if OpenGL is enabled
@ -596,12 +590,15 @@ if test "x$enable_opengl" = xyes; then
CORE_DIRS="$CORE_DIRS mapi/glapi"
fi
# build es1api and es2api if OpenGL ES is enabled
case "x$enable_gles1$enable_gles2$enable_gles_overlay" in
x*yes*)
CORE_DIRS="$CORE_DIRS mapi/es1api mapi/es2api"
;;
esac
# build es1api if OpenGL ES 1.x is enabled
if test "x$enable_gles1" = xyes; then
CORE_DIRS="$CORE_DIRS mapi/es1api"
fi
# build es2api if OpenGL ES 2.x is enabled
if test "x$enable_gles2" = xyes; then
CORE_DIRS="$CORE_DIRS mapi/es2api"
fi
# build vgapi if OpenVG is enabled
if test "x$enable_openvg" = xyes; then
@ -609,7 +606,7 @@ if test "x$enable_openvg" = xyes; then
fi
# build glsl and mesa if OpenGL or OpenGL ES is enabled
case "x$enable_opengl$enable_gles1$enable_gles2$enable_gles_overlay" in
case "x$enable_opengl$enable_gles1$enable_gles2" in
x*yes*)
CORE_DIRS="$CORE_DIRS glsl mesa"
;;
@ -811,13 +808,19 @@ if test "$mesa_driver" = xlib; then
fi
dnl
dnl More DRI setup
dnl TLS detection
dnl
AC_ARG_ENABLE([glx-tls],
[AS_HELP_STRING([--enable-glx-tls],
[enable TLS support in GLX @<:@default=disabled@:>@])],
[GLX_USE_TLS="$enableval"],
[GLX_USE_TLS=no])
AC_SUBST(GLX_TLS, ${GLX_USE_TLS})
dnl
dnl More DRI setup
dnl
dnl Directory for DRI drivers
AC_ARG_WITH([dri-driverdir],
[AS_HELP_STRING([--with-dri-driverdir=DIR],
@ -1472,9 +1475,6 @@ x*yes*)
EGL_CLIENT_APIS="$EGL_CLIENT_APIS "'$(GL_LIB)'
;;
esac
if test "x$enable_gles_overlay" = xyes; then
EGL_CLIENT_APIS="$EGL_CLIENT_APIS "'$(GLESv1_CM_LIB) $(GLESv2_LIB)'
fi
if test "x$enable_openvg" = xyes; then
EGL_CLIENT_APIS="$EGL_CLIENT_APIS "'$(VG_LIB)'
VG_LIB_DEPS="$VG_LIB_DEPS -lpthread"
@ -1773,19 +1773,6 @@ if test "x$enable_gallium_swrast" = xyes || test "x$enable_gallium_swrast" = xau
fi
fi
dnl
dnl Gallium noop configuration
dnl
AC_ARG_ENABLE([gallium-noop],
[AS_HELP_STRING([--enable-gallium-noop],
[build gallium radeon @<:@default=disabled@:>@])],
[enable_gallium_noop="$enableval"],
[enable_gallium_noop=auto])
if test "x$enable_gallium_noop" = xyes; then
GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS noop"
GALLIUM_TARGET_DIRS="$GALLIUM_TARGET_DIRS dri-noop"
fi
dnl prepend CORE_DIRS to SRC_DIRS
SRC_DIRS="$CORE_DIRS $SRC_DIRS"
@ -1818,7 +1805,6 @@ echo " includedir: $includedir"
dnl API info
echo ""
echo " OpenGL: $enable_opengl (ES1: $enable_gles1 ES2: $enable_gles2)"
echo " GLES overlay: $enable_gles_overlay"
echo " OpenVG: $enable_openvg"
dnl Driver info
@ -1855,7 +1841,7 @@ if test "$enable_egl" = yes; then
egl_drivers=""
for d in $EGL_DRIVERS_DIRS; do
egl_drivers="$egl_drivers egl_$d"
egl_drivers="$egl_drivers builtin:egl_$d"
done
if test "$enable_gallium" = yes -a "$HAVE_ST_EGL" = yes; then

18
docs/egl.html
View file

@ -88,17 +88,6 @@ internal library that supports multiple APIs.</p>
</li>
<li><code>--enable-gles-overlay</code>
<p>This option enables OpenGL ES as separate internal libraries. This is an
alternative approach to enable OpenGL ES.</p>
<p>This is only supported by <code>egl_gallium</code>. For systems using DRI
drivers, <code>--enable-gles1</code> and <code>--enable-gles2</code> are
suggested instead as all drivers will benefit.</p>
</li>
<li><code>--enable-openvg</code>
<p>OpenVG must be explicitly enabled by this option.</p>
@ -148,9 +137,10 @@ may set</p>
<li><code>EGL_DRIVER</code>
<p>This variable specifies a full path to an EGL driver and it forces the
specified EGL driver to be loaded. It comes in handy when one wants to test a
specific driver. This variable is ignored for setuid/setgid binaries.</p>
<p>This variable specifies a full path to or the name of an EGL driver. It
forces the specified EGL driver to be loaded. It comes in handy when one wants
to test a specific driver. This variable is ignored for setuid/setgid
binaries.</p>
</li>

4
docs/opengles.html
View file

@ -17,7 +17,7 @@ target="_parent"> http://www.khronos.org/opengles/</a>.</p>
<h2>Build the Libraries</h2>
<ol>
<li>Run <code>configure</code> with <code>--enable-gles-overlay</code> and enable the Gallium driver for your hardware.</li>
<li>Run <code>configure</code> with <code>--enable-gles1 --enable-gles2</code> and enable the Gallium driver for your hardware.</li>
<li>Build and install Mesa as usual.</li>
</ol>
@ -53,8 +53,6 @@ your build. For example,</p>
<tr><td>Library Name</td><td>Used By</td><td>Enabled</td><td>OpenGL</td><td>OpenGL ES 1.x</td><td>OpenGL ES 2.x</td></tr>
<tr><td><code>libmesa.a</td><td>Classic DRI drivers</td><td>y</td><td>y</td><td>--enable-gles1</td><td>--enable-gles2</td></tr>
<tr><td><code>libmesagallium.a</td><td>Gallium EGL and DRI drivers</td><td>y</td><td>y</td><td>--enable-gles1</td><td>--enable-gles2</td></tr>
<tr><td><code>libes1gallium.a</td><td>Gallium EGL drivers</td><td>--enable-gles-overlay</td><td>n</td><td>y</td><td>n</td></tr>
<tr><td><code>libes2gallium.a</td><td>Gallium EGL drivers</td><td>--enable-gles-overlay</td><td>n</td><td>n</td><td>y</td></tr>
</table>
<h3>Dispatch Table</h3>

9
include/GL/internal/dri_interface.h
View file

@ -251,6 +251,15 @@ struct __DRItexBufferExtensionRec {
GLint target,
GLint format,
__DRIdrawable *pDraw);
/**
* Method to release texture buffer in case some special platform
* need this.
*
* For GLX_EXT_texture_from_pixmap with AIGLX.
*/
void (*releaseTexBuffer)(__DRIcontext *pDRICtx,
GLint target,
__DRIdrawable *pDraw);
};
/**

2
src/egl/Makefile
View file

@ -3,7 +3,7 @@
TOP = ../..
include $(TOP)/configs/current
SUBDIRS = main drivers
SUBDIRS = drivers main
default: subdirs

30
src/egl/drivers/Makefile.template
View file

@ -2,6 +2,7 @@
#
# Drivers should define
#
# EGL_BUILTIN, the driver is built-in or external
# EGL_DRIVER, the driver name
# EGL_SOURCES, the driver sources
# EGL_INCLUDES, the include pathes
@ -12,32 +13,45 @@
#
EGL_DRIVER_PATH = $(TOP)/$(LIB_DIR)/egl/$(EGL_DRIVER)
EGL_DRIVER_PATH = $(TOP)/$(LIB_DIR)/egl/$(EGL_DRIVER).so
EGL_OBJECTS = $(EGL_SOURCES:.c=.o)
# built-in or external
ifeq ($(EGL_BUILTIN),true)
EGL_TARGET = lib$(EGL_DRIVER).a
EGL_INSTALL =
else
EGL_TARGET = $(EGL_DRIVER_PATH)
EGL_INSTALL = install-so
endif
default: depend $(EGL_DRIVER_PATH)
default: depend $(EGL_TARGET)
$(EGL_DRIVER_PATH): $(EGL_DRIVER)
$(EGL_DRIVER_PATH): $(EGL_DRIVER).so
@$(INSTALL) -d $(TOP)/$(LIB_DIR)/egl
$(INSTALL) $< $(TOP)/$(LIB_DIR)/egl
$(EGL_DRIVER): $(EGL_OBJECTS) Makefile $(TOP)/src/egl/drivers/Makefile.template
@$(MKLIB) -o $(EGL_DRIVER) -noprefix \
$(EGL_DRIVER).so: $(EGL_OBJECTS) Makefile $(TOP)/src/egl/drivers/Makefile.template
@$(MKLIB) -o $(EGL_DRIVER).so -noprefix \
-linker '$(CC)' -ldflags '-L$(TOP)/$(LIB_DIR) $(LDFLAGS)' \
$(MKLIB_OPTIONS) \
$(EGL_OBJECTS) $(EGL_LIBS) -l$(EGL_LIB)
lib$(EGL_DRIVER).a: $(EGL_OBJECTS) Makefile $(TOP)/src/egl/drivers/Makefile.template
@$(MKLIB) -o $(EGL_DRIVER) -static $(EGL_OBJECTS)
.c.o:
$(CC) -c $(EGL_INCLUDES) $(CFLAGS) $(EGL_CFLAGS) $< -o $@
install: $(EGL_DRIVER_PATH)
install-so: $(EGL_DRIVER_PATH)
$(INSTALL) -d $(DESTDIR)$(EGL_DRIVER_INSTALL_DIR)
$(MINSTALL) $(EGL_DRIVER_PATH) $(DESTDIR)$(EGL_DRIVER_INSTALL_DIR)
install: $(EGL_INSTALL)
clean:
rm -f $(EGL_DRIVER)
rm -f $(EGL_DRIVER).so
rm -f lib$(EGL_DRIVER).a
rm -f $(EGL_OBJECTS)
rm -f depend depend.bak

7
src/egl/drivers/dri2/Makefile
View file

@ -3,7 +3,7 @@
TOP = ../../../..
include $(TOP)/configs/current
EGL_DRIVER = egl_dri2.so
EGL_DRIVER = egl_dri2
EGL_SOURCES = egl_dri2.c
EGL_INCLUDES = \
@ -15,6 +15,9 @@ EGL_INCLUDES = \
$(LIBUDEV_CFLAGS) \
$(LIBDRM_CFLAGS)
EGL_LIBS = $(XCB_DRI2_LIBS) $(LIBUDEV_LIBS) $(LIBDRM_LIBS)
EGL_LIBS = $(XCB_DRI2_LIBS) $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIB)
EGL_CFLAGS = -D_EGL_MAIN=_eglBuiltInDriverDRI2
EGL_BUILTIN = true
include ../Makefile.template

91
src/egl/drivers/dri2/egl_dri2.c
View file

@ -47,7 +47,6 @@
#include <libudev.h>
#endif
#include <glapi/glapi.h>
#include "eglconfig.h"
#include "eglcontext.h"
#include "egldisplay.h"
@ -63,6 +62,7 @@ struct dri2_egl_driver
{
_EGLDriver base;
_EGLProc (*get_proc_address)(const char *procname);
void (*glFlush)(void);
};
@ -1867,11 +1867,9 @@ dri2_swap_buffers_region(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw,
static _EGLProc
dri2_get_proc_address(_EGLDriver *drv, const char *procname)
{
(void) drv;
struct dri2_egl_driver *dri2_drv = dri2_egl_driver(drv);
/* FIXME: Do we need to support lookup of EGL symbols too? */
return (_EGLProc) _glapi_get_proc_address(procname);
return dri2_drv->get_proc_address(procname);
}
static EGLBoolean
@ -1903,13 +1901,6 @@ dri2_wait_native(_EGLDriver *drv, _EGLDisplay *disp, EGLint engine)
return EGL_TRUE;
}
static void
dri2_unload(_EGLDriver *drv)
{
struct dri2_egl_driver *dri2_drv = dri2_egl_driver(drv);
free(dri2_drv);
}
static EGLBoolean
dri2_copy_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *surf,
EGLNativePixmapType target)
@ -1983,10 +1974,31 @@ static EGLBoolean
dri2_release_tex_image(_EGLDriver *drv,
_EGLDisplay *disp, _EGLSurface *surf, EGLint buffer)
{
(void) drv;
(void) disp;
(void) surf;
(void) buffer;
#if __DRI_TEX_BUFFER_VERSION >= 3
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
struct dri2_egl_context *dri2_ctx;
_EGLContext *ctx;
GLint target;
ctx = _eglGetCurrentContext();
dri2_ctx = dri2_egl_context(ctx);
if (!_eglReleaseTexImage(drv, disp, surf, buffer))
return EGL_FALSE;
switch (dri2_surf->base.TextureTarget) {
case EGL_TEXTURE_2D:
target = GL_TEXTURE_2D;
break;
default:
assert(0);
}
if (dri2_dpy->tex_buffer->releaseTexBuffer!=NULL)
(*dri2_dpy->tex_buffer->releaseTexBuffer)(dri2_ctx->dri_context,
target,
dri2_surf->dri_drawable);
#endif
return EGL_TRUE;
}
@ -2316,12 +2328,51 @@ dri2_export_drm_image_mesa(_EGLDriver *drv, _EGLDisplay *disp, _EGLImage *img,
return EGL_TRUE;
}
static void
dri2_unload(_EGLDriver *drv)
{
struct dri2_egl_driver *dri2_drv = dri2_egl_driver(drv);
free(dri2_drv);
}
static EGLBoolean
dri2_load(_EGLDriver *drv)
{
struct dri2_egl_driver *dri2_drv = dri2_egl_driver(drv);
void *handle;
handle = dlopen(NULL, RTLD_LAZY | RTLD_GLOBAL);
if (handle) {
dri2_drv->get_proc_address = (_EGLProc (*)(const char *))
dlsym(handle, "_glapi_get_proc_address");
/* no need to keep a reference */
dlclose(handle);
}
/*
* If glapi is not available, loading DRI drivers will fail. Ideally, we
* should load one of libGL, libGLESv1_CM, or libGLESv2 and go on. But if
* the app has loaded another one of them with RTLD_LOCAL, there may be
* unexpected behaviors later because there will be two copies of glapi
* (with global variables of the same names!) in the memory.
*/
if (!dri2_drv->get_proc_address) {
_eglLog(_EGL_WARNING, "DRI2: failed to find _glapi_get_proc_address");
return EGL_FALSE;
}
dri2_drv->glFlush = (void (*)(void))
dri2_drv->get_proc_address("glFlush");
return EGL_TRUE;
}
/**
* This is the main entrypoint into the driver, called by libEGL.
* Create a new _EGLDriver object and init its dispatch table.
*/
_EGLDriver *
_eglMain(const char *args)
_EGL_MAIN(const char *args)
{
struct dri2_egl_driver *dri2_drv;
@ -2331,6 +2382,9 @@ _eglMain(const char *args)
if (!dri2_drv)
return NULL;
if (!dri2_load(&dri2_drv->base))
return NULL;
memset(dri2_drv, 0, sizeof *dri2_drv);
_eglInitDriverFallbacks(&dri2_drv->base);
dri2_drv->base.API.Initialize = dri2_initialize;
@ -2357,8 +2411,5 @@ _eglMain(const char *args)
dri2_drv->base.Name = "DRI2";
dri2_drv->base.Unload = dri2_unload;
dri2_drv->glFlush =
(void (*)(void)) dri2_get_proc_address(&dri2_drv->base, "glFlush");
return &dri2_drv->base;
}

7
src/egl/drivers/glx/Makefile
View file

@ -3,7 +3,7 @@
TOP = ../../../..
include $(TOP)/configs/current
EGL_DRIVER = egl_glx.so
EGL_DRIVER = egl_glx
EGL_SOURCES = egl_glx.c
EGL_INCLUDES = \
@ -11,6 +11,9 @@ EGL_INCLUDES = \
-I$(TOP)/src/egl/main
EGL_CFLAGS = $(X11_CFLAGS)
EGL_LIBS = $(X11_LIBS) -lGL
EGL_LIBS = $(X11_LIBS) $(DLOPEN_LIBS)
EGL_CFLAGS += -D_EGL_MAIN=_eglBuiltInDriverGLX
EGL_BUILTIN = true
include ../Makefile.template

357
src/egl/drivers/glx/egl_glx.c
View file

@ -36,8 +36,8 @@
#include <stdlib.h>
#include <string.h>
#include <X11/Xlib.h>
#include <GL/glx.h>
#include <EGL/egl.h>
#include <dlfcn.h>
#include "GL/glx.h"
#include "eglconfig.h"
#include "eglcontext.h"
@ -54,10 +54,66 @@
#error "GL/glx.h must be equal to or greater than GLX 1.4"
#endif
/* GLX 1.0 */
typedef GLXContext (*GLXCREATECONTEXTPROC)( Display *dpy, XVisualInfo *vis, GLXContext shareList, Bool direct );
typedef void (*GLXDESTROYCONTEXTPROC)( Display *dpy, GLXContext ctx );
typedef Bool (*GLXMAKECURRENTPROC)( Display *dpy, GLXDrawable drawable, GLXContext ctx);
typedef void (*GLXSWAPBUFFERSPROC)( Display *dpy, GLXDrawable drawable );
typedef GLXPixmap (*GLXCREATEGLXPIXMAPPROC)( Display *dpy, XVisualInfo *visual, Pixmap pixmap );
typedef void (*GLXDESTROYGLXPIXMAPPROC)( Display *dpy, GLXPixmap pixmap );
typedef Bool (*GLXQUERYVERSIONPROC)( Display *dpy, int *maj, int *min );
typedef int (*GLXGETCONFIGPROC)( Display *dpy, XVisualInfo *visual, int attrib, int *value );
typedef void (*GLXWAITGLPROC)( void );
typedef void (*GLXWAITXPROC)( void );
/* GLX 1.1 */
typedef const char *(*GLXQUERYEXTENSIONSSTRINGPROC)( Display *dpy, int screen );
typedef const char *(*GLXQUERYSERVERSTRINGPROC)( Display *dpy, int screen, int name );
typedef const char *(*GLXGETCLIENTSTRINGPROC)( Display *dpy, int name );
/** subclass of _EGLDriver */
struct GLX_egl_driver
{
_EGLDriver Base; /**< base class */
void *handle;
/* GLX 1.0 */
GLXCREATECONTEXTPROC glXCreateContext;
GLXDESTROYCONTEXTPROC glXDestroyContext;
GLXMAKECURRENTPROC glXMakeCurrent;
GLXSWAPBUFFERSPROC glXSwapBuffers;
GLXCREATEGLXPIXMAPPROC glXCreateGLXPixmap;
GLXDESTROYGLXPIXMAPPROC glXDestroyGLXPixmap;
GLXQUERYVERSIONPROC glXQueryVersion;
GLXGETCONFIGPROC glXGetConfig;
GLXWAITGLPROC glXWaitGL;
GLXWAITXPROC glXWaitX;
/* GLX 1.1 */
GLXQUERYEXTENSIONSSTRINGPROC glXQueryExtensionsString;
GLXQUERYSERVERSTRINGPROC glXQueryServerString;
GLXGETCLIENTSTRINGPROC glXGetClientString;
/* GLX 1.3 or (GLX_SGI_make_current_read and GLX_SGIX_fbconfig) */
PFNGLXGETFBCONFIGSPROC glXGetFBConfigs;
PFNGLXGETFBCONFIGATTRIBPROC glXGetFBConfigAttrib;
PFNGLXGETVISUALFROMFBCONFIGPROC glXGetVisualFromFBConfig;
PFNGLXCREATEWINDOWPROC glXCreateWindow;
PFNGLXDESTROYWINDOWPROC glXDestroyWindow;
PFNGLXCREATEPIXMAPPROC glXCreatePixmap;
PFNGLXDESTROYPIXMAPPROC glXDestroyPixmap;
PFNGLXCREATEPBUFFERPROC glXCreatePbuffer;
PFNGLXDESTROYPBUFFERPROC glXDestroyPbuffer;
PFNGLXCREATENEWCONTEXTPROC glXCreateNewContext;
PFNGLXMAKECONTEXTCURRENTPROC glXMakeContextCurrent;
/* GLX 1.4 or GLX_ARB_get_proc_address */
PFNGLXGETPROCADDRESSPROC glXGetProcAddress;
/* GLX_SGIX_pbuffer */
PFNGLXCREATEGLXPBUFFERSGIXPROC glXCreateGLXPbufferSGIX;
PFNGLXDESTROYGLXPBUFFERSGIXPROC glXDestroyGLXPbufferSGIX;
};
@ -76,14 +132,9 @@ struct GLX_egl_display
EGLBoolean have_fbconfig;
EGLBoolean have_pbuffer;
/* GLX_SGIX_pbuffer */
PFNGLXCREATEGLXPBUFFERSGIXPROC glXCreateGLXPbufferSGIX;
PFNGLXDESTROYGLXPBUFFERSGIXPROC glXDestroyGLXPbufferSGIX;
/* workaround quirks of different GLX implementations */
EGLBoolean single_buffered_quirk;
EGLBoolean glx_window_quirk;
};
@ -168,19 +219,21 @@ static const struct {
static EGLBoolean
convert_fbconfig(Display *dpy, GLXFBConfig fbconfig,
convert_fbconfig(struct GLX_egl_driver *GLX_drv,
struct GLX_egl_display *GLX_dpy, GLXFBConfig fbconfig,
struct GLX_egl_config *GLX_conf)
{
Display *dpy = GLX_dpy->dpy;
int err, attr, val;
unsigned i;
/* must have rgba bit */
err = glXGetFBConfigAttrib(dpy, fbconfig, GLX_RENDER_TYPE, &val);
err = GLX_drv->glXGetFBConfigAttrib(dpy, fbconfig, GLX_RENDER_TYPE, &val);
if (err || !(val & GLX_RGBA_BIT))
return EGL_FALSE;
/* must know whether it is double-buffered */
err = glXGetFBConfigAttrib(dpy, fbconfig, GLX_DOUBLEBUFFER, &val);
err = GLX_drv->glXGetFBConfigAttrib(dpy, fbconfig, GLX_DOUBLEBUFFER, &val);
if (err)
return EGL_FALSE;
GLX_conf->double_buffered = val;
@ -196,7 +249,7 @@ convert_fbconfig(Display *dpy, GLXFBConfig fbconfig,
if (!egl_attr)
continue;
err = glXGetFBConfigAttrib(dpy, fbconfig, attr, &val);
err = GLX_drv->glXGetFBConfigAttrib(dpy, fbconfig, attr, &val);
if (err) {
if (err == GLX_BAD_ATTRIBUTE) {
err = 0;
@ -303,21 +356,23 @@ static const struct {
};
static EGLBoolean
convert_visual(Display *dpy, XVisualInfo *vinfo,
convert_visual(struct GLX_egl_driver *GLX_drv,
struct GLX_egl_display *GLX_dpy, XVisualInfo *vinfo,
struct GLX_egl_config *GLX_conf)
{
Display *dpy = GLX_dpy->dpy;
int err, attr, val;
unsigned i;
/* the visual must support OpenGL and RGBA buffer */
err = glXGetConfig(dpy, vinfo, GLX_USE_GL, &val);
err = GLX_drv->glXGetConfig(dpy, vinfo, GLX_USE_GL, &val);
if (!err && val)
err = glXGetConfig(dpy, vinfo, GLX_RGBA, &val);
err = GLX_drv->glXGetConfig(dpy, vinfo, GLX_RGBA, &val);
if (err || !val)
return EGL_FALSE;
/* must know whether it is double-buffered */
err = glXGetConfig(dpy, vinfo, GLX_DOUBLEBUFFER, &val);
err = GLX_drv->glXGetConfig(dpy, vinfo, GLX_DOUBLEBUFFER, &val);
if (err)
return EGL_FALSE;
GLX_conf->double_buffered = val;
@ -341,7 +396,7 @@ convert_visual(Display *dpy, XVisualInfo *vinfo,
if (!egl_attr)
continue;
err = glXGetConfig(dpy, vinfo, attr, &val);
err = GLX_drv->glXGetConfig(dpy, vinfo, attr, &val);
if (err) {
if (err == GLX_BAD_ATTRIBUTE) {
err = 0;
@ -406,14 +461,16 @@ fix_config(struct GLX_egl_display *GLX_dpy, struct GLX_egl_config *GLX_conf)
static EGLBoolean
create_configs(_EGLDisplay *dpy, struct GLX_egl_display *GLX_dpy,
EGLint screen)
create_configs(_EGLDriver *drv, _EGLDisplay *dpy, EGLint screen)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_display *GLX_dpy = GLX_egl_display(dpy);
EGLint num_configs = 0, i;
EGLint id = 1;
if (GLX_dpy->have_fbconfig) {
GLX_dpy->fbconfigs = glXGetFBConfigs(GLX_dpy->dpy, screen, &num_configs);
GLX_dpy->fbconfigs =
GLX_drv->glXGetFBConfigs(GLX_dpy->dpy, screen, &num_configs);
}
else {
XVisualInfo vinfo_template;
@ -434,10 +491,14 @@ create_configs(_EGLDisplay *dpy, struct GLX_egl_display *GLX_dpy,
memset(&template, 0, sizeof(template));
_eglInitConfig(&template.Base, dpy, id);
if (GLX_dpy->have_fbconfig)
ok = convert_fbconfig(GLX_dpy->dpy, GLX_dpy->fbconfigs[i], &template);
else
ok = convert_visual(GLX_dpy->dpy, &GLX_dpy->visuals[i], &template);
if (GLX_dpy->have_fbconfig) {
ok = convert_fbconfig(GLX_drv, GLX_dpy,
GLX_dpy->fbconfigs[i], &template);
}
else {
ok = convert_visual(GLX_drv, GLX_dpy,
&GLX_dpy->visuals[i], &template);
}
if (!ok)
continue;
@ -462,13 +523,12 @@ create_configs(_EGLDisplay *dpy, struct GLX_egl_display *GLX_dpy,
static void
check_extensions(struct GLX_egl_display *GLX_dpy, EGLint screen)
check_extensions(struct GLX_egl_driver *GLX_drv,
struct GLX_egl_display *GLX_dpy, EGLint screen)
{
GLX_dpy->extensions =
glXQueryExtensionsString(GLX_dpy->dpy, screen);
GLX_drv->glXQueryExtensionsString(GLX_dpy->dpy, screen);
if (GLX_dpy->extensions) {
/* glXGetProcAddress is assumed */
if (strstr(GLX_dpy->extensions, "GLX_SGI_make_current_read")) {
/* GLX 1.3 entry points are used */
GLX_dpy->have_make_current_read = EGL_TRUE;
@ -480,13 +540,8 @@ check_extensions(struct GLX_egl_display *GLX_dpy, EGLint screen)
}
if (strstr(GLX_dpy->extensions, "GLX_SGIX_pbuffer")) {
GLX_dpy->glXCreateGLXPbufferSGIX = (PFNGLXCREATEGLXPBUFFERSGIXPROC)
glXGetProcAddress((const GLubyte *) "glXCreateGLXPbufferSGIX");
GLX_dpy->glXDestroyGLXPbufferSGIX = (PFNGLXDESTROYGLXPBUFFERSGIXPROC)
glXGetProcAddress((const GLubyte *) "glXDestroyGLXPbufferSGIX");
if (GLX_dpy->glXCreateGLXPbufferSGIX &&
GLX_dpy->glXDestroyGLXPbufferSGIX &&
if (GLX_drv->glXCreateGLXPbufferSGIX &&
GLX_drv->glXDestroyGLXPbufferSGIX &&
GLX_dpy->have_fbconfig)
GLX_dpy->have_pbuffer = EGL_TRUE;
}
@ -502,16 +557,17 @@ check_extensions(struct GLX_egl_display *GLX_dpy, EGLint screen)
static void
check_quirks(struct GLX_egl_display *GLX_dpy, EGLint screen)
check_quirks(struct GLX_egl_driver *GLX_drv,
struct GLX_egl_display *GLX_dpy, EGLint screen)
{
const char *vendor;
GLX_dpy->single_buffered_quirk = EGL_TRUE;
GLX_dpy->glx_window_quirk = EGL_TRUE;
vendor = glXGetClientString(GLX_dpy->dpy, GLX_VENDOR);
vendor = GLX_drv->glXGetClientString(GLX_dpy->dpy, GLX_VENDOR);
if (vendor && strstr(vendor, "NVIDIA")) {
vendor = glXQueryServerString(GLX_dpy->dpy, screen, GLX_VENDOR);
vendor = GLX_drv->glXQueryServerString(GLX_dpy->dpy, screen, GLX_VENDOR);
if (vendor && strstr(vendor, "NVIDIA")) {
_eglLog(_EGL_DEBUG, "disable quirks");
GLX_dpy->single_buffered_quirk = EGL_FALSE;
@ -528,10 +584,9 @@ static EGLBoolean
GLX_eglInitialize(_EGLDriver *drv, _EGLDisplay *disp,
EGLint *major, EGLint *minor)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_display *GLX_dpy;
(void) drv;
if (disp->Platform != _EGL_PLATFORM_X11)
return EGL_FALSE;
@ -549,7 +604,8 @@ GLX_eglInitialize(_EGLDriver *drv, _EGLDisplay *disp,
}
}
if (!glXQueryVersion(GLX_dpy->dpy, &GLX_dpy->glx_maj, &GLX_dpy->glx_min)) {
if (!GLX_drv->glXQueryVersion(GLX_dpy->dpy,
&GLX_dpy->glx_maj, &GLX_dpy->glx_min)) {
_eglLog(_EGL_WARNING, "GLX: glXQueryVersion failed");
if (!disp->PlatformDisplay)
XCloseDisplay(GLX_dpy->dpy);
@ -557,21 +613,21 @@ GLX_eglInitialize(_EGLDriver *drv, _EGLDisplay *disp,
return EGL_FALSE;
}
check_extensions(GLX_dpy, DefaultScreen(GLX_dpy->dpy));
check_quirks(GLX_dpy, DefaultScreen(GLX_dpy->dpy));
create_configs(disp, GLX_dpy, DefaultScreen(GLX_dpy->dpy));
if (!_eglGetArraySize(disp->Configs)) {
_eglLog(_EGL_WARNING, "GLX: failed to create any config");
if (!disp->PlatformDisplay)
XCloseDisplay(GLX_dpy->dpy);
free(GLX_dpy);
return EGL_FALSE;
}
disp->DriverData = (void *) GLX_dpy;
disp->ClientAPIsMask = EGL_OPENGL_BIT;
check_extensions(GLX_drv, GLX_dpy, DefaultScreen(GLX_dpy->dpy));
check_quirks(GLX_drv, GLX_dpy, DefaultScreen(GLX_dpy->dpy));
create_configs(drv, disp, DefaultScreen(GLX_dpy->dpy));
if (!_eglGetArraySize(disp->Configs)) {
_eglLog(_EGL_WARNING, "GLX: failed to create any config");
if (!disp->PlatformDisplay)
XCloseDisplay(GLX_dpy->dpy);
free(GLX_dpy);
return EGL_FALSE;
}
/* we're supporting EGL 1.4 */
*major = 1;
*minor = 4;
@ -579,6 +635,7 @@ GLX_eglInitialize(_EGLDriver *drv, _EGLDisplay *disp,
return EGL_TRUE;
}
/**
* Called via eglTerminate(), drv->API.Terminate().
*/
@ -612,12 +669,11 @@ static _EGLContext *
GLX_eglCreateContext(_EGLDriver *drv, _EGLDisplay *disp, _EGLConfig *conf,
_EGLContext *share_list, const EGLint *attrib_list)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_context *GLX_ctx = CALLOC_STRUCT(GLX_egl_context);
struct GLX_egl_display *GLX_dpy = GLX_egl_display(disp);
struct GLX_egl_context *GLX_ctx_shared = GLX_egl_context(share_list);
(void) drv;
if (!GLX_ctx) {
_eglError(EGL_BAD_ALLOC, "eglCreateContext");
return NULL;
@ -628,19 +684,19 @@ GLX_eglCreateContext(_EGLDriver *drv, _EGLDisplay *disp, _EGLConfig *conf,
return NULL;
}
if (GLX_dpy->have_fbconfig)
GLX_ctx->context =
glXCreateNewContext(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
GLX_RGBA_TYPE,
GLX_ctx_shared ? GLX_ctx_shared->context : NULL,
GL_TRUE);
else
GLX_ctx->context =
glXCreateContext(GLX_dpy->dpy,
&GLX_dpy->visuals[GLX_egl_config_index(conf)],
GLX_ctx_shared ? GLX_ctx_shared->context : NULL,
GL_TRUE);
if (GLX_dpy->have_fbconfig) {
GLX_ctx->context = GLX_drv->glXCreateNewContext(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
GLX_RGBA_TYPE,
GLX_ctx_shared ? GLX_ctx_shared->context : NULL,
GL_TRUE);
}
else {
GLX_ctx->context = GLX_drv->glXCreateContext(GLX_dpy->dpy,
&GLX_dpy->visuals[GLX_egl_config_index(conf)],
GLX_ctx_shared ? GLX_ctx_shared->context : NULL,
GL_TRUE);
}
if (!GLX_ctx->context) {
free(GLX_ctx);
return NULL;
@ -673,6 +729,7 @@ static EGLBoolean
GLX_eglMakeCurrent(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *dsurf,
_EGLSurface *rsurf, _EGLContext *ctx)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_display *GLX_dpy = GLX_egl_display(disp);
struct GLX_egl_surface *GLX_dsurf = GLX_egl_surface(dsurf);
struct GLX_egl_surface *GLX_rsurf = GLX_egl_surface(rsurf);
@ -683,8 +740,6 @@ GLX_eglMakeCurrent(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *dsurf,
GLXContext cctx;
EGLBoolean ret = EGL_FALSE;
(void) drv;
/* make new bindings */
if (!_eglBindContext(ctx, dsurf, rsurf, &old_ctx, &old_dsurf, &old_rsurf))
return EGL_FALSE;
@ -694,9 +749,9 @@ GLX_eglMakeCurrent(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *dsurf,
cctx = (GLX_ctx) ? GLX_ctx->context : NULL;
if (GLX_dpy->have_make_current_read)
ret = glXMakeContextCurrent(GLX_dpy->dpy, ddraw, rdraw, cctx);
ret = GLX_drv->glXMakeContextCurrent(GLX_dpy->dpy, ddraw, rdraw, cctx);
else if (ddraw == rdraw)
ret = glXMakeCurrent(GLX_dpy->dpy, ddraw, cctx);
ret = GLX_drv->glXMakeCurrent(GLX_dpy->dpy, ddraw, cctx);
if (ret) {
if (_eglPutSurface(old_dsurf))
@ -747,12 +802,11 @@ GLX_eglCreateWindowSurface(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf, EGLNativeWindowType window,
const EGLint *attrib_list)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_display *GLX_dpy = GLX_egl_display(disp);
struct GLX_egl_surface *GLX_surf;
uint width, height;
(void) drv;
GLX_surf = CALLOC_STRUCT(GLX_egl_surface);
if (!GLX_surf) {
_eglError(EGL_BAD_ALLOC, "eglCreateWindowSurface");
@ -767,13 +821,14 @@ GLX_eglCreateWindowSurface(_EGLDriver *drv, _EGLDisplay *disp,
GLX_surf->drawable = window;
if (GLX_dpy->have_1_3 && !GLX_dpy->glx_window_quirk)
GLX_surf->glx_drawable =
glXCreateWindow(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
GLX_surf->drawable, NULL);
else
if (GLX_dpy->have_1_3 && !GLX_dpy->glx_window_quirk) {
GLX_surf->glx_drawable = GLX_drv->glXCreateWindow(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
GLX_surf->drawable, NULL);
}
else {
GLX_surf->glx_drawable = GLX_surf->drawable;
}
if (!GLX_surf->glx_drawable) {
free(GLX_surf);
@ -781,7 +836,7 @@ GLX_eglCreateWindowSurface(_EGLDriver *drv, _EGLDisplay *disp,
}
if (GLX_dpy->have_1_3 && !GLX_dpy->glx_window_quirk)
GLX_surf->destroy = glXDestroyWindow;
GLX_surf->destroy = GLX_drv->glXDestroyWindow;
get_drawable_size(GLX_dpy->dpy, window, &width, &height);
GLX_surf->Base.Width = width;
@ -795,12 +850,11 @@ GLX_eglCreatePixmapSurface(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf, EGLNativePixmapType pixmap,
const EGLint *attrib_list)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_display *GLX_dpy = GLX_egl_display(disp);
struct GLX_egl_surface *GLX_surf;
uint width, height;
(void) drv;
GLX_surf = CALLOC_STRUCT(GLX_egl_surface);
if (!GLX_surf) {
_eglError(EGL_BAD_ALLOC, "eglCreatePixmapSurface");
@ -816,25 +870,25 @@ GLX_eglCreatePixmapSurface(_EGLDriver *drv, _EGLDisplay *disp,
GLX_surf->drawable = pixmap;
if (GLX_dpy->have_1_3) {
GLX_surf->glx_drawable =
glXCreatePixmap(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
GLX_surf->drawable, NULL);
GLX_surf->glx_drawable = GLX_drv->glXCreatePixmap(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
GLX_surf->drawable, NULL);
}
else if (GLX_dpy->have_fbconfig) {
GLXFBConfig fbconfig = GLX_dpy->fbconfigs[GLX_egl_config_index(conf)];
XVisualInfo *vinfo = glXGetVisualFromFBConfig(GLX_dpy->dpy, fbconfig);
XVisualInfo *vinfo;
vinfo = GLX_drv->glXGetVisualFromFBConfig(GLX_dpy->dpy, fbconfig);
if (vinfo) {
GLX_surf->glx_drawable =
glXCreateGLXPixmap(GLX_dpy->dpy, vinfo, GLX_surf->drawable);
GLX_surf->glx_drawable = GLX_drv->glXCreateGLXPixmap(GLX_dpy->dpy,
vinfo, GLX_surf->drawable);
XFree(vinfo);
}
}
else {
GLX_surf->glx_drawable =
glXCreateGLXPixmap(GLX_dpy->dpy,
&GLX_dpy->visuals[GLX_egl_config_index(conf)],
GLX_surf->drawable);
GLX_surf->glx_drawable = GLX_drv->glXCreateGLXPixmap(GLX_dpy->dpy,
&GLX_dpy->visuals[GLX_egl_config_index(conf)],
GLX_surf->drawable);
}
if (!GLX_surf->glx_drawable) {
@ -843,7 +897,7 @@ GLX_eglCreatePixmapSurface(_EGLDriver *drv, _EGLDisplay *disp,
}
GLX_surf->destroy = (GLX_dpy->have_1_3) ?
glXDestroyPixmap : glXDestroyGLXPixmap;
GLX_drv->glXDestroyPixmap : GLX_drv->glXDestroyGLXPixmap;
get_drawable_size(GLX_dpy->dpy, pixmap, &width, &height);
GLX_surf->Base.Width = width;
@ -856,13 +910,12 @@ static _EGLSurface *
GLX_eglCreatePbufferSurface(_EGLDriver *drv, _EGLDisplay *disp,
_EGLConfig *conf, const EGLint *attrib_list)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_display *GLX_dpy = GLX_egl_display(disp);
struct GLX_egl_surface *GLX_surf;
int attribs[5];
int i;
(void) drv;
GLX_surf = CALLOC_STRUCT(GLX_egl_surface);
if (!GLX_surf) {
_eglError(EGL_BAD_ALLOC, "eglCreatePbufferSurface");
@ -892,14 +945,11 @@ GLX_eglCreatePbufferSurface(_EGLDriver *drv, _EGLDisplay *disp,
}
attribs[i] = None;
GLX_surf->glx_drawable =
glXCreatePbuffer(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
attribs);
GLX_surf->glx_drawable = GLX_drv->glXCreatePbuffer(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)], attribs);
}
else if (GLX_dpy->have_pbuffer) {
GLX_surf->glx_drawable = GLX_dpy->glXCreateGLXPbufferSGIX(
GLX_dpy->dpy,
GLX_surf->glx_drawable = GLX_drv->glXCreateGLXPbufferSGIX(GLX_dpy->dpy,
GLX_dpy->fbconfigs[GLX_egl_config_index(conf)],
GLX_surf->Base.Width,
GLX_surf->Base.Height,
@ -912,7 +962,7 @@ GLX_eglCreatePbufferSurface(_EGLDriver *drv, _EGLDisplay *disp,
}
GLX_surf->destroy = (GLX_dpy->have_1_3) ?
glXDestroyPbuffer : GLX_dpy->glXDestroyGLXPbufferSGIX;
GLX_drv->glXDestroyPbuffer : GLX_drv->glXDestroyGLXPbufferSGIX;
return &GLX_surf->Base;
}
@ -933,12 +983,11 @@ GLX_eglDestroySurface(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *surf)
static EGLBoolean
GLX_eglSwapBuffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
struct GLX_egl_display *GLX_dpy = GLX_egl_display(disp);
struct GLX_egl_surface *GLX_surf = GLX_egl_surface(draw);
(void) drv;
glXSwapBuffers(GLX_dpy->dpy, GLX_surf->glx_drawable);
GLX_drv->glXSwapBuffers(GLX_dpy->dpy, GLX_surf->glx_drawable);
return EGL_TRUE;
}
@ -949,31 +998,33 @@ GLX_eglSwapBuffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
static _EGLProc
GLX_eglGetProcAddress(_EGLDriver *drv, const char *procname)
{
(void) drv;
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
return (_EGLProc) glXGetProcAddress((const GLubyte *) procname);
return (_EGLProc) GLX_drv->glXGetProcAddress((const GLubyte *) procname);
}
static EGLBoolean
GLX_eglWaitClient(_EGLDriver *drv, _EGLDisplay *dpy, _EGLContext *ctx)
{
(void) drv;
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
(void) dpy;
(void) ctx;
glXWaitGL();
GLX_drv->glXWaitGL();
return EGL_TRUE;
}
static EGLBoolean
GLX_eglWaitNative(_EGLDriver *drv, _EGLDisplay *dpy, EGLint engine)
{
(void) drv;
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
(void) dpy;
if (engine != EGL_CORE_NATIVE_ENGINE)
return _eglError(EGL_BAD_PARAMETER, "eglWaitNative");
glXWaitX();
GLX_drv->glXWaitX();
return EGL_TRUE;
}
@ -981,16 +1032,90 @@ static void
GLX_Unload(_EGLDriver *drv)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
if (GLX_drv->handle)
dlclose(GLX_drv->handle);
free(GLX_drv);
}
static EGLBoolean
GLX_Load(_EGLDriver *drv)
{
struct GLX_egl_driver *GLX_drv = GLX_egl_driver(drv);
void *handle;
handle = dlopen("libGL.so", RTLD_LAZY | RTLD_LOCAL);
if (!handle)
goto fail;
GLX_drv->glXGetProcAddress = dlsym(handle, "glXGetProcAddress");
if (!GLX_drv->glXGetProcAddress)
GLX_drv->glXGetProcAddress = dlsym(handle, "glXGetProcAddressARB");
if (!GLX_drv->glXGetProcAddress)
goto fail;
#define GET_PROC(proc_type, proc_name, check) \
do { \
GLX_drv->proc_name = (proc_type) \
GLX_drv->glXGetProcAddress((const GLubyte *) #proc_name); \
if (check && !GLX_drv->proc_name) goto fail; \
} while (0)
/* GLX 1.0 */
GET_PROC(GLXCREATECONTEXTPROC, glXCreateContext, EGL_TRUE);
GET_PROC(GLXDESTROYCONTEXTPROC, glXDestroyContext, EGL_TRUE);
GET_PROC(GLXMAKECURRENTPROC, glXMakeCurrent, EGL_TRUE);
GET_PROC(GLXSWAPBUFFERSPROC, glXSwapBuffers, EGL_TRUE);
GET_PROC(GLXCREATEGLXPIXMAPPROC, glXCreateGLXPixmap, EGL_TRUE);
GET_PROC(GLXDESTROYGLXPIXMAPPROC, glXDestroyGLXPixmap, EGL_TRUE);
GET_PROC(GLXQUERYVERSIONPROC, glXQueryVersion, EGL_TRUE);
GET_PROC(GLXGETCONFIGPROC, glXGetConfig, EGL_TRUE);
GET_PROC(GLXWAITGLPROC, glXWaitGL, EGL_TRUE);
GET_PROC(GLXWAITXPROC, glXWaitX, EGL_TRUE);
/* GLX 1.1 */
GET_PROC(GLXQUERYEXTENSIONSSTRINGPROC, glXQueryExtensionsString, EGL_TRUE);
GET_PROC(GLXQUERYSERVERSTRINGPROC, glXQueryServerString, EGL_TRUE);
GET_PROC(GLXGETCLIENTSTRINGPROC, glXGetClientString, EGL_TRUE);
/* GLX 1.3 */
GET_PROC(PFNGLXGETFBCONFIGSPROC, glXGetFBConfigs, EGL_FALSE);
GET_PROC(PFNGLXGETFBCONFIGATTRIBPROC, glXGetFBConfigAttrib, EGL_FALSE);
GET_PROC(PFNGLXGETVISUALFROMFBCONFIGPROC, glXGetVisualFromFBConfig, EGL_FALSE);
GET_PROC(PFNGLXCREATEWINDOWPROC, glXCreateWindow, EGL_FALSE);
GET_PROC(PFNGLXDESTROYWINDOWPROC, glXDestroyWindow, EGL_FALSE);
GET_PROC(PFNGLXCREATEPIXMAPPROC, glXCreatePixmap, EGL_FALSE);
GET_PROC(PFNGLXDESTROYPIXMAPPROC, glXDestroyPixmap, EGL_FALSE);
GET_PROC(PFNGLXCREATEPBUFFERPROC, glXCreatePbuffer, EGL_FALSE);
GET_PROC(PFNGLXDESTROYPBUFFERPROC, glXDestroyPbuffer, EGL_FALSE);
GET_PROC(PFNGLXCREATENEWCONTEXTPROC, glXCreateNewContext, EGL_FALSE);
GET_PROC(PFNGLXMAKECONTEXTCURRENTPROC, glXMakeContextCurrent, EGL_FALSE);
/* GLX_SGIX_pbuffer */
GET_PROC(PFNGLXCREATEGLXPBUFFERSGIXPROC,
glXCreateGLXPbufferSGIX, EGL_FALSE);
GET_PROC(PFNGLXDESTROYGLXPBUFFERSGIXPROC,
glXDestroyGLXPbufferSGIX, EGL_FALSE);
#undef GET_PROC
GLX_drv->handle = handle;
return EGL_TRUE;
fail:
if (handle)
dlclose(handle);
return EGL_FALSE;
}
/**
* This is the main entrypoint into the driver, called by libEGL.
* Create a new _EGLDriver object and init its dispatch table.
*/
_EGLDriver *
_eglMain(const char *args)
_EGL_MAIN(const char *args)
{
struct GLX_egl_driver *GLX_drv = CALLOC_STRUCT(GLX_egl_driver);
@ -999,6 +1124,12 @@ _eglMain(const char *args)
if (!GLX_drv)
return NULL;
if (!GLX_Load(&GLX_drv->Base)) {
_eglLog(_EGL_WARNING, "GLX: failed to load GLX");
free(GLX_drv);
return NULL;
}
_eglInitDriverFallbacks(&GLX_drv->Base);
GLX_drv->Base.API.Initialize = GLX_eglInitialize;
GLX_drv->Base.API.Terminate = GLX_eglTerminate;

16
src/egl/main/Makefile
View file

@ -52,6 +52,19 @@ OBJECTS = $(SOURCES:.c=.o)
# use dl*() to load drivers
LOCAL_CFLAGS = -D_EGL_OS_UNIX=1
LOCAL_LIBS =
# egl_dri2 and egl_glx are built-ins
ifeq ($(filter dri2, $(EGL_DRIVERS_DIRS)),dri2)
LOCAL_CFLAGS += -D_EGL_BUILT_IN_DRIVER_DRI2
LOCAL_LIBS += $(TOP)/src/egl/drivers/dri2/libegl_dri2.a
EGL_LIB_DEPS += $(XCB_DRI2_LIBS) $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIB)
endif
ifeq ($(filter glx, $(EGL_DRIVERS_DIRS)),glx)
LOCAL_CFLAGS += -D_EGL_BUILT_IN_DRIVER_GLX
LOCAL_LIBS += $(TOP)/src/egl/drivers/glx/libegl_glx.a
EGL_LIB_DEPS += $(X11_LIBS) $(DLOPEN_LIBS)
endif
# translate --with-egl-platforms to _EGLPlatformType
EGL_NATIVE_PLATFORM=_EGL_INVALID_PLATFORM
@ -84,7 +97,8 @@ $(TOP)/$(LIB_DIR)/$(EGL_LIB_NAME): $(OBJECTS)
$(MKLIB) -o $(EGL_LIB) -linker '$(CC)' -ldflags '$(LDFLAGS)' \
-major $(EGL_MAJOR) -minor $(EGL_MINOR) \
-install $(TOP)/$(LIB_DIR) $(MKLIB_OPTIONS) \
$(EGL_LIB_DEPS) $(OBJECTS)
-L$(TOP)/$(LIB_DIR) $(EGL_LIB_DEPS) \
$(OBJECTS) $(LOCAL_LIBS)
install-headers:
$(INSTALL) -d $(DESTDIR)$(INSTALL_INC_DIR)/KHR

135
src/egl/main/egldriver.c
View file

@ -25,6 +25,7 @@
typedef struct _egl_module {
char *Path;
_EGLMain_t BuiltIn;
void *Handle;
_EGLDriver *Driver;
} _EGLModule;
@ -32,6 +33,18 @@ typedef struct _egl_module {
static _EGL_DECLARE_MUTEX(_eglModuleMutex);
static _EGLArray *_eglModules;
const struct {
const char *name;
_EGLMain_t main;
} _eglBuiltInDrivers[] = {
#ifdef _EGL_BUILT_IN_DRIVER_DRI2
{ "egl_dri2", _eglBuiltInDriverDRI2 },
#endif
#ifdef _EGL_BUILT_IN_DRIVER_GLX
{ "egl_glx", _eglBuiltInDriverGLX },
#endif
{ NULL, NULL }
};
/**
* Wrappers for dlopen/dlclose()
@ -157,9 +170,18 @@ _eglLoadModule(_EGLModule *mod)
lib_handle lib;
_EGLDriver *drv;
mainFunc = _eglOpenLibrary(mod->Path, &lib);
if (!mainFunc)
return EGL_FALSE;
if (mod->Driver)
return EGL_TRUE;
if (mod->BuiltIn) {
lib = (lib_handle) NULL;
mainFunc = mod->BuiltIn;
}
else {
mainFunc = _eglOpenLibrary(mod->Path, &lib);
if (!mainFunc)
return EGL_FALSE;
}
drv = mainFunc(NULL);
if (!drv) {
@ -312,68 +334,6 @@ _eglLoaderFile(const char *dir, size_t len, void *loader_data)
}
/**
* A loader function for use with _eglPreloadForEach. The loader data is the
* pattern (prefix) of the files to look for.
*/
static EGLBoolean
_eglLoaderPattern(const char *dir, size_t len, void *loader_data)
{
#if defined(_EGL_OS_UNIX)
const char *prefix, *suffix;
size_t prefix_len, suffix_len;
DIR *dirp;
struct dirent *dirent;
char path[1024];
if (len + 2 > sizeof(path))
return EGL_TRUE;
if (len) {
memcpy(path, dir, len);
path[len++] = '/';
}
path[len] = '\0';
dirp = opendir(path);
if (!dirp)
return EGL_TRUE;
prefix = (const char *) loader_data;
prefix_len = strlen(prefix);
suffix = library_suffix();
suffix_len = (suffix) ? strlen(suffix) : 0;
while ((dirent = readdir(dirp))) {
size_t dirent_len = strlen(dirent->d_name);
const char *p;
/* match the prefix */
if (strncmp(dirent->d_name, prefix, prefix_len) != 0)
continue;
/* match the suffix */
if (suffix) {
p = dirent->d_name + dirent_len - suffix_len;
if (p < dirent->d_name || strcmp(p, suffix) != 0)
continue;
}
/* make a full path and add it to the module array */
if (len + dirent_len + 1 <= sizeof(path)) {
strcpy(path + len, dirent->d_name);
_eglAddModule(path);
}
}
closedir(dirp);
return EGL_TRUE;
#else /* _EGL_OS_UNIX */
/* stop immediately */
return EGL_FALSE;
#endif
}
/**
* Run the callback function on each driver directory.
*
@ -489,34 +449,37 @@ _eglAddUserDriver(void)
}
}
#endif /* _EGL_OS_UNIX */
if (env)
if (env) {
_EGLModule *mod;
EGLint i;
/* env can be a path */
_eglPreloadForEach(search_path, _eglLoaderFile, (void *) env);
/* or the name of a built-in driver */
for (i = 0; _eglBuiltInDrivers[i].name; i++) {
if (!strcmp(_eglBuiltInDrivers[i].name, env)) {
mod = _eglAddModule(env);
if (mod)
mod->BuiltIn = _eglBuiltInDrivers[i].main;
}
}
}
}
/**
* Add default drivers to the module array.
* Add built-in drivers to the module array.
*/
static void
_eglAddDefaultDrivers(void)
_eglAddBuiltInDrivers(void)
{
const char *search_path = _eglGetSearchPath();
_EGLModule *mod;
EGLint i;
#if defined(_EGL_OS_WINDOWS)
const char *DefaultDriverNames[] = {
"egl_gallium"
};
#elif defined(_EGL_OS_UNIX)
const char *DefaultDriverNames[] = {
"egl_gallium",
"egl_dri2",
"egl_glx"
};
#endif
for (i = 0; i < ARRAY_SIZE(DefaultDriverNames); i++) {
void *name = (void *) DefaultDriverNames[i];
_eglPreloadForEach(search_path, _eglLoaderFile, name);
for (i = 0; _eglBuiltInDrivers[i].name; i++) {
mod = _eglAddModule(_eglBuiltInDrivers[i].name);
if (mod)
mod->BuiltIn = _eglBuiltInDrivers[i].main;
}
}
@ -528,13 +491,15 @@ _eglAddDefaultDrivers(void)
static EGLBoolean
_eglAddDrivers(void)
{
void *external = (void *) "egl_gallium";
if (_eglModules)
return EGL_TRUE;
/* the order here decides the priorities of the drivers */
_eglAddUserDriver();
_eglAddDefaultDrivers();
_eglPreloadForEach(_eglGetSearchPath(), _eglLoaderPattern, (void *) "egl_");
_eglPreloadForEach(_eglGetSearchPath(), _eglLoaderFile, external);
_eglAddBuiltInDrivers();
return (_eglModules != NULL);
}

8
src/egl/main/egldriver.h
View file

@ -64,6 +64,14 @@ struct _egl_driver
};
extern _EGLDriver *
_eglBuiltInDriverDRI2(const char *args);
extern _EGLDriver *
_eglBuiltInDriverGLX(const char *args);
PUBLIC _EGLDriver *
_eglMain(const char *args);

51
src/gallium/auxiliary/target-helpers/inline_noop_helper.h Normal file
View file

@ -0,0 +1,51 @@
#ifndef INLINE_DEBUG_HELPER_H
#define INLINE_DEBUG_HELPER_H
#include "pipe/p_compiler.h"
#include "util/u_debug.h"
/* Helper function to wrap a screen with
* one or more debug driver: rbug, trace.
*/
#ifdef GALLIUM_TRACE
#include "trace/tr_public.h"
#endif
#ifdef GALLIUM_RBUG
#include "rbug/rbug_public.h"
#endif
#ifdef GALLIUM_GALAHAD
#include "galahad/glhd_public.h"
#endif
#ifdef GALLIUM_NOOP
#include "noop/noop_public.h"
#endif
static INLINE struct pipe_screen *
debug_screen_wrap(struct pipe_screen *screen)
{
#if defined(GALLIUM_RBUG)
screen = rbug_screen_create(screen);
#endif
#if defined(GALLIUM_TRACE)
screen = trace_screen_create(screen);
#endif
#if defined(GALLIUM_GALAHAD)
screen = galahad_screen_create(screen);
#endif
#if defined(GALLIUM_NOOP)
screen = noop_screen_create(screen);
#endif
return screen;
}
#endif

4
src/gallium/drivers/i965/brw_batchbuffer.c
View file

@ -64,13 +64,11 @@ brw_batchbuffer_reset(struct brw_batchbuffer *batch)
}
struct brw_batchbuffer *
brw_batchbuffer_alloc(struct brw_winsys_screen *sws,
struct brw_chipset chipset)
brw_batchbuffer_alloc(struct brw_winsys_screen *sws)
{
struct brw_batchbuffer *batch = CALLOC_STRUCT(brw_batchbuffer);
batch->sws = sws;
batch->chipset = chipset;
brw_batchbuffer_reset(batch);
return batch;

5
src/gallium/drivers/i965/brw_batchbuffer.h
View file

@ -26,7 +26,6 @@ struct brw_batchbuffer {
struct brw_winsys_screen *sws;
struct brw_winsys_buffer *buf;
struct brw_chipset chipset;
/**
* Values exported to speed up the writing the batchbuffer,
@ -47,8 +46,8 @@ struct brw_batchbuffer {
/*@}*/
};
struct brw_batchbuffer *brw_batchbuffer_alloc( struct brw_winsys_screen *sws,
struct brw_chipset chipset );
struct brw_batchbuffer *brw_batchbuffer_alloc( struct brw_winsys_screen *sws );
void brw_batchbuffer_free(struct brw_batchbuffer *batch);

6
src/gallium/drivers/i965/brw_clip.c
View file

@ -66,16 +66,14 @@ compile_clip_prog( struct brw_context *brw,
c.func.single_program_flow = 1;
c.chipset = brw->chipset;
c.key = *key;
c.need_ff_sync = c.chipset.is_igdng;
/* Need to locate the two positions present in vertex + header.
* These are currently hardcoded:
*/
c.header_position_offset = ATTR_SIZE;
if (c.chipset.is_igdng)
if (brw->gen == 5)
delta = 3 * REG_SIZE;
else
delta = REG_SIZE;
@ -97,7 +95,7 @@ compile_clip_prog( struct brw_context *brw,
if (c.key.output_edgeflag != BRW_OUTPUT_NOT_PRESENT)
c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
c.nr_regs = (c.key.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
else
c.nr_regs = (c.key.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */

2
src/gallium/drivers/i965/brw_clip.h
View file

@ -125,12 +125,10 @@ struct brw_clip_compile {
GLuint last_tmp;
GLboolean need_direction;
struct brw_chipset chipset;
GLuint last_mrf;
GLuint header_position_offset;
GLboolean need_ff_sync;
GLuint nr_color_attrs;
GLuint offset_color0;

14
src/gallium/drivers/i965/brw_clip_line.c
View file

@ -32,6 +32,7 @@
#include "util/u_debug.h"
#include "brw_defines.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_clip.h"
@ -41,7 +42,7 @@
static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
{
GLuint i = 0,j;
struct brw_context *brw = c->func.brw;
/* Register usage is static, precompute here:
*/
c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
@ -79,7 +80,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
i++;
}
if (c->need_ff_sync) {
if (brw->needs_ff_sync) {
c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
i++;
}
@ -120,6 +121,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
static void clip_and_emit_line( struct brw_clip_compile *c )
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
struct brw_indirect vtx0 = brw_indirect(0, 0);
struct brw_indirect vtx1 = brw_indirect(1, 0);
struct brw_indirect newvtx0 = brw_indirect(2, 0);
@ -146,7 +148,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_clip_init_clipmask(c);
/* -ve rhw workaround */
if (c->chipset.is_965) {
if (brw->has_negative_rhw_bug) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
@ -183,7 +185,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
* Both can be negative on GM965/G965 due to RHW workaround
* if so, this object should be rejected.
*/
if (c->chipset.is_965) {
if (brw->has_negative_rhw_bug) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0));
is_neg2 = brw_IF(p, BRW_EXECUTE_1);
{
@ -208,7 +210,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
/* If both are positive, do nothing */
/* Only on GM965/G965 */
if (c->chipset.is_965) {
if (brw->has_negative_rhw_bug) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
is_neg2 = brw_IF(p, BRW_EXECUTE_1);
}
@ -223,7 +225,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
if (c->chipset.is_965) {
if (brw->has_negative_rhw_bug) {
brw_ENDIF(p, is_neg2);
}
}

4
src/gallium/drivers/i965/brw_clip_state.c
View file

@ -109,7 +109,7 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Although up to 16 concurrent Clip threads are allowed on IGDNG,
* only 2 threads can output VUEs at a time.
*/
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
clip.thread4.max_threads = 16 - 1;
else
clip.thread4.max_threads = 2 - 1;
@ -134,7 +134,7 @@ clip_unit_create_from_key(struct brw_context *brw,
clip.clip5.api_mode = BRW_CLIP_API_OGL;
clip.clip5.clip_mode = key->clip_mode;
if (BRW_IS_G4X(brw))
if (brw->is_g4x)
clip.clip5.negative_w_clip_test = 1;
clip.clip6.clipper_viewport_state_ptr = 0;

8
src/gallium/drivers/i965/brw_clip_tri.c
View file

@ -30,6 +30,7 @@
*/
#include "brw_defines.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_clip.h"
@ -43,6 +44,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
GLuint nr_verts )
{
GLuint i = 0,j;
struct brw_context *brw = c->func.brw;
/* Register usage is static, precompute here:
*/
@ -69,7 +71,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
for (j = 0; j < 3; j++) {
GLuint delta = c->key.nr_attrs*16 + 32;
if (c->chipset.is_igdng)
if (brw->gen == 5)
delta = c->key.nr_attrs * 16 + 32 * 3;
brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
@ -110,7 +112,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
i++;
}
if (c->need_ff_sync) {
if (brw->needs_ff_sync) {
c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
i++;
}
@ -563,7 +565,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
/* if -ve rhw workaround bit is set,
do cliptest */
if (c->chipset.is_965) {
if (p->brw->has_negative_rhw_bug) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));

12
src/gallium/drivers/i965/brw_clip_util.c
View file

@ -31,6 +31,7 @@
#include "brw_defines.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_clip.h"
@ -126,6 +127,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
GLboolean force_edgeflag)
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
struct brw_reg tmp = get_tmp(c);
GLuint i;
@ -142,7 +144,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
for (i = 0; i < c->key.nr_attrs; i++) {
GLuint delta = i*16 + 32;
if (c->chipset.is_igdng)
if (brw->gen == 5)
delta = i * 16 + 32 * 3;
if (delta == c->offset_edgeflag) {
@ -176,7 +178,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
if (i & 1) {
GLuint delta = i*16 + 32;
if (c->chipset.is_igdng)
if (brw->gen == 5)
delta = i * 16 + 32 * 3;
brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
@ -350,7 +352,8 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
void brw_clip_ff_sync(struct brw_clip_compile *c)
{
if (c->need_ff_sync) {
struct brw_context *brw = c->func.brw;
if (brw->needs_ff_sync) {
struct brw_compile *p = &c->func;
struct brw_instruction *need_ff_sync;
@ -379,7 +382,8 @@ void brw_clip_ff_sync(struct brw_clip_compile *c)
void brw_clip_init_ff_sync(struct brw_clip_compile *c)
{
if (c->need_ff_sync) {
struct brw_context *brw = c->func.brw;
if (brw->needs_ff_sync) {
struct brw_compile *p = &c->func;
brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0));

9
src/gallium/drivers/i965/brw_context.c
View file

@ -107,7 +107,7 @@ struct pipe_context *brw_create_context(struct pipe_screen *screen,
void *priv)
{
struct brw_context *brw = (struct brw_context *) CALLOC_STRUCT(brw_context);
struct brw_screen *brs = brw_screen(screen);
if (!brw) {
debug_printf("%s: failed to alloc context\n", __FUNCTION__);
return NULL;
@ -117,7 +117,10 @@ struct pipe_context *brw_create_context(struct pipe_screen *screen,
brw->base.priv = priv;
brw->base.destroy = brw_destroy_context;
brw->sws = brw_screen(screen)->sws;
brw->chipset = brw_screen(screen)->chipset;
brw->is_g4x = brs->is_g4x;
brw->needs_ff_sync = brs->needs_ff_sync;
brw->has_negative_rhw_bug = brs->has_negative_rhw_bug;
brw->gen = brs->gen;
brw_init_resource_functions( brw );
brw_pipe_blend_init( brw );
@ -145,7 +148,7 @@ struct pipe_context *brw_create_context(struct pipe_screen *screen,
make_empty_list(&brw->query.active_head);
brw->batch = brw_batchbuffer_alloc( brw->sws, brw->chipset );
brw->batch = brw_batchbuffer_alloc( brw->sws );
if (brw->batch == NULL)
goto fail;

15
src/gallium/drivers/i965/brw_context.h
View file

@ -529,7 +529,14 @@ struct brw_query_object {
struct brw_context
{
struct pipe_context base;
struct brw_chipset chipset;
int gen;
boolean has_negative_rhw_bug;
boolean needs_ff_sync;
boolean is_g4x;
int urb_size;
int vs_max_threads;
int wm_max_threads;
struct brw_winsys_screen *sws;
@ -854,11 +861,5 @@ brw_context( struct pipe_context *ctx )
return (struct brw_context *)ctx;
}
#define BRW_IS_965(brw) ((brw)->chipset.is_965)
#define BRW_IS_IGDNG(brw) ((brw)->chipset.is_igdng)
#define BRW_IS_G4X(brw) ((brw)->chipset.is_g4x)
#endif

359
src/gallium/drivers/i965/brw_defines.h
View file

@ -463,6 +463,13 @@
#define BRW_COMPRESSION_2NDHALF 1
#define BRW_COMPRESSION_COMPRESSED 2
#define GEN6_COMPRESSION_1Q 0
#define GEN6_COMPRESSION_2Q 1
#define GEN6_COMPRESSION_3Q 2
#define GEN6_COMPRESSION_4Q 3
#define GEN6_COMPRESSION_1H 0
#define GEN6_COMPRESSION_2H 2
#define BRW_CONDITIONAL_NONE 0
#define BRW_CONDITIONAL_Z 1
#define BRW_CONDITIONAL_NZ 2
@ -502,6 +509,27 @@
#define BRW_MASK_ENABLE 0
#define BRW_MASK_DISABLE 1
/** @{
*
* Gen6 has replaced "mask enable/disable" with WECtrl, which is
* effectively the same but much simpler to think about. Now, there
* are two contributors ANDed together to whether channels are
* executed: The predication on the instruction, and the channel write
* enable.
*/
/**
* This is the default value. It means that a channel's write enable is set
* if the per-channel IP is pointing at this instruction.
*/
#define BRW_WE_NORMAL 0
/**
* This is used like BRW_MASK_DISABLE, and causes all channels to have
* their write enable set. Note that predication still contributes to
* whether the channel actually gets written.
*/
#define BRW_WE_ALL 1
/** @} */
#define BRW_OPCODE_MOV 1
#define BRW_OPCODE_SEL 2
#define BRW_OPCODE_NOT 4
@ -531,6 +559,8 @@
#define BRW_OPCODE_POP 47
#define BRW_OPCODE_WAIT 48
#define BRW_OPCODE_SEND 49
#define BRW_OPCODE_SENDC 50
#define BRW_OPCODE_MATH 56
#define BRW_OPCODE_ADD 64
#define BRW_OPCODE_MUL 65
#define BRW_OPCODE_AVG 66
@ -550,6 +580,7 @@
#define BRW_OPCODE_DP2 87
#define BRW_OPCODE_DPA2 88
#define BRW_OPCODE_LINE 89
#define BRW_OPCODE_PLN 90
#define BRW_OPCODE_NOP 126
#define BRW_PREDICATE_NONE 0
@ -599,6 +630,8 @@
#define BRW_ARF_NOTIFICATION_COUNT 0x90
#define BRW_ARF_IP 0xA0
#define BRW_MRF_COMPR4 (1 << 7)
#define BRW_AMASK 0
#define BRW_IMASK 1
#define BRW_LMASK 2
@ -645,13 +678,14 @@
#define BRW_POLYGON_FACING_BACK 1
#define BRW_MESSAGE_TARGET_NULL 0
#define BRW_MESSAGE_TARGET_MATH 1
#define BRW_MESSAGE_TARGET_MATH 1 /* reserved on GEN6 */
#define BRW_MESSAGE_TARGET_SAMPLER 2
#define BRW_MESSAGE_TARGET_GATEWAY 3
#define BRW_MESSAGE_TARGET_DATAPORT_READ 4
#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5
#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 /* sampler cache on GEN6 */
#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 /* render cache on Gen6 */
#define BRW_MESSAGE_TARGET_URB 6
#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7
#define BRW_MESSAGE_TARGET_CONST_CACHE 9 /* GEN6 */
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
@ -674,20 +708,15 @@
#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_IGDNG 0
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_IGDNG 0
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_IGDNG 0
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_IGDNG 1
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_BIAS_IGDNG 1
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS_IGDNG 1
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_IGDNG 2
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_IGDNG 2
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD_IGDNG 2
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_COMPARE_IGDNG 3
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE_IGDNG 3
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE_IGDNG 3
#define BRW_SAMPLER_MESSAGE_SAMPLE_GEN5 0
#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5 1
#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_GEN5 2
#define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5 3
#define BRW_SAMPLER_MESSAGE_SAMPLE_DERIVS_GEN5 4
#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5 5
#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE_GEN5 6
/* for IGDNG only */
/* for GEN5 only */
#define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
#define BRW_SAMPLER_SIMD_MODE_SIMD8 1
#define BRW_SAMPLER_SIMD_MODE_SIMD16 2
@ -705,10 +734,24 @@
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
/* This one stays the same across generations. */
#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
/* GEN4 */
#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2
#define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
/* G45, GEN5 */
#define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
#define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
#define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
#define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
#define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
/* GEN6 */
#define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
#define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
#define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
#define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
#define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
@ -728,6 +771,16 @@
#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
/* GEN6 */
#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE_GEN6 7
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE_GEN6 8
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE_GEN6 9
#define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE_GEN6 10
#define BRW_DATAPORT_WRITE_MESSAGE_DWORLD_SCATTERED_WRITE_GEN6 11
#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6 12
#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE_GEN6 13
#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE_GEN6 14
#define BRW_MATH_FUNCTION_INV 1
#define BRW_MATH_FUNCTION_LOG 2
#define BRW_MATH_FUNCTION_EXP 3
@ -736,7 +789,8 @@
#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */
#define BRW_MATH_FUNCTION_COS 7 /* was 8 */
#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */
#define BRW_MATH_FUNCTION_TAN 9
#define BRW_MATH_FUNCTION_TAN 9 /* gen4 */
#define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
#define BRW_MATH_FUNCTION_POW 10
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
@ -787,17 +841,33 @@
#define CMD_PIPELINED_STATE_POINTERS 0x7800
#define CMD_BINDING_TABLE_PTRS 0x7801
# define GEN6_BINDING_TABLE_MODIFY_VS (1 << 8)
# define GEN6_BINDING_TABLE_MODIFY_GS (1 << 9)
# define GEN6_BINDING_TABLE_MODIFY_PS (1 << 12)
#define CMD_3D_SAMPLER_STATE_POINTERS 0x7802 /* SNB+ */
# define PS_SAMPLER_STATE_CHANGE (1 << 12)
# define GS_SAMPLER_STATE_CHANGE (1 << 9)
# define VS_SAMPLER_STATE_CHANGE (1 << 8)
/* DW1: VS */
/* DW2: GS */
/* DW3: PS */
#define CMD_VERTEX_BUFFER 0x7808
# define BRW_VB0_INDEX_SHIFT 27
# define GEN6_VB0_INDEX_SHIFT 26
# define BRW_VB0_ACCESS_VERTEXDATA (0 << 26)
# define BRW_VB0_ACCESS_INSTANCEDATA (1 << 26)
# define GEN6_VB0_ACCESS_VERTEXDATA (0 << 20)
# define GEN6_VB0_ACCESS_INSTANCEDATA (1 << 20)
# define BRW_VB0_PITCH_SHIFT 0
#define CMD_VERTEX_ELEMENT 0x7809
# define BRW_VE0_INDEX_SHIFT 27
# define GEN6_VE0_INDEX_SHIFT 26
# define BRW_VE0_FORMAT_SHIFT 16
# define BRW_VE0_VALID (1 << 26)
# define GEN6_VE0_VALID (1 << 25)
# define BRW_VE0_SRC_OFFSET_SHIFT 0
# define BRW_VE1_COMPONENT_NOSTORE 0
# define BRW_VE1_COMPONENT_STORE_SRC 1
@ -816,6 +886,236 @@
#define CMD_INDEX_BUFFER 0x780a
#define CMD_VF_STATISTICS_965 0x780b
#define CMD_VF_STATISTICS_GM45 0x680b
#define CMD_3D_CC_STATE_POINTERS 0x780e /* GEN6+ */
#define CMD_URB 0x7805 /* GEN6+ */
# define GEN6_URB_VS_SIZE_SHIFT 16
# define GEN6_URB_VS_ENTRIES_SHIFT 0
# define GEN6_URB_GS_ENTRIES_SHIFT 8
# define GEN6_URB_GS_SIZE_SHIFT 0
#define CMD_VIEWPORT_STATE_POINTERS 0x780d /* GEN6+ */
# define GEN6_CC_VIEWPORT_MODIFY (1 << 12)
# define GEN6_SF_VIEWPORT_MODIFY (1 << 11)
# define GEN6_CLIP_VIEWPORT_MODIFY (1 << 10)
#define CMD_3D_SCISSOR_STATE_POINTERS 0x780f /* GEN6+ */
#define CMD_3D_VS_STATE 0x7810 /* GEN6+ */
/* DW2 */
# define GEN6_VS_SPF_MODE (1 << 31)
# define GEN6_VS_VECTOR_MASK_ENABLE (1 << 30)
# define GEN6_VS_SAMPLER_COUNT_SHIFT 27
# define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
# define GEN6_VS_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
# define GEN6_VS_FLOATING_POINT_MODE_ALT (1 << 16)
/* DW4 */
# define GEN6_VS_DISPATCH_START_GRF_SHIFT 20
# define GEN6_VS_URB_READ_LENGTH_SHIFT 11
# define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT 4
/* DW5 */
# define GEN6_VS_MAX_THREADS_SHIFT 25
# define GEN6_VS_STATISTICS_ENABLE (1 << 10)
# define GEN6_VS_CACHE_DISABLE (1 << 1)
# define GEN6_VS_ENABLE (1 << 0)
#define CMD_3D_GS_STATE 0x7811 /* GEN6+ */
/* DW2 */
# define GEN6_GS_SPF_MODE (1 << 31)
# define GEN6_GS_VECTOR_MASK_ENABLE (1 << 30)
# define GEN6_GS_SAMPLER_COUNT_SHIFT 27
# define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
/* DW4 */
# define GEN6_GS_URB_READ_LENGTH_SHIFT 11
# define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT 4
# define GEN6_GS_DISPATCH_START_GRF_SHIFT 0
/* DW5 */
# define GEN6_GS_MAX_THREADS_SHIFT 25
# define GEN6_GS_STATISTICS_ENABLE (1 << 10)
# define GEN6_GS_SO_STATISTICS_ENABLE (1 << 9)
# define GEN6_GS_RENDERING_ENABLE (1 << 8)
/* DW6 */
# define GEN6_GS_ENABLE (1 << 15)
#define CMD_3D_CLIP_STATE 0x7812 /* GEN6+ */
/* DW1 */
# define GEN6_CLIP_STATISTICS_ENABLE (1 << 10)
/**
* Just does cheap culling based on the clip distance. Bits must be
* disjoint with USER_CLIP_CLIP_DISTANCE bits.
*/
# define GEN6_USER_CLIP_CULL_DISTANCES_SHIFT 0
/* DW2 */
# define GEN6_CLIP_ENABLE (1 << 31)
# define GEN6_CLIP_API_OGL (0 << 30)
# define GEN6_CLIP_API_D3D (1 << 30)
# define GEN6_CLIP_XY_TEST (1 << 28)
# define GEN6_CLIP_Z_TEST (1 << 27)
# define GEN6_CLIP_GB_TEST (1 << 26)
/** 8-bit field of which user clip distances to clip aganist. */
# define GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT 16
# define GEN6_CLIP_MODE_NORMAL (0 << 13)
# define GEN6_CLIP_MODE_REJECT_ALL (3 << 13)
# define GEN6_CLIP_MODE_ACCEPT_ALL (4 << 13)
# define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE (1 << 9)
# define GEN6_CLIP_BARYCENTRIC_ENABLE (1 << 8)
# define GEN6_CLIP_TRI_PROVOKE_SHIFT 4
# define GEN6_CLIP_LINE_PROVOKE_SHIFT 2
# define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT 0
/* DW3 */
# define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT 17
# define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT 6
# define GEN6_CLIP_FORCE_ZERO_RTAINDEX (1 << 5)
#define CMD_3D_SF_STATE 0x7813 /* GEN6+ */
/* DW1 */
# define GEN6_SF_NUM_OUTPUTS_SHIFT 22
# define GEN6_SF_SWIZZLE_ENABLE (1 << 21)
# define GEN6_SF_POINT_SPRITE_LOWERLEFT (1 << 20)
# define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11
# define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4
/* DW2 */
# define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS (1 << 11)
# define GEN6_SF_STATISTICS_ENABLE (1 << 10)
# define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID (1 << 9)
# define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME (1 << 8)
# define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT (1 << 7)
# define GEN6_SF_FRONT_SOLID (0 << 5)
# define GEN6_SF_FRONT_WIREFRAME (1 << 5)
# define GEN6_SF_FRONT_POINT (2 << 5)
# define GEN6_SF_BACK_SOLID (0 << 3)
# define GEN6_SF_BACK_WIREFRAME (1 << 3)
# define GEN6_SF_BACK_POINT (2 << 3)
# define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE (1 << 1)
# define GEN6_SF_WINDING_CCW (1 << 0)
/* DW3 */
# define GEN6_SF_LINE_AA_ENABLE (1 << 31)
# define GEN6_SF_CULL_BOTH (0 << 29)
# define GEN6_SF_CULL_NONE (1 << 29)
# define GEN6_SF_CULL_FRONT (2 << 29)
# define GEN6_SF_CULL_BACK (3 << 29)
# define GEN6_SF_LINE_WIDTH_SHIFT 18 /* U3.7 */
# define GEN6_SF_LINE_END_CAP_WIDTH_0_5 (0 << 16)
# define GEN6_SF_LINE_END_CAP_WIDTH_1_0 (1 << 16)
# define GEN6_SF_LINE_END_CAP_WIDTH_2_0 (2 << 16)
# define GEN6_SF_LINE_END_CAP_WIDTH_4_0 (3 << 16)
# define GEN6_SF_SCISSOR_ENABLE (1 << 11)
# define GEN6_SF_MSRAST_OFF_PIXEL (0 << 8)
# define GEN6_SF_MSRAST_OFF_PATTERN (1 << 8)
# define GEN6_SF_MSRAST_ON_PIXEL (2 << 8)
# define GEN6_SF_MSRAST_ON_PATTERN (3 << 8)
/* DW4 */
# define GEN6_SF_TRI_PROVOKE_SHIFT 29
# define GEN6_SF_LINE_PROVOKE_SHIFT 27
# define GEN6_SF_TRIFAN_PROVOKE_SHIFT 25
# define GEN6_SF_LINE_AA_MODE_MANHATTAN (0 << 14)
# define GEN6_SF_LINE_AA_MODE_TRUE (1 << 14)
# define GEN6_SF_VERTEX_SUBPIXEL_8BITS (0 << 12)
# define GEN6_SF_VERTEX_SUBPIXEL_4BITS (1 << 12)
# define GEN6_SF_USE_STATE_POINT_WIDTH (1 << 11)
# define GEN6_SF_POINT_WIDTH_SHIFT 0 /* U8.3 */
/* DW5: depth offset constant */
/* DW6: depth offset scale */
/* DW7: depth offset clamp */
/* DW8 */
# define ATTRIBUTE_1_OVERRIDE_W (1 << 31)
# define ATTRIBUTE_1_OVERRIDE_Z (1 << 30)
# define ATTRIBUTE_1_OVERRIDE_Y (1 << 29)
# define ATTRIBUTE_1_OVERRIDE_X (1 << 28)
# define ATTRIBUTE_1_CONST_SOURCE_SHIFT 25
# define ATTRIBUTE_1_SWIZZLE_SHIFT 22
# define ATTRIBUTE_1_SOURCE_SHIFT 16
# define ATTRIBUTE_0_OVERRIDE_W (1 << 15)
# define ATTRIBUTE_0_OVERRIDE_Z (1 << 14)
# define ATTRIBUTE_0_OVERRIDE_Y (1 << 13)
# define ATTRIBUTE_0_OVERRIDE_X (1 << 12)
# define ATTRIBUTE_0_CONST_SOURCE_SHIFT 9
# define ATTRIBUTE_0_SWIZZLE_SHIFT 6
# define ATTRIBUTE_0_SOURCE_SHIFT 0
# define ATTRIBUTE_SWIZZLE_INPUTATTR 0
# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING 1
# define ATTRIBUTE_SWIZZLE_INPUTATTR_W 2
# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W 3
# define ATTRIBUTE_SWIZZLE_SHIFT 6
/* DW16: Point sprite texture coordinate enables */
/* DW17: Constant interpolation enables */
/* DW18: attr 0-7 wrap shortest enables */
/* DW19: attr 8-16 wrap shortest enables */
#define CMD_3D_WM_STATE 0x7814 /* GEN6+ */
/* DW1: kernel pointer */
/* DW2 */
# define GEN6_WM_SPF_MODE (1 << 31)
# define GEN6_WM_VECTOR_MASK_ENABLE (1 << 30)
# define GEN6_WM_SAMPLER_COUNT_SHIFT 27
# define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
# define GEN6_WM_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
# define GEN6_WM_FLOATING_POINT_MODE_ALT (1 << 16)
/* DW3: scratch space */
/* DW4 */
# define GEN6_WM_STATISTICS_ENABLE (1 << 31)
# define GEN6_WM_DEPTH_CLEAR (1 << 30)
# define GEN6_WM_DEPTH_RESOLVE (1 << 28)
# define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27)
# define GEN6_WM_DISPATCH_START_GRF_SHIFT_0 16
# define GEN6_WM_DISPATCH_START_GRF_SHIFT_1 8
# define GEN6_WM_DISPATCH_START_GRF_SHIFT_2 0
/* DW5 */
# define GEN6_WM_MAX_THREADS_SHIFT 25
# define GEN6_WM_KILL_ENABLE (1 << 22)
# define GEN6_WM_COMPUTED_DEPTH (1 << 21)
# define GEN6_WM_USES_SOURCE_DEPTH (1 << 20)
# define GEN6_WM_DISPATCH_ENABLE (1 << 19)
# define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 16)
# define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 16)
# define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 16)
# define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 16)
# define GEN6_WM_LINE_AA_WIDTH_0_5 (0 << 14)
# define GEN6_WM_LINE_AA_WIDTH_1_0 (1 << 14)
# define GEN6_WM_LINE_AA_WIDTH_2_0 (2 << 14)
# define GEN6_WM_LINE_AA_WIDTH_4_0 (3 << 14)
# define GEN6_WM_POLYGON_STIPPLE_ENABLE (1 << 13)
# define GEN6_WM_LINE_STIPPLE_ENABLE (1 << 11)
# define GEN6_WM_OMASK_TO_RENDER_TARGET (1 << 9)
# define GEN6_WM_USES_SOURCE_W (1 << 8)
# define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE (1 << 7)
# define GEN6_WM_32_DISPATCH_ENABLE (1 << 2)
# define GEN6_WM_16_DISPATCH_ENABLE (1 << 1)
# define GEN6_WM_8_DISPATCH_ENABLE (1 << 0)
/* DW6 */
# define GEN6_WM_NUM_SF_OUTPUTS_SHIFT 20
# define GEN6_WM_POSOFFSET_NONE (0 << 18)
# define GEN6_WM_POSOFFSET_CENTROID (2 << 18)
# define GEN6_WM_POSOFFSET_SAMPLE (3 << 18)
# define GEN6_WM_POSITION_ZW_PIXEL (0 << 16)
# define GEN6_WM_POSITION_ZW_CENTROID (2 << 16)
# define GEN6_WM_POSITION_ZW_SAMPLE (3 << 16)
# define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15)
# define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14)
# define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13)
# define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12)
# define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11)
# define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10)
# define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 9)
# define GEN6_WM_MSRAST_OFF_PIXEL (0 << 1)
# define GEN6_WM_MSRAST_OFF_PATTERN (1 << 1)
# define GEN6_WM_MSRAST_ON_PIXEL (2 << 1)
# define GEN6_WM_MSRAST_ON_PATTERN (3 << 1)
# define GEN6_WM_MSDISPMODE_PERPIXEL (1 << 0)
/* DW7: kernel 1 pointer */
/* DW8: kernel 2 pointer */
#define CMD_3D_CONSTANT_VS_STATE 0x7815 /* GEN6+ */
#define CMD_3D_CONSTANT_GS_STATE 0x7816 /* GEN6+ */
#define CMD_3D_CONSTANT_PS_STATE 0x7817 /* GEN6+ */
# define GEN6_CONSTANT_BUFFER_3_ENABLE (1 << 15)
# define GEN6_CONSTANT_BUFFER_2_ENABLE (1 << 14)
# define GEN6_CONSTANT_BUFFER_1_ENABLE (1 << 13)
# define GEN6_CONSTANT_BUFFER_0_ENABLE (1 << 12)
#define CMD_3D_SAMPLE_MASK 0x7818 /* GEN6+ */
#define CMD_DRAW_RECT 0x7900
#define CMD_BLEND_CONSTANT_COLOR 0x7901
@ -827,6 +1127,25 @@
#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909
#define CMD_AA_LINE_PARAMETERS 0x790a
#define CMD_GS_SVB_INDEX 0x790b /* CTG+ */
/* DW1 */
# define SVB_INDEX_SHIFT 29
# define SVB_LOAD_INTERNAL_VERTEX_COUNT (1 << 0) /* SNB+ */
/* DW2: SVB index */
/* DW3: SVB maximum index */
#define CMD_3D_MULTISAMPLE 0x790d /* SNB+ */
/* DW1 */
# define MS_PIXEL_LOCATION_CENTER (0 << 4)
# define MS_PIXEL_LOCATION_UPPER_LEFT (1 << 4)
# define MS_NUMSAMPLES_1 (0 << 1)
# define MS_NUMSAMPLES_4 (2 << 1)
# define MS_NUMSAMPLES_8 (3 << 1)
#define CMD_3D_CLEAR_PARAMS 0x7910 /* ILK+ */
# define DEPTH_CLEAR_VALID (1 << 15)
/* DW1: depth clear value */
#define CMD_PIPE_CONTROL 0x7a00
#define CMD_3D_PRIM 0x7b00
@ -839,8 +1158,8 @@
#define R02_PRIM_END 0x1
#define R02_PRIM_START 0x2
#define URB_SIZES(brw) (BRW_IS_IGDNG(brw) ? 1024 : \
(BRW_IS_G4X(brw) ? 384 : 256)) /* 512 bit units */
#define URB_SIZES(brw) (brw->gen == 5 ? 1024 : \
(brw->is_g4x ? 384 : 256)) /* 512 bit units */

179
src/gallium/drivers/i965/brw_disasm.c
View file

@ -49,12 +49,14 @@ struct {
[BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
@ -69,13 +71,14 @@ struct {
[BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
[BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 1, .ndst = 01 },
[BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
@ -144,7 +147,6 @@ char *chan_sel[4] = {
};
char *dest_condmod[16] = {
[0] = NULL
};
char *debug_ctrl[2] = {
@ -157,6 +159,16 @@ char *saturate[2] = {
[1] = ".sat"
};
char *accwr[2] = {
[0] = "",
[1] = "AccWrEnable"
};
char *wectrl[2] = {
[0] = "WE_normal",
[1] = "WE_all"
};
char *exec_size[8] = {
[0] = "1",
[1] = "2",
@ -204,6 +216,7 @@ char *compr_ctrl[4] = {
[0] = "",
[1] = "sechalf",
[2] = "compr",
[3] = "compr4",
};
char *dep_ctrl[4] = {
@ -233,6 +246,16 @@ char *reg_encoding[8] = {
[7] = "F"
};
int reg_type_size[8] = {
[0] = 4,
[1] = 4,
[2] = 2,
[3] = 2,
[4] = 1,
[5] = 1,
[7] = 4
};
char *imm_encoding[8] = {
[0] = "UD",
[1] = "D",
@ -321,6 +344,11 @@ char *math_precision[2] = {
[1] = "partial_precision"
};
char *urb_opcode[2] = {
[0] = "urb_write",
[1] = "ff_sync",
};
char *urb_swizzle[4] = {
[BRW_URB_SWIZZLE_NONE] = "",
[BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
@ -416,6 +444,11 @@ static int print_opcode (FILE *file, int id)
static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
{
int err = 0;
/* Clear the Compr4 instruction compression bit. */
if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
_reg_nr &= ~(1 << 7);
if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
switch (_reg_nr & 0xf0) {
case BRW_ARF_NULL:
@ -427,6 +460,9 @@ static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
case BRW_ARF_ACCUMULATOR:
format (file, "acc%d", _reg_nr & 0x0f);
break;
case BRW_ARF_FLAG:
format (file, "f%d", _reg_nr & 0x0f);
break;
case BRW_ARF_MASK:
format (file, "mask%d", _reg_nr & 0x0f);
break;
@ -457,7 +493,7 @@ static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
return err;
}
static int dest (FILE *file, const struct brw_instruction *inst)
static int dest (FILE *file, struct brw_instruction *inst)
{
int err = 0;
@ -469,7 +505,8 @@ static int dest (FILE *file, const struct brw_instruction *inst)
if (err == -1)
return 0;
if (inst->bits1.da1.dest_subreg_nr)
format (file, ".%d", inst->bits1.da1.dest_subreg_nr);
format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
reg_type_size[inst->bits1.da1.dest_reg_type]);
format (file, "<%d>", inst->bits1.da1.dest_horiz_stride);
err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
}
@ -477,7 +514,8 @@ static int dest (FILE *file, const struct brw_instruction *inst)
{
string (file, "g[a0");
if (inst->bits1.ia1.dest_subreg_nr)
format (file, ".%d", inst->bits1.ia1.dest_subreg_nr);
format (file, ".%d", inst->bits1.ia1.dest_subreg_nr /
reg_type_size[inst->bits1.ia1.dest_reg_type]);
if (inst->bits1.ia1.dest_indirect_offset)
format (file, " %d", inst->bits1.ia1.dest_indirect_offset);
string (file, "]");
@ -493,7 +531,8 @@ static int dest (FILE *file, const struct brw_instruction *inst)
if (err == -1)
return 0;
if (inst->bits1.da16.dest_subreg_nr)
format (file, ".%d", inst->bits1.da16.dest_subreg_nr);
format (file, ".%d", inst->bits1.da16.dest_subreg_nr /
reg_type_size[inst->bits1.da16.dest_reg_type]);
string (file, "<1>");
err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
@ -534,7 +573,7 @@ static int src_da1 (FILE *file, GLuint type, GLuint _reg_file,
if (err == -1)
return 0;
if (sub_reg_num)
format (file, ".%d", sub_reg_num);
format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
src_align1_region (file, _vert_stride, _width, _horiz_stride);
err |= control (file, "src reg encoding", reg_encoding, type, NULL);
return err;
@ -588,11 +627,12 @@ static int src_da16 (FILE *file,
if (err == -1)
return 0;
if (_subreg_nr)
format (file, ".%d", _subreg_nr);
/* bit4 for subreg number byte addressing. Make this same meaning as
in da1 case, so output looks consistent. */
format (file, ".%d", 16 / reg_type_size[_reg_type]);
string (file, "<");
err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
string (file, ",1,1>");
err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
string (file, ",4,1>");
/*
* Three kinds of swizzle display:
* identity - nothing printed
@ -619,11 +659,12 @@ static int src_da16 (FILE *file,
err |= control (file, "channel select", chan_sel, swz_z, NULL);
err |= control (file, "channel select", chan_sel, swz_w, NULL);
}
err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
return err;
}
static int imm (FILE *file, GLuint type, const struct brw_instruction *inst) {
static int imm (FILE *file, GLuint type, struct brw_instruction *inst) {
switch (type) {
case BRW_REGISTER_TYPE_UD:
format (file, "0x%08xUD", inst->bits3.ud);
@ -652,7 +693,7 @@ static int imm (FILE *file, GLuint type, const struct brw_instruction *inst) {
return 0;
}
static int src0 (FILE *file, const struct brw_instruction *inst)
static int src0 (FILE *file, struct brw_instruction *inst)
{
if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
return imm (file, inst->bits1.da1.src0_reg_type,
@ -712,7 +753,7 @@ static int src0 (FILE *file, const struct brw_instruction *inst)
}
}
static int src1 (FILE *file, const struct brw_instruction *inst)
static int src1 (FILE *file, struct brw_instruction *inst)
{
if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
return imm (file, inst->bits1.da1.src1_reg_type,
@ -772,7 +813,7 @@ static int src1 (FILE *file, const struct brw_instruction *inst)
}
}
int brw_disasm_insn (FILE *file, const struct brw_instruction *inst)
int brw_disasm_insn (FILE *file, struct brw_instruction *inst, int gen)
{
int err = 0;
int space = 0;
@ -822,7 +863,8 @@ int brw_disasm_insn (FILE *file, const struct brw_instruction *inst)
err |= src1 (file, inst);
}
if (inst->header.opcode == BRW_OPCODE_SEND) {
if (inst->header.opcode == BRW_OPCODE_SEND ||
inst->header.opcode == BRW_OPCODE_SENDC) {
newline (file);
pad (file, 16);
space = 0;
@ -842,24 +884,70 @@ int brw_disasm_insn (FILE *file, const struct brw_instruction *inst)
inst->bits3.math.precision, &space);
break;
case BRW_MESSAGE_TARGET_SAMPLER:
format (file, " (%d, %d, ",
inst->bits3.sampler.binding_table_index,
inst->bits3.sampler.sampler);
err |= control (file, "sampler target format", sampler_target_format,
inst->bits3.sampler.return_format, NULL);
string (file, ")");
if (gen >= 5) {
format (file, " (%d, %d, %d, %d)",
inst->bits3.sampler_gen5.binding_table_index,
inst->bits3.sampler_gen5.sampler,
inst->bits3.sampler_gen5.msg_type,
inst->bits3.sampler_gen5.simd_mode);
} else if (0 /* FINISHME: is_g4x */) {
format (file, " (%d, %d)",
inst->bits3.sampler_g4x.binding_table_index,
inst->bits3.sampler_g4x.sampler);
} else {
format (file, " (%d, %d, ",
inst->bits3.sampler.binding_table_index,
inst->bits3.sampler.sampler);
err |= control (file, "sampler target format", sampler_target_format,
inst->bits3.sampler.return_format, NULL);
string (file, ")");
}
break;
case BRW_MESSAGE_TARGET_DATAPORT_READ:
if (gen >= 6) {
format (file, " (%d, %d, %d, %d, %d, %d)",
inst->bits3.dp_render_cache.binding_table_index,
inst->bits3.dp_render_cache.msg_control,
inst->bits3.dp_render_cache.msg_type,
inst->bits3.dp_render_cache.send_commit_msg,
inst->bits3.dp_render_cache.msg_length,
inst->bits3.dp_render_cache.response_length);
} else if (gen >= 5 /* FINISHME: || is_g4x */) {
format (file, " (%d, %d, %d)",
inst->bits3.dp_read_gen5.binding_table_index,
inst->bits3.dp_read_gen5.msg_control,
inst->bits3.dp_read_gen5.msg_type);
} else {
format (file, " (%d, %d, %d)",
inst->bits3.dp_read.binding_table_index,
inst->bits3.dp_read.msg_control,
inst->bits3.dp_read.msg_type);
}
break;
case BRW_MESSAGE_TARGET_DATAPORT_WRITE:
format (file, " (%d, %d, %d, %d)",
inst->bits3.dp_write.binding_table_index,
(inst->bits3.dp_write.pixel_scoreboard_clear << 3) |
inst->bits3.dp_write.msg_control,
inst->bits3.dp_write.msg_type,
inst->bits3.dp_write.send_commit_msg);
if (gen >= 6) {
format (file, " (%d, %d, %d, %d, %d, %d)",
inst->bits3.dp_render_cache.binding_table_index,
inst->bits3.dp_render_cache.msg_control,
inst->bits3.dp_render_cache.msg_type,
inst->bits3.dp_render_cache.send_commit_msg,
inst->bits3.dp_render_cache.msg_length,
inst->bits3.dp_render_cache.response_length);
} else {
format (file, " (%d, %d, %d, %d)",
inst->bits3.dp_write.binding_table_index,
(inst->bits3.dp_write.pixel_scoreboard_clear << 3) |
inst->bits3.dp_write.msg_control,
inst->bits3.dp_write.msg_type,
inst->bits3.dp_write.send_commit_msg);
}
break;
case BRW_MESSAGE_TARGET_URB:
format (file, " %d", inst->bits3.urb.offset);
space = 1;
if (gen >= 5) {
format (file, " %d", inst->bits3.urb_gen5.offset);
} else {
format (file, " %d", inst->bits3.urb.offset);
}
err |= control (file, "urb swizzle", urb_swizzle,
inst->bits3.urb.swizzle_control, &space);
err |= control (file, "urb allocate", urb_allocate,
@ -868,6 +956,11 @@ int brw_disasm_insn (FILE *file, const struct brw_instruction *inst)
inst->bits3.urb.used, &space);
err |= control (file, "urb complete", urb_complete,
inst->bits3.urb.complete, &space);
if (gen >= 5) {
format (file, " mlen %d, rlen %d\n",
inst->bits3.urb_gen5.msg_length,
inst->bits3.urb_gen5.response_length);
}
break;
case BRW_MESSAGE_TARGET_THREAD_SPAWNER:
break;
@ -877,10 +970,17 @@ int brw_disasm_insn (FILE *file, const struct brw_instruction *inst)
}
if (space)
string (file, " ");
format (file, "mlen %d",
inst->bits3.generic.msg_length);
format (file, " rlen %d",
inst->bits3.generic.response_length);
if (gen >= 5) {
format (file, "mlen %d",
inst->bits3.generic_gen5.msg_length);
format (file, " rlen %d",
inst->bits3.generic_gen5.response_length);
} else {
format (file, "mlen %d",
inst->bits3.generic.msg_length);
format (file, " rlen %d",
inst->bits3.generic.response_length);
}
}
pad (file, 64);
if (inst->header.opcode != BRW_OPCODE_NOP) {
@ -891,7 +991,8 @@ int brw_disasm_insn (FILE *file, const struct brw_instruction *inst)
err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
err |= control (file, "compression control", compr_ctrl, inst->header.compression_control, &space);
err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
if (inst->header.opcode == BRW_OPCODE_SEND)
if (inst->header.opcode == BRW_OPCODE_SEND ||
inst->header.opcode == BRW_OPCODE_SENDC)
err |= control (file, "end of thread", end_of_thread,
inst->bits3.generic.end_of_thread, &space);
if (space)
@ -905,13 +1006,13 @@ int brw_disasm_insn (FILE *file, const struct brw_instruction *inst)
int brw_disasm (FILE *file,
const struct brw_instruction *inst,
unsigned count)
struct brw_instruction *inst,
unsigned count, int gen)
{
int i, err;
for (i = 0; i < count; i++) {
err = brw_disasm_insn(stderr, &inst[i]);
err = brw_disasm_insn(stderr, &inst[i], gen);
if (err)
return err;
}

6
src/gallium/drivers/i965/brw_disasm.h
View file

@ -27,10 +27,10 @@
struct brw_instruction;
int brw_disasm_insn (FILE *file, const struct brw_instruction *inst);
int brw_disasm_insn (FILE *file, struct brw_instruction *inst, int gen);
int brw_disasm (FILE *file,
const struct brw_instruction *inst,
unsigned count);
struct brw_instruction *inst,
unsigned count, int gen);
#endif

2
src/gallium/drivers/i965/brw_draw_upload.c
View file

@ -170,7 +170,7 @@ static int brw_emit_vertex_buffers( struct brw_context *brw )
OUT_RELOC(brw->vb.vb[i].bo,
BRW_USAGE_VERTEX,
brw->vb.vb[i].offset);
if (BRW_IS_IGDNG(brw)) {
if (brw->gen == 5) {
OUT_RELOC(brw->vb.vb[i].bo,
BRW_USAGE_VERTEX,
brw->vb.vb[i].bo->size - 1);

158
src/gallium/drivers/i965/brw_eu_emit.c
View file

@ -255,19 +255,19 @@ static void brw_set_math_message( struct brw_context *brw,
{
brw_set_src1(insn, brw_imm_d(0));
if (BRW_IS_IGDNG(brw)) {
insn->bits3.math_igdng.function = function;
insn->bits3.math_igdng.int_type = integer_type;
insn->bits3.math_igdng.precision = low_precision;
insn->bits3.math_igdng.saturate = saturate;
insn->bits3.math_igdng.data_type = dataType;
insn->bits3.math_igdng.snapshot = 0;
insn->bits3.math_igdng.header_present = 0;
insn->bits3.math_igdng.response_length = response_length;
insn->bits3.math_igdng.msg_length = msg_length;
insn->bits3.math_igdng.end_of_thread = 0;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_MATH;
insn->bits2.send_igdng.end_of_thread = 0;
if (brw->gen == 5) {
insn->bits3.math_gen5.function = function;
insn->bits3.math_gen5.int_type = integer_type;
insn->bits3.math_gen5.precision = low_precision;
insn->bits3.math_gen5.saturate = saturate;
insn->bits3.math_gen5.data_type = dataType;
insn->bits3.math_gen5.snapshot = 0;
insn->bits3.math_gen5.header_present = 0;
insn->bits3.math_gen5.response_length = response_length;
insn->bits3.math_gen5.msg_length = msg_length;
insn->bits3.math_gen5.end_of_thread = 0;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_MATH;
insn->bits2.send_gen5.end_of_thread = 0;
} else {
insn->bits3.math.function = function;
insn->bits3.math.int_type = integer_type;
@ -295,18 +295,18 @@ static void brw_set_ff_sync_message( struct brw_context *brw,
{
brw_set_src1(insn, brw_imm_d(0));
insn->bits3.urb_igdng.opcode = 1;
insn->bits3.urb_igdng.offset = offset;
insn->bits3.urb_igdng.swizzle_control = swizzle_control;
insn->bits3.urb_igdng.allocate = allocate;
insn->bits3.urb_igdng.used = used;
insn->bits3.urb_igdng.complete = complete;
insn->bits3.urb_igdng.header_present = 1;
insn->bits3.urb_igdng.response_length = response_length;
insn->bits3.urb_igdng.msg_length = msg_length;
insn->bits3.urb_igdng.end_of_thread = end_of_thread;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
insn->bits3.urb_gen5.opcode = 1;
insn->bits3.urb_gen5.offset = offset;
insn->bits3.urb_gen5.swizzle_control = swizzle_control;
insn->bits3.urb_gen5.allocate = allocate;
insn->bits3.urb_gen5.used = used;
insn->bits3.urb_gen5.complete = complete;
insn->bits3.urb_gen5.header_present = 1;
insn->bits3.urb_gen5.response_length = response_length;
insn->bits3.urb_gen5.msg_length = msg_length;
insn->bits3.urb_gen5.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
}
static void brw_set_urb_message( struct brw_context *brw,
@ -322,19 +322,19 @@ static void brw_set_urb_message( struct brw_context *brw,
{
brw_set_src1(insn, brw_imm_d(0));
if (BRW_IS_IGDNG(brw)) {
insn->bits3.urb_igdng.opcode = 0; /* ? */
insn->bits3.urb_igdng.offset = offset;
insn->bits3.urb_igdng.swizzle_control = swizzle_control;
insn->bits3.urb_igdng.allocate = allocate;
insn->bits3.urb_igdng.used = used; /* ? */
insn->bits3.urb_igdng.complete = complete;
insn->bits3.urb_igdng.header_present = 1;
insn->bits3.urb_igdng.response_length = response_length;
insn->bits3.urb_igdng.msg_length = msg_length;
insn->bits3.urb_igdng.end_of_thread = end_of_thread;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
if (brw->gen == 5) {
insn->bits3.urb_gen5.opcode = 0; /* ? */
insn->bits3.urb_gen5.offset = offset;
insn->bits3.urb_gen5.swizzle_control = swizzle_control;
insn->bits3.urb_gen5.allocate = allocate;
insn->bits3.urb_gen5.used = used; /* ? */
insn->bits3.urb_gen5.complete = complete;
insn->bits3.urb_gen5.header_present = 1;
insn->bits3.urb_gen5.response_length = response_length;
insn->bits3.urb_gen5.msg_length = msg_length;
insn->bits3.urb_gen5.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
} else {
insn->bits3.urb.opcode = 0; /* ? */
insn->bits3.urb.offset = offset;
@ -361,18 +361,18 @@ static void brw_set_dp_write_message( struct brw_context *brw,
{
brw_set_src1(insn, brw_imm_d(0));
if (BRW_IS_IGDNG(brw)) {
insn->bits3.dp_write_igdng.binding_table_index = binding_table_index;
insn->bits3.dp_write_igdng.msg_control = msg_control;
insn->bits3.dp_write_igdng.pixel_scoreboard_clear = pixel_scoreboard_clear;
insn->bits3.dp_write_igdng.msg_type = msg_type;
insn->bits3.dp_write_igdng.send_commit_msg = 0;
insn->bits3.dp_write_igdng.header_present = 1;
insn->bits3.dp_write_igdng.response_length = response_length;
insn->bits3.dp_write_igdng.msg_length = msg_length;
insn->bits3.dp_write_igdng.end_of_thread = end_of_thread;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
if (brw->gen == 5) {
insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_write_gen5.msg_control = msg_control;
insn->bits3.dp_write_gen5.pixel_scoreboard_clear = pixel_scoreboard_clear;
insn->bits3.dp_write_gen5.msg_type = msg_type;
insn->bits3.dp_write_gen5.send_commit_msg = 0;
insn->bits3.dp_write_gen5.header_present = 1;
insn->bits3.dp_write_gen5.response_length = response_length;
insn->bits3.dp_write_gen5.msg_length = msg_length;
insn->bits3.dp_write_gen5.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
} else {
insn->bits3.dp_write.binding_table_index = binding_table_index;
insn->bits3.dp_write.msg_control = msg_control;
@ -398,18 +398,18 @@ static void brw_set_dp_read_message( struct brw_context *brw,
{
brw_set_src1(insn, brw_imm_d(0));
if (BRW_IS_IGDNG(brw)) {
insn->bits3.dp_read_igdng.binding_table_index = binding_table_index;
insn->bits3.dp_read_igdng.msg_control = msg_control;
insn->bits3.dp_read_igdng.msg_type = msg_type;
insn->bits3.dp_read_igdng.target_cache = target_cache;
insn->bits3.dp_read_igdng.header_present = 1;
insn->bits3.dp_read_igdng.response_length = response_length;
insn->bits3.dp_read_igdng.msg_length = msg_length;
insn->bits3.dp_read_igdng.pad1 = 0;
insn->bits3.dp_read_igdng.end_of_thread = end_of_thread;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
if (brw->gen == 5) {
insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_read_gen5.msg_control = msg_control;
insn->bits3.dp_read_gen5.msg_type = msg_type;
insn->bits3.dp_read_gen5.target_cache = target_cache;
insn->bits3.dp_read_gen5.header_present = 1;
insn->bits3.dp_read_gen5.response_length = response_length;
insn->bits3.dp_read_gen5.msg_length = msg_length;
insn->bits3.dp_read_gen5.pad1 = 0;
insn->bits3.dp_read_gen5.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
} else {
insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/
insn->bits3.dp_read.msg_control = msg_control; /*8:11*/
@ -437,18 +437,18 @@ static void brw_set_sampler_message(struct brw_context *brw,
assert(eot == 0);
brw_set_src1(insn, brw_imm_d(0));
if (BRW_IS_IGDNG(brw)) {
insn->bits3.sampler_igdng.binding_table_index = binding_table_index;
insn->bits3.sampler_igdng.sampler = sampler;
insn->bits3.sampler_igdng.msg_type = msg_type;
insn->bits3.sampler_igdng.simd_mode = simd_mode;
insn->bits3.sampler_igdng.header_present = header_present;
insn->bits3.sampler_igdng.response_length = response_length;
insn->bits3.sampler_igdng.msg_length = msg_length;
insn->bits3.sampler_igdng.end_of_thread = eot;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_SAMPLER;
insn->bits2.send_igdng.end_of_thread = eot;
} else if (BRW_IS_G4X(brw)) {
if (brw->gen == 5) {
insn->bits3.sampler_gen5.binding_table_index = binding_table_index;
insn->bits3.sampler_gen5.sampler = sampler;
insn->bits3.sampler_gen5.msg_type = msg_type;
insn->bits3.sampler_gen5.simd_mode = simd_mode;
insn->bits3.sampler_gen5.header_present = header_present;
insn->bits3.sampler_gen5.response_length = response_length;
insn->bits3.sampler_gen5.msg_length = msg_length;
insn->bits3.sampler_gen5.end_of_thread = eot;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER;
insn->bits2.send_gen5.end_of_thread = eot;
} else if (brw->is_g4x) {
insn->bits3.sampler_g4x.binding_table_index = binding_table_index;
insn->bits3.sampler_g4x.sampler = sampler;
insn->bits3.sampler_g4x.msg_type = msg_type;
@ -478,7 +478,7 @@ static struct brw_instruction *next_insn( struct brw_compile *p,
if (0 && (BRW_DEBUG & DEBUG_DISASSEM))
{
if (p->nr_insn)
brw_disasm_insn(stderr, &p->store[p->nr_insn-1]);
brw_disasm_insn(stderr, &p->store[p->nr_insn-1], p->brw->gen);
}
assert(p->nr_insn + 1 < BRW_EU_MAX_INSN);
@ -658,7 +658,7 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
struct brw_instruction *insn;
GLuint br = 1;
if (BRW_IS_IGDNG(p->brw))
if (p->brw->gen == 5)
br = 2;
if (p->single_program_flow) {
@ -699,7 +699,7 @@ void brw_ENDIF(struct brw_compile *p,
{
GLuint br = 1;
if (BRW_IS_IGDNG(p->brw))
if (p->brw->gen == 5)
br = 2;
if (p->single_program_flow) {
@ -813,7 +813,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *insn;
GLuint br = 1;
if (BRW_IS_IGDNG(p->brw))
if (p->brw->gen == 5)
br = 2;
if (p->single_program_flow)
@ -856,7 +856,7 @@ void brw_land_fwd_jump(struct brw_compile *p,
struct brw_instruction *landing = &p->store[p->nr_insn];
GLuint jmpi = 1;
if (BRW_IS_IGDNG(p->brw))
if (p->brw->gen == 5)
jmpi = 2;
assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI);

4
src/gallium/drivers/i965/brw_gs.c
View file

@ -51,13 +51,13 @@ static enum pipe_error compile_gs_prog( struct brw_context *brw,
memset(&c, 0, sizeof(c));
c.key = *key;
c.need_ff_sync = BRW_IS_IGDNG(brw);
c.need_ff_sync = brw->gen == 5;
/* Need to locate the two positions present in vertex + header.
* These are currently hardcoded:
*/
c.nr_attrs = c.key.nr_attrs;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
else
c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */

2
src/gallium/drivers/i965/brw_gs_state.c
View file

@ -103,7 +103,7 @@ gs_unit_create_from_key(struct brw_context *brw,
else
gs.thread4.max_threads = 0;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
gs.thread4.rendering_enable = 1;
if (BRW_DEBUG & DEBUG_STATS)

14
src/gallium/drivers/i965/brw_misc_state.c
View file

@ -239,7 +239,7 @@ static int prepare_depthbuffer(struct brw_context *brw)
static int emit_depthbuffer(struct brw_context *brw)
{
struct pipe_surface *surface = brw->curr.fb.zsbuf;
unsigned int len = (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? 6 : 5;
unsigned int len = (brw->is_g4x || brw->gen == 5) ? 6 : 5;
if (surface == NULL) {
BEGIN_BATCH(len, IGNORE_CLIPRECTS);
@ -250,7 +250,7 @@ static int emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(0);
if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
if (brw->is_g4x || brw->gen == 5)
OUT_BATCH(0);
ADVANCE_BATCH();
@ -298,7 +298,7 @@ static int emit_depthbuffer(struct brw_context *brw)
((surface->height - 1) << 19));
OUT_BATCH(0);
if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
if (brw->is_g4x || brw->gen == 5)
OUT_BATCH(0);
ADVANCE_BATCH();
@ -374,7 +374,7 @@ static int upload_invariant_state( struct brw_context *brw )
struct brw_pipeline_select ps;
memset(&ps, 0, sizeof(ps));
if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
if (brw->is_g4x || brw->gen == 5)
ps.header.opcode = CMD_PIPELINE_SELECT_GM45;
else
ps.header.opcode = CMD_PIPELINE_SELECT_965;
@ -413,7 +413,7 @@ static int upload_invariant_state( struct brw_context *brw )
struct brw_vf_statistics vfs;
memset(&vfs, 0, sizeof(vfs));
if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
if (brw->is_g4x || brw->gen == 5)
vfs.opcode = CMD_VF_STATISTICS_GM45;
else
vfs.opcode = CMD_VF_STATISTICS_965;
@ -424,7 +424,7 @@ static int upload_invariant_state( struct brw_context *brw )
BRW_BATCH_STRUCT(brw, &vfs);
}
if (!BRW_IS_965(brw))
if (!(brw->gen == 4))
{
struct brw_aa_line_parameters balp;
@ -480,7 +480,7 @@ static int upload_state_base_address( struct brw_context *brw )
/* Output the structure (brw_state_base_address) directly to the
* batchbuffer, so we can emit relocations inline.
*/
if (BRW_IS_IGDNG(brw)) {
if (brw->gen == 5) {
BEGIN_BATCH(8, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */

2
src/gallium/drivers/i965/brw_pipe_rast.c
View file

@ -35,7 +35,7 @@ calculate_clip_key_rast( const struct brw_context *brw,
{
memset(key, 0, sizeof *key);
if (brw->chipset.is_igdng)
if (brw->gen == 5)
key->clip_mode = BRW_CLIPMODE_KERNEL_CLIP;
else
key->clip_mode = BRW_CLIPMODE_NORMAL;

21
src/gallium/drivers/i965/brw_pipe_surface.c
View file

@ -169,20 +169,15 @@ static struct brw_surface *create_in_place_view( struct brw_screen *brw_screen,
surface->ss.ss1.base_addr = surface->offset - tile_offset;
if (brw_screen->chipset.is_g4x) {
if (tex->tiling == BRW_TILING_X) {
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
*/
surface->ss.ss5.x_offset = (tile_offset % 512) / tex->cpp / 4;
surface->ss.ss5.y_offset = tile_offset / 512 / 2;
} else {
surface->ss.ss5.x_offset = (tile_offset % 128) / tex->cpp / 4;
if (tex->tiling == BRW_TILING_X) {
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
*/
surface->ss.ss5.x_offset = (tile_offset % 512) / tex->cpp / 4;
surface->ss.ss5.y_offset = tile_offset / 512 / 2;
} else {
surface->ss.ss5.x_offset = (tile_offset % 128) / tex->cpp / 4;
surface->ss.ss5.y_offset = tile_offset / 128 / 2;
}
}
else {
assert(tile_offset == 0);
}
}

2
src/gallium/drivers/i965/brw_pipe_vertex.c
View file

@ -203,7 +203,7 @@ static void brw_translate_vertex_elements(struct brw_context *brw,
brw_velems->ve[i].ve1.vfcomponent2 = comp2;
brw_velems->ve[i].ve1.vfcomponent3 = comp3;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
brw_velems->ve[i].ve1.dst_offset = 0;
else
brw_velems->ve[i].ve1.dst_offset = i * 4;

50
src/gallium/drivers/i965/brw_reg.h
View file

@ -93,18 +93,54 @@
#define PCI_CHIP_G45_G 0x2E22
#define PCI_CHIP_G41_G 0x2E32
#define PCI_CHIP_B43_G 0x2E42
#define PCI_CHIP_B43_G1 0x2E92
#define PCI_CHIP_ILD_G 0x0042
#define PCI_CHIP_ILM_G 0x0046
struct brw_chipset {
unsigned pci_id:16;
unsigned is_965:1;
unsigned is_igdng:1;
unsigned is_g4x:1;
unsigned pad:13;
};
#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */
#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */
#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* Server */
#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
devid == PCI_CHIP_Q45_G || \
devid == PCI_CHIP_G45_G || \
devid == PCI_CHIP_G41_G || \
devid == PCI_CHIP_B43_G || \
devid == PCI_CHIP_B43_G1)
#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
#define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \
devid == PCI_CHIP_I965_Q || \
devid == PCI_CHIP_I965_G_1 || \
devid == PCI_CHIP_I965_GM || \
devid == PCI_CHIP_I965_GME || \
devid == PCI_CHIP_I946_GZ || \
IS_G4X(devid))
#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_IRONLAKE(devid) IS_GEN5(devid)
#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_S)
#define IS_965(devid) (IS_GEN4(devid) || \
IS_G4X(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid))
/* XXX: hacks
*/

2
src/gallium/drivers/i965/brw_resource_texture.c
View file

@ -392,7 +392,7 @@ brw_texture_create( struct pipe_screen *screen,
if (tex->compressed == 0 &&
!bscreen->no_tiling)
{
if (bscreen->chipset.is_965 &&
if (bscreen->gen < 5 &&
util_format_is_depth_or_stencil(template->format))
tex->tiling = BRW_TILING_Y;
else

2
src/gallium/drivers/i965/brw_resource_texture_layout.c
View file

@ -388,7 +388,7 @@ GLboolean brw_texture_layout(struct brw_screen *brw_screen,
{
switch (tex->b.b.target) {
case PIPE_TEXTURE_CUBE:
if (brw_screen->chipset.is_igdng)
if (brw_screen->gen == 5)
brw_layout_cubemap_idgng( tex );
else
brw_layout_3d_cube( tex );

60
src/gallium/drivers/i965/brw_screen.c
View file

@ -97,7 +97,7 @@ brw_get_name(struct pipe_screen *screen)
static char buffer[128];
const char *chipset;
switch (brw_screen(screen)->chipset.pci_id) {
switch (brw_screen(screen)->pci_id) {
case PCI_CHIP_I965_G:
chipset = "I965_G";
break;
@ -405,8 +405,6 @@ struct pipe_screen *
brw_screen_create(struct brw_winsys_screen *sws)
{
struct brw_screen *bscreen;
struct brw_chipset chipset;
#ifdef DEBUG
BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
@ -415,46 +413,30 @@ brw_screen_create(struct brw_winsys_screen *sws)
BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
#endif
memset(&chipset, 0, sizeof chipset);
chipset.pci_id = sws->pci_id;
switch (chipset.pci_id) {
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I965_G_1:
case PCI_CHIP_I946_GZ:
case PCI_CHIP_I965_GM:
case PCI_CHIP_I965_GME:
chipset.is_965 = TRUE;
break;
case PCI_CHIP_GM45_GM:
case PCI_CHIP_IGD_E_G:
case PCI_CHIP_Q45_G:
case PCI_CHIP_G45_G:
case PCI_CHIP_G41_G:
case PCI_CHIP_B43_G:
chipset.is_g4x = TRUE;
break;
case PCI_CHIP_ILD_G:
case PCI_CHIP_ILM_G:
chipset.is_igdng = TRUE;
break;
default:
debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
__FUNCTION__, chipset.pci_id);
return NULL;
}
bscreen = CALLOC_STRUCT(brw_screen);
if (!bscreen)
return NULL;
bscreen->chipset = chipset;
bscreen->pci_id = sws->pci_id;
if (IS_GEN6(sws->pci_id)) {
bscreen->gen = 6;
bscreen->needs_ff_sync = TRUE;
} else if (IS_GEN5(sws->pci_id)) {
bscreen->gen = 5;
bscreen->needs_ff_sync = TRUE;
} else if (IS_965(sws->pci_id)) {
bscreen->gen = 4;
if (IS_G4X(sws->pci_id)) {
bscreen->is_g4x = true;
}
} else {
debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
__FUNCTION__, sws->pci_id);
free(bscreen);
return NULL;
}
sws->gen = bscreen->gen;
bscreen->sws = sws;
bscreen->base.winsys = NULL;
bscreen->base.destroy = brw_destroy_screen;

6
src/gallium/drivers/i965/brw_screen.h
View file

@ -43,7 +43,11 @@ struct brw_winsys_screen;
struct brw_screen
{
struct pipe_screen base;
struct brw_chipset chipset;
int gen;
boolean has_negative_rhw_bug;
boolean needs_ff_sync;
boolean is_g4x;
int pci_id;
struct brw_winsys_screen *sws;
boolean no_tiling;
};

4
src/gallium/drivers/i965/brw_sf_emit.c
View file

@ -161,7 +161,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c )
if (c->key.primitive == SF_UNFILLED_TRIS)
return;
if (BRW_IS_IGDNG(p->brw))
if (p->brw->gen == 5)
jmpi = 2;
brw_push_insn_state(p);
@ -205,7 +205,7 @@ static void do_flatshade_line( struct brw_sf_compile *c )
if (c->key.primitive == SF_UNFILLED_TRIS)
return;
if (BRW_IS_IGDNG(p->brw))
if (p->brw->gen == 5)
jmpi = 2;
brw_push_insn_state(p);

4
src/gallium/drivers/i965/brw_sf_state.c
View file

@ -148,7 +148,7 @@ sf_unit_create_from_key(struct brw_context *brw,
sf.thread3.dispatch_grf_start_reg = 3;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
sf.thread3.urb_entry_read_offset = 3;
else
sf.thread3.urb_entry_read_offset = 1;
@ -161,7 +161,7 @@ sf_unit_create_from_key(struct brw_context *brw,
/* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or
* 48(IGDNG) threads
*/
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
chipset_max_threads = 48;
else
chipset_max_threads = 24;

238
src/gallium/drivers/i965/brw_structs.h
View file

@ -279,7 +279,7 @@ struct brw_aa_line_parameters
struct header header;
struct {
GLuint aa_coverage_scope:8;
GLuint aa_coverage_slope:8;
GLuint pad0:8;
GLuint aa_coverage_bias:8;
GLuint pad1:8;
@ -659,7 +659,105 @@ struct brw_clip_unit_state
GLfloat viewport_ymax;
};
struct gen6_blend_state
{
struct {
GLuint dest_blend_factor:5;
GLuint source_blend_factor:5;
GLuint pad3:1;
GLuint blend_func:3;
GLuint pad2:1;
GLuint ia_dest_blend_factor:5;
GLuint ia_source_blend_factor:5;
GLuint pad1:1;
GLuint ia_blend_func:3;
GLuint pad0:1;
GLuint ia_blend_enable:1;
GLuint blend_enable:1;
} blend0;
struct {
GLuint post_blend_clamp_enable:1;
GLuint pre_blend_clamp_enable:1;
GLuint clamp_range:2;
GLuint pad0:4;
GLuint x_dither_offset:2;
GLuint y_dither_offset:2;
GLuint dither_enable:1;
GLuint alpha_test_func:3;
GLuint alpha_test_enable:1;
GLuint pad1:1;
GLuint logic_op_func:4;
GLuint logic_op_enable:1;
GLuint pad2:1;
GLuint write_disable_b:1;
GLuint write_disable_g:1;
GLuint write_disable_r:1;
GLuint write_disable_a:1;
GLuint pad3:1;
GLuint alpha_to_coverage_dither:1;
GLuint alpha_to_one:1;
GLuint alpha_to_coverage:1;
} blend1;
};
struct gen6_color_calc_state
{
struct {
GLuint alpha_test_format:1;
GLuint pad0:14;
GLuint round_disable:1;
GLuint bf_stencil_ref:8;
GLuint stencil_ref:8;
} cc0;
union {
GLfloat alpha_ref_f;
struct {
GLuint ui:8;
GLuint pad0:24;
} alpha_ref_fi;
} cc1;
GLfloat constant_r;
GLfloat constant_g;
GLfloat constant_b;
GLfloat constant_a;
};
struct gen6_depth_stencil_state
{
struct {
GLuint pad0:3;
GLuint bf_stencil_pass_depth_pass_op:3;
GLuint bf_stencil_pass_depth_fail_op:3;
GLuint bf_stencil_fail_op:3;
GLuint bf_stencil_func:3;
GLuint bf_stencil_enable:1;
GLuint pad1:2;
GLuint stencil_write_enable:1;
GLuint stencil_pass_depth_pass_op:3;
GLuint stencil_pass_depth_fail_op:3;
GLuint stencil_fail_op:3;
GLuint stencil_func:3;
GLuint stencil_enable:1;
} ds0;
struct {
GLuint bf_stencil_write_mask:8;
GLuint bf_stencil_test_mask:8;
GLuint stencil_write_mask:8;
GLuint stencil_test_mask:8;
} ds1;
struct {
GLuint pad0:26;
GLuint depth_write_enable:1;
GLuint depth_test_func:3;
GLuint pad1:1;
GLuint depth_test_enable:1;
} ds2;
};
struct brw_cc_unit_state
{
@ -814,6 +912,13 @@ struct brw_sf_unit_state
};
struct gen6_scissor_rect
{
GLuint xmin:16;
GLuint ymin:16;
GLuint xmax:16;
GLuint ymax:16;
};
struct brw_gs_unit_state
{
@ -825,7 +930,7 @@ struct brw_gs_unit_state
struct
{
GLuint pad0:8;
GLuint rendering_enable:1; /* for IGDNG */
GLuint rendering_enable:1; /* for Ironlake */
GLuint pad4:1;
GLuint stats_enable:1;
GLuint nr_urb_entries:7;
@ -935,7 +1040,7 @@ struct brw_wm_unit_state
GLfloat global_depth_offset_constant;
GLfloat global_depth_offset_scale;
/* for IGDNG only */
/* for Ironlake only */
struct {
GLuint pad0:1;
GLuint grf_reg_count_1:3;
@ -962,6 +1067,15 @@ struct brw_sampler_default_color {
GLfloat color[4];
};
struct gen5_sampler_default_color {
uint8_t ub[4];
float f[4];
uint16_t hf[4];
uint16_t us[4];
int16_t s[4];
uint8_t b[4];
};
struct brw_sampler_state
{
@ -973,7 +1087,7 @@ struct brw_sampler_state
GLuint mag_filter:3;
GLuint mip_filter:2;
GLuint base_level:5;
GLuint pad:1;
GLuint min_mag_neq:1;
GLuint lod_preclamp:1;
GLuint default_color_mode:1;
GLuint pad0:1;
@ -985,7 +1099,8 @@ struct brw_sampler_state
GLuint r_wrap_mode:3;
GLuint t_wrap_mode:3;
GLuint s_wrap_mode:3;
GLuint pad:3;
GLuint cube_control_mode:1;
GLuint pad:2;
GLuint max_lod:10;
GLuint min_lod:10;
} ss1;
@ -999,7 +1114,9 @@ struct brw_sampler_state
struct brw_ss3
{
GLuint pad:19;
GLuint non_normalized_coord:1;
GLuint pad:12;
GLuint address_round:6;
GLuint max_aniso:3;
GLuint chroma_key_mode:1;
GLuint chroma_key_index:2;
@ -1044,6 +1161,15 @@ struct brw_sf_viewport
} scissor;
};
struct gen6_sf_viewport {
GLfloat m00;
GLfloat m11;
GLfloat m22;
GLfloat m30;
GLfloat m31;
GLfloat m32;
};
/* Documented in the subsystem/shared-functions/sampler chapter...
*/
struct brw_surface_state
@ -1055,7 +1181,12 @@ struct brw_surface_state
GLuint cube_neg_y:1;
GLuint cube_pos_x:1;
GLuint cube_neg_x:1;
GLuint pad:4;
GLuint pad:2;
/* Required on gen6 for surfaces accessed through render cache messages.
*/
GLuint render_cache_read_write:1;
/* Ironlake and newer: instead of replicating one of the texels */
GLuint cube_corner_average:1;
GLuint mipmap_layout_mode:1;
GLuint vert_line_stride_ofs:1;
GLuint vert_line_stride:1;
@ -1202,7 +1333,8 @@ struct brw_instruction
GLuint predicate_inverse:1;
GLuint execution_size:3;
GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
GLuint pad0:2;
GLuint acc_wr_control:1;
GLuint cmpt_control:1;
GLuint debug_control:1;
GLuint saturate:1;
} header;
@ -1250,7 +1382,7 @@ struct brw_instruction
GLuint dest_writemask:4;
GLuint dest_subreg_nr:1;
GLuint dest_reg_nr:8;
GLuint pad1:2;
GLuint dest_horiz_stride:2;
GLuint dest_address_mode:1;
} da16;
@ -1264,9 +1396,21 @@ struct brw_instruction
GLuint dest_writemask:4;
GLint dest_indirect_offset:6;
GLuint dest_subreg_nr:3;
GLuint pad1:2;
GLuint dest_horiz_stride:2;
GLuint dest_address_mode:1;
} ia16;
struct {
GLuint dest_reg_file:2;
GLuint dest_reg_type:3;
GLuint src0_reg_file:2;
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;
GLuint src1_reg_type:3;
GLuint pad:1;
GLint jump_count:16;
} branch_gen6;
} bits1;
@ -1339,7 +1483,7 @@ struct brw_instruction
GLuint end_of_thread:1;
GLuint pad1:1;
GLuint sfid:4;
} send_igdng; /* for IGDNG only */
} send_gen5; /* for Ironlake only */
} bits2;
@ -1413,6 +1557,21 @@ struct brw_instruction
GLuint pad0:12;
} if_else;
struct
{
/* Signed jump distance to the ip to jump to if all channels
* are disabled after the break or continue. It should point
* to the end of the innermost control flow block, as that's
* where some channel could get re-enabled.
*/
int jip:16;
/* Signed jump distance to the location to resume execution
* of this channel if it's enabled for the break or continue.
*/
int uip:16;
} break_cont;
struct {
GLuint function:4;
GLuint int_type:1;
@ -1440,7 +1599,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} math_igdng;
} math_gen5;
struct {
GLuint binding_table_index:8;
@ -1476,7 +1635,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} sampler_igdng;
} sampler_gen5;
struct brw_urb_immediate urb;
@ -1494,7 +1653,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} urb_igdng;
} urb_gen5;
struct {
GLuint binding_table_index:8;
@ -1508,6 +1667,18 @@ struct brw_instruction
GLuint end_of_thread:1;
} dp_read;
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint msg_type:3;
GLuint target_cache:2;
GLuint response_length:4;
GLuint msg_length:4;
GLuint msg_target:4;
GLuint pad1:3;
GLuint end_of_thread:1;
} dp_read_g4x;
struct {
GLuint binding_table_index:8;
GLuint msg_control:3;
@ -1519,7 +1690,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} dp_read_igdng;
} dp_read_gen5;
struct {
GLuint binding_table_index:8;
@ -1546,10 +1717,38 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} dp_write_igdng;
} dp_write_gen5;
/* Sandybridge DP for sample cache, constant cache, render cache */
struct {
GLuint binding_table_index:8;
GLuint msg_control:5;
GLuint msg_type:3;
GLuint pad0:3;
GLuint header_present:1;
GLuint response_length:5;
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} dp_sampler_const_cache;
struct {
GLuint pad:16;
GLuint binding_table_index:8;
GLuint msg_control:3;
GLuint slot_group_select:1;
GLuint pixel_scoreboard_clear:1;
GLuint msg_type:4;
GLuint send_commit_msg:1;
GLuint pad0:1;
GLuint header_present:1;
GLuint response_length:5;
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} dp_render_cache;
struct {
GLuint function_control:16;
GLuint response_length:4;
GLuint msg_length:4;
GLuint msg_target:4;
@ -1557,14 +1756,15 @@ struct brw_instruction
GLuint end_of_thread:1;
} generic;
/* Of this struct, only end_of_thread is not present for gen6. */
struct {
GLuint pad:19;
GLuint function_control:19;
GLuint header_present:1;
GLuint response_length:5;
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} generic_igdng;
} generic_gen5;
GLint d;
GLuint ud;

2
src/gallium/drivers/i965/brw_structs_dump.c
View file

@ -72,7 +72,7 @@ brw_dump_aa_line_parameters(const struct brw_aa_line_parameters *ptr)
{
debug_printf("\t\t.header.length = 0x%x\n", (*ptr).header.length);
debug_printf("\t\t.header.opcode = 0x%x\n", (*ptr).header.opcode);
debug_printf("\t\t.bits0.aa_coverage_scope = 0x%x\n", (*ptr).bits0.aa_coverage_scope);
debug_printf("\t\t.bits0.aa_coverage_scope = 0x%x\n", (*ptr).bits0.aa_coverage_slope);
debug_printf("\t\t.bits0.aa_coverage_bias = 0x%x\n", (*ptr).bits0.aa_coverage_bias);
debug_printf("\t\t.bits1.aa_coverage_endcap_slope = 0x%x\n", (*ptr).bits1.aa_coverage_endcap_slope);
debug_printf("\t\t.bits1.aa_coverage_endcap_bias = 0x%x\n", (*ptr).bits1.aa_coverage_endcap_bias);

4
src/gallium/drivers/i965/brw_urb.c
View file

@ -147,7 +147,7 @@ static int recalculate_urb_fence( struct brw_context *brw )
brw->urb.constrained = 0;
if (BRW_IS_IGDNG(brw)) {
if (brw->gen == 5) {
brw->urb.nr_vs_entries = 128;
brw->urb.nr_sf_entries = 48;
if (check_urb_layout(brw)) {
@ -157,7 +157,7 @@ static int recalculate_urb_fence( struct brw_context *brw )
brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
}
} else if (BRW_IS_G4X(brw)) {
} else if (brw->is_g4x) {
brw->urb.nr_vs_entries = 64;
if (check_urb_layout(brw)) {
goto done;

1
src/gallium/drivers/i965/brw_vs.h
View file

@ -56,7 +56,6 @@ struct brw_vs_compile {
struct brw_compile func;
struct brw_vs_prog_key key;
struct brw_vs_prog_data prog_data;
struct brw_chipset chipset;
struct brw_vertex_shader *vp;

17
src/gallium/drivers/i965/brw_vs_emit.c
View file

@ -116,6 +116,7 @@ static boolean find_output_slot( struct brw_vs_compile *c,
*/
static void brw_vs_alloc_regs( struct brw_vs_compile *c )
{
struct brw_context *brw = c->func.brw;
GLuint i, reg = 0, subreg = 0, mrf;
int attributes_in_vue;
@ -218,7 +219,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
*/
c->nr_outputs = c->prog_data.nr_outputs;
if (c->chipset.is_igdng)
if (brw->gen == 5)
mrf = 8;
else
mrf = 4;
@ -333,7 +334,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
*/
attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
if (c->chipset.is_igdng)
if (brw->gen == 5)
c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
else
c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
@ -1124,6 +1125,7 @@ static struct brw_reg get_dst( struct brw_vs_compile *c,
static void emit_vertex_write( struct brw_vs_compile *c)
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
struct brw_reg m0 = brw_message_reg(0);
struct brw_reg pos = c->regs[TGSI_FILE_OUTPUT][VERT_RESULT_HPOS];
struct brw_reg ndc;
@ -1143,7 +1145,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
*/
if (c->prog_data.writes_psiz ||
c->key.nr_userclip ||
c->chipset.is_965)
brw->has_negative_rhw_bug)
{
struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
GLuint i;
@ -1174,7 +1176,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
* Later, clipping will detect ucp[6] and ensure the primitive is
* clipped against all fixed planes.
*/
if (c->chipset.is_965) {
if (brw->has_negative_rhw_bug) {
brw_CMP(p,
vec8(brw_null_reg()),
BRW_CONDITIONAL_L,
@ -1202,7 +1204,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, offset(m0, 2), ndc);
if (c->chipset.is_igdng) {
if (brw->gen == 5) {
/* There are 20 DWs (D0-D19) in VUE vertex header on IGDNG */
brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */
/* m4, m5 contain the distances from vertex to the user clip planeXXX.
@ -1339,6 +1341,7 @@ static void emit_insn(struct brw_vs_compile *c,
unsigned opcode = inst->Instruction.Opcode;
unsigned label = inst->Label.Label;
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
struct brw_reg args[3], dst;
GLuint i;
@ -1514,7 +1517,7 @@ static void emit_insn(struct brw_vs_compile *c,
c->loop_depth--;
if (c->chipset.is_igdng)
if (brw->gen == 5)
br = 2;
inst0 = inst1 = brw_WHILE(p, c->loop_inst[c->loop_depth]);
@ -1652,6 +1655,6 @@ void brw_vs_emit(struct brw_vs_compile *c)
if (BRW_DEBUG & DEBUG_VS) {
debug_printf("vs-native:\n");
brw_disasm(stderr, p->store, p->nr_insn);
brw_disasm(stderr, p->store, p->nr_insn, p->brw->gen);
}
}

8
src/gallium/drivers/i965/brw_vs_state.c
View file

@ -100,7 +100,7 @@ vs_unit_create_from_key(struct brw_context *brw,
*/
vs.thread1.single_program_flow = 0;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
else
vs.thread1.binding_table_entry_count = key->nr_surfaces;
@ -111,16 +111,16 @@ vs_unit_create_from_key(struct brw_context *brw,
vs.thread3.urb_entry_read_offset = 0;
vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2;
else
vs.thread4.nr_urb_entries = key->nr_urb_entries;
vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
chipset_max_threads = 72;
else if (BRW_IS_G4X(brw))
else if (brw->is_g4x)
chipset_max_threads = 32;
else
chipset_max_threads = 16;

4
src/gallium/drivers/i965/brw_winsys.h
View file

@ -148,7 +148,7 @@ static INLINE void make_reloc(struct brw_winsys_reloc *reloc,
struct brw_winsys_screen {
unsigned pci_id;
int gen;
/**
* Buffer functions.
*/
@ -282,7 +282,7 @@ void brw_dump_data( unsigned pci_id,
enum brw_buffer_data_type data_type,
unsigned offset,
const void *data,
size_t size );
size_t size, int gen );
#endif

6
src/gallium/drivers/i965/brw_winsys_debug.c
View file

@ -9,7 +9,7 @@ void brw_dump_data( unsigned pci_id,
enum brw_buffer_data_type data_type,
unsigned offset,
const void *data,
size_t size )
size_t size, int gen )
{
if (BRW_DUMP & DUMP_ASM) {
switch (data_type) {
@ -18,7 +18,7 @@ void brw_dump_data( unsigned pci_id,
case BRW_DATA_GS_VS_PROG:
case BRW_DATA_GS_GS_PROG:
case BRW_DATA_GS_CLIP_PROG:
brw_disasm( stderr, data, size / sizeof(struct brw_instruction) );
brw_disasm( stderr, (struct brw_instruction *)data, size / sizeof(struct brw_instruction), gen );
break;
default:
break;
@ -77,7 +77,7 @@ void brw_dump_data( unsigned pci_id,
if (BRW_DUMP & DUMP_BATCH) {
switch (data_type) {
case BRW_DATA_BATCH_BUFFER:
intel_decode(data, size / 4, offset, pci_id);
intel_decode(data, size / 4, offset, pci_id, 0);
break;
default:
break;

12
src/gallium/drivers/i965/brw_wm_emit.c
View file

@ -848,11 +848,11 @@ static void emit_tex( struct brw_wm_compile *c,
responseLength = 8; /* always */
if (BRW_IS_IGDNG(p->brw)) {
if (p->brw->gen == 5) {
if (shadow)
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE_IGDNG;
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
else
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_IGDNG;
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
} else {
if (shadow)
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
@ -917,8 +917,8 @@ static void emit_txb( struct brw_wm_compile *c,
brw_MOV(p, brw_message_reg(8), coord[3]);
msgLength = 9;
if (BRW_IS_IGDNG(p->brw))
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS_IGDNG;
if (p->brw->gen == 5)
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
else
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
@ -1516,6 +1516,6 @@ void brw_wm_emit( struct brw_wm_compile *c )
if (BRW_DEBUG & DEBUG_WM) {
debug_printf("wm-native:\n");
brw_disasm(stderr, p->store, p->nr_insn);
brw_disasm(stderr, p->store, p->nr_insn, p->brw->gen);
}
}

6
src/gallium/drivers/i965/brw_wm_glsl.c
View file

@ -1607,7 +1607,7 @@ static void emit_txb(struct brw_wm_compile *c,
brw_MOV(p, brw_message_reg(5), src[3]); /* bias */
brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); /* ref (unused?) */
if (BRW_IS_IGDNG(p->brw)) {
if (p->brw->gen == 5) {
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_IGDNG;
} else {
/* Does it work well on SIMD8? */
@ -1688,7 +1688,7 @@ static void emit_tex(struct brw_wm_compile *c,
brw_MOV(p, brw_message_reg(6), src[2]); /* ref value / R coord */
}
if (BRW_IS_IGDNG(p->brw)) {
if (p->brw->gen == 5) {
if (shadow)
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_COMPARE_IGDNG;
else
@ -1970,7 +1970,7 @@ static void brw_wm_emit_branching_shader(struct brw_context *brw, struct brw_wm_
struct brw_instruction *inst0, *inst1;
GLuint br = 1;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
br = 2;
loop_depth--;

10
src/gallium/drivers/i965/brw_wm_state.c
View file

@ -70,9 +70,9 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
key->max_threads = 1;
else {
/* WM maximum threads is number of EUs times number of threads per EU. */
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
key->max_threads = 12 * 6;
else if (BRW_IS_G4X(brw))
else if (brw->is_g4x)
key->max_threads = 10 * 5;
else
key->max_threads = 8 * 4;
@ -155,7 +155,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
wm.thread1.depth_coef_urb_read_offset = 1;
wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
else
wm.thread1.binding_table_entry_count = key->nr_surfaces;
@ -174,7 +174,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
if (BRW_IS_IGDNG(brw))
if (brw->gen == 5)
wm.wm4.sampler_count = 0; /* hardware requirement */
else
wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
@ -277,7 +277,7 @@ static enum pipe_error upload_wm_unit( struct brw_context *brw )
grf_reg_count = (align(key.total_grf, 16) / 16 - 1);
per_thread_scratch_space = key.total_scratch / 1024 - 1;
stats_enable = (BRW_DEBUG & DEBUG_STATS) || key.stats_wm;
sampler_count = BRW_IS_IGDNG(brw) ? 0 :(key.sampler_count + 1) / 4;
sampler_count = brw->gen == 5 ? 0 :(key.sampler_count + 1) / 4;
/* Emit WM program relocation */
make_reloc(&reloc[nr_reloc++],

559
src/gallium/drivers/i965/intel_decode.c
View file

@ -42,10 +42,11 @@
#include "util/u_memory.h"
#include "util/u_string.h"
#include "intel_decode.h"
#include "brw_reg.h"
/*#include "intel_chipset.h"*/
#define IS_965(x) 1 /* XXX */
#define IS_9XX(x) 1 /* XXX */
#define BUFFER_FAIL(_count, _len, _name) do { \
@ -99,10 +100,11 @@ decode_mi(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
} opcodes_mi[] = {
{ 0x08, 0, 1, 1, "MI_ARB_ON_OFF" },
{ 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" },
{ 0x30, 0x3f, 3, 3, "MI_BATCH_BUFFER" },
{ 0x31, 0x3f, 2, 2, "MI_BATCH_BUFFER_START" },
{ 0x14, 0x3f, 3, 3, "MI_DISPLAY_BUFFER_INFO" },
{ 0x04, 0, 1, 1, "MI_FLUSH" },
{ 0x22, 0, 3, 3, "MI_LOAD_REGISTER_IMM" },
{ 0x22, 0x1f, 3, 3, "MI_LOAD_REGISTER_IMM" },
{ 0x13, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_EXCL" },
{ 0x12, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_INCL" },
{ 0x00, 0, 1, 1, "MI_NOOP" },
@ -116,6 +118,11 @@ decode_mi(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
{ 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT" },
};
switch ((data[0] & 0x1f800000) >> 23) {
case 0x0a:
instr_out(data, hw_offset, 0, "MI_BATCH_BUFFER_END\n");
return -1;
}
for (opcode = 0; opcode < Elements(opcodes_mi); opcode++) {
if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) {
@ -308,9 +315,13 @@ decode_2d(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
static int
decode_3d_1c(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
{
switch ((data[0] & 0x00f80000) >> 19) {
uint32_t opcode;
opcode = (data[0] & 0x00f80000) >> 19;
switch (opcode) {
case 0x11:
instr_out(data, hw_offset, 0, "3DSTATE_DEPTH_SUBRECTANGLE_DISALBE\n");
instr_out(data, hw_offset, 0, "3DSTATE_DEPTH_SUBRECTANGLE_DISABLE\n");
return 1;
case 0x10:
instr_out(data, hw_offset, 0, "3DSTATE_SCISSOR_ENABLE\n");
@ -326,7 +337,8 @@ decode_3d_1c(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
return 1;
}
instr_out(data, hw_offset, 0, "3D UNKNOWN\n");
instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_1c opcode = 0x%x\n",
opcode);
(*failures)++;
return 1;
}
@ -384,7 +396,7 @@ i915_get_instruction_dst(const uint32_t *data, int i, char *dstname, int do_mask
sprintf(dstname, "oD%s%s", dstmask, sat);
break;
case 6:
if (dst_nr > 2)
if (dst_nr > 3)
fprintf(out, "bad destination reg U%d\n", dst_nr);
sprintf(dstname, "U%d%s%s", dst_nr, dstmask, sat);
break;
@ -455,7 +467,7 @@ i915_get_instruction_src_name(uint32_t src_type, uint32_t src_nr, char *name)
break;
case 6:
sprintf(name, "U%d", src_nr);
if (src_nr > 2)
if (src_nr > 3)
fprintf(out, "bad src reg %s\n", name);
break;
default:
@ -800,10 +812,14 @@ i915_decode_instruction(const uint32_t *data, uint32_t hw_offset,
}
static int
decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures, int i830)
decode_3d_1d(const uint32_t *data, int count,
uint32_t hw_offset,
uint32_t devid,
int *failures)
{
unsigned int len, i, c, opcode, word, map, sampler, instr;
unsigned int len, i, c, idx, word, map, sampler, instr;
char *format;
uint32_t opcode;
struct {
uint32_t opcode;
@ -814,7 +830,7 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
} opcodes_3d_1d[] = {
{ 0x8e, 0, 3, 3, "3DSTATE_BUFFER_INFO" },
{ 0x86, 0, 4, 4, "3DSTATE_CHROMA_KEY" },
{ 0x9c, 0, 1, 1, "3DSTATE_CLEAR_PARAMETERS" },
{ 0x9c, 0, 7, 7, "3DSTATE_CLEAR_PARAMETERS" },
{ 0x88, 0, 2, 2, "3DSTATE_CONSTANT_BLEND_COLOR" },
{ 0x99, 0, 2, 2, "3DSTATE_DEFAULT_DIFFUSE" },
{ 0x9a, 0, 2, 2, "3DSTATE_DEFAULT_SPECULAR" },
@ -822,7 +838,6 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
{ 0x97, 0, 2, 2, "3DSTATE_DEPTH_OFFSET_SCALE" },
{ 0x85, 0, 2, 2, "3DSTATE_DEST_BUFFER_VARIABLES" },
{ 0x80, 0, 5, 5, "3DSTATE_DRAWING_RECTANGLE" },
{ 0x8e, 0, 3, 3, "3DSTATE_BUFFER_INFO" },
{ 0x9d, 0, 65, 65, "3DSTATE_FILTER_COEFFICIENTS_4X4" },
{ 0x9e, 0, 4, 4, "3DSTATE_MONO_FILTER" },
{ 0x89, 0, 4, 4, "3DSTATE_FOG_MODE" },
@ -834,9 +849,11 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
{ 0x8d, 1, 3, 3, "3DSTATE_W_STATE_I830" },
{ 0x01, 1, 2, 2, "3DSTATE_COLOR_FACTOR_I830" },
{ 0x02, 1, 2, 2, "3DSTATE_MAP_COORD_SETBIND_I830" },
};
}, *opcode_3d_1d;
switch ((data[0] & 0x00ff0000) >> 16) {
opcode = (data[0] & 0x00ff0000) >> 16;
switch (opcode) {
case 0x07:
/* This instruction is unusual. A 0 length means just 1 DWORD instead of
* 2. The 0 length is specified in one place to be unsupported, but
@ -891,26 +908,56 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
instr_out(data, hw_offset, 0, "3DSTATE_LOAD_STATE_IMMEDIATE_1\n");
len = (data[0] & 0x0000000f) + 2;
i = 1;
for (word = 0; word <= 7; word++) {
for (word = 0; word <= 8; word++) {
if (data[0] & (1 << (4 + word))) {
if (i >= count)
BUFFER_FAIL(count, len, "3DSTATE_LOAD_STATE_IMMEDIATE_1");
/* save vertex state for decode */
if (word == 2) {
saved_s2_set = 1;
saved_s2 = data[i];
}
if (word == 4) {
saved_s4_set = 1;
saved_s4 = data[i];
if (IS_9XX(devid)) {
if (word == 2) {
saved_s2_set = 1;
saved_s2 = data[i];
}
if (word == 4) {
saved_s4_set = 1;
saved_s4 = data[i];
}
}
instr_out(data, hw_offset, i++, "S%d\n", word);
}
}
if (len != i) {
fprintf(out, "Bad count in 3DSTATE_LOAD_INDIRECT\n");
fprintf(out, "Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_1\n");
(*failures)++;
}
return len;
case 0x03:
instr_out(data, hw_offset, 0, "3DSTATE_LOAD_STATE_IMMEDIATE_2\n");
len = (data[0] & 0x0000000f) + 2;
i = 1;
for (word = 6; word <= 14; word++) {
if (data[0] & (1 << word)) {
if (i >= count)
BUFFER_FAIL(count, len, "3DSTATE_LOAD_STATE_IMMEDIATE_2");
if (word == 6)
instr_out(data, hw_offset, i++, "TBCF\n");
else if (word >= 7 && word <= 10) {
instr_out(data, hw_offset, i++, "TB%dC\n", word - 7);
instr_out(data, hw_offset, i++, "TB%dA\n", word - 7);
} else if (word >= 11 && word <= 14) {
instr_out(data, hw_offset, i++, "TM%dS0\n", word - 11);
instr_out(data, hw_offset, i++, "TM%dS1\n", word - 11);
instr_out(data, hw_offset, i++, "TM%dS2\n", word - 11);
instr_out(data, hw_offset, i++, "TM%dS3\n", word - 11);
instr_out(data, hw_offset, i++, "TM%dS4\n", word - 11);
}
}
}
if (len != i) {
fprintf(out, "Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_2\n");
(*failures)++;
}
return len;
@ -922,11 +969,27 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
i = 2;
for (map = 0; map <= 15; map++) {
if (data[1] & (1 << map)) {
int width, height, pitch, dword;
const char *tiling;
if (i + 3 >= count)
BUFFER_FAIL(count, len, "3DSTATE_MAP_STATE");
instr_out(data, hw_offset, i++, "map %d MS2\n", map);
instr_out(data, hw_offset, i++, "map %d MS3\n", map);
instr_out(data, hw_offset, i++, "map %d MS4\n", map);
dword = data[i];
width = ((dword >> 10) & ((1 << 11) - 1))+1;
height = ((dword >> 21) & ((1 << 11) - 1))+1;
tiling = "none";
if (dword & (1 << 2))
tiling = "fenced";
else if (dword & (1 << 1))
tiling = dword & (1 << 0) ? "Y" : "X";
instr_out(data, hw_offset, i++, "map %d MS3 [width=%d, height=%d, tiling=%s]\n", map, width, height, tiling);
dword = data[i];
pitch = 4*(((dword >> 21) & ((1 << 11) - 1))+1);
instr_out(data, hw_offset, i++, "map %d MS4 [pitch=%d]\n", map, pitch);
}
}
if (len != i) {
@ -982,8 +1045,8 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
}
return len;
case 0x01:
if (i830)
break;
if (!IS_9XX(devid))
break;
instr_out(data, hw_offset, 0, "3DSTATE_SAMPLER_STATE\n");
instr_out(data, hw_offset, 1, "mask\n");
len = (data[0] & 0x0000003f) + 2;
@ -1034,30 +1097,61 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
format,
(data[1] & (1 << 31)) ? "en" : "dis");
return len;
case 0x8e:
{
const char *name, *tiling;
len = (data[0] & 0x0000000f) + 2;
if (len != 3)
fprintf(out, "Bad count in 3DSTATE_BUFFER_INFO\n");
if (count < 3)
BUFFER_FAIL(count, len, "3DSTATE_BUFFER_INFO");
switch((data[1] >> 24) & 0x7) {
case 0x3: name = "color"; break;
case 0x7: name = "depth"; break;
default: name = "unknown"; break;
}
tiling = "none";
if (data[1] & (1 << 23))
tiling = "fenced";
else if (data[1] & (1 << 22))
tiling = data[1] & (1 << 21) ? "Y" : "X";
instr_out(data, hw_offset, 0, "3DSTATE_BUFFER_INFO\n");
instr_out(data, hw_offset, 1, "%s, tiling = %s, pitch=%d\n", name, tiling, data[1]&0xffff);
instr_out(data, hw_offset, 2, "address\n");
return len;
}
}
for (opcode = 0; opcode < Elements(opcodes_3d_1d); opcode++) {
if (opcodes_3d_1d[opcode].i830_only && !i830)
for (idx = 0; idx < Elements(opcodes_3d_1d); idx++)
{
opcode_3d_1d = &opcodes_3d_1d[idx];
if (opcode_3d_1d->i830_only && IS_9XX(devid))
continue;
if (((data[0] & 0x00ff0000) >> 16) == opcodes_3d_1d[opcode].opcode) {
if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) {
len = 1;
instr_out(data, hw_offset, 0, "%s\n", opcodes_3d_1d[opcode].name);
if (opcodes_3d_1d[opcode].max_len > 1) {
instr_out(data, hw_offset, 0, "%s\n", opcode_3d_1d->name);
if (opcode_3d_1d->max_len > 1) {
len = (data[0] & 0x0000ffff) + 2;
if (len < opcodes_3d_1d[opcode].min_len ||
len > opcodes_3d_1d[opcode].max_len)
if (len < opcode_3d_1d->min_len ||
len > opcode_3d_1d->max_len)
{
fprintf(out, "Bad count in %s\n",
opcodes_3d_1d[opcode].name);
opcode_3d_1d->name);
(*failures)++;
}
}
for (i = 1; i < len; i++) {
if (i >= count)
BUFFER_FAIL(count, len, opcodes_3d_1d[opcode].name);
BUFFER_FAIL(count, len, opcode_3d_1d->name);
instr_out(data, hw_offset, i, "dword %d\n", i);
}
@ -1065,7 +1159,7 @@ decode_3d_1d(const uint32_t *data, int count, uint32_t hw_offset, int *failures,
}
}
instr_out(data, hw_offset, 0, "3D UNKNOWN\n");
instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_1d opcode = 0x%x\n", opcode);
(*failures)++;
return 1;
}
@ -1075,8 +1169,10 @@ decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset,
int *failures)
{
char immediate = (data[0] & (1 << 23)) == 0;
unsigned int len, i;
unsigned int len, i, ret;
char *primtype;
int original_s2 = saved_s2;
int original_s4 = saved_s4;
switch ((data[0] >> 18) & 0xf) {
case 0x0: primtype = "TRILIST"; break;
@ -1089,7 +1185,7 @@ decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset,
case 0x7: primtype = "RECTLIST"; break;
case 0x8: primtype = "POINTLIST"; break;
case 0x9: primtype = "DIB"; break;
case 0xa: primtype = "CLEAR_RECT"; break;
case 0xa: primtype = "CLEAR_RECT"; saved_s4 = 3 << 6; saved_s2 = ~0; break;
default: primtype = "unknown"; break;
}
@ -1193,6 +1289,8 @@ decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset,
vertex++;
}
}
ret = len;
} else {
/* indirect vertices */
len = data[0] & 0x0000ffff; /* index count */
@ -1210,13 +1308,15 @@ decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset,
if ((data[i] & 0xffff) == 0xffff) {
instr_out(data, hw_offset, i,
" indices: (terminator)\n");
return i;
ret = i;
goto out;
} else if ((data[i] >> 16) == 0xffff) {
instr_out(data, hw_offset, i,
" indices: 0x%04x, "
"(terminator)\n",
data[i] & 0xffff);
return i;
ret = i;
goto out;
} else {
instr_out(data, hw_offset, i,
" indices: 0x%04x, 0x%04x\n",
@ -1226,7 +1326,8 @@ decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset,
fprintf(out,
"3DPRIMITIVE: no terminator found in index buffer\n");
(*failures)++;
return count;
ret = count;
goto out;
} else {
/* fixed size vertex index buffer */
for (i = 0; i < len; i += 2) {
@ -1241,7 +1342,8 @@ decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset,
}
}
}
return (len + 1) / 2 + 1;
ret = (len + 1) / 2 + 1;
goto out;
} else {
/* sequential vertex access */
if (count < 2)
@ -1250,17 +1352,22 @@ decode_3d_primitive(const uint32_t *data, int count, uint32_t hw_offset,
"3DPRIMITIVE sequential indirect %s, %d starting from "
"%d\n", primtype, len, data[1] & 0xffff);
instr_out(data, hw_offset, 1, " start\n");
return 2;
ret = 2;
goto out;
}
}
return len;
out:
saved_s2 = original_s2;
saved_s4 = original_s4;
return ret;
}
static int
decode_3d(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
decode_3d(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures)
{
unsigned int opcode;
uint32_t opcode;
unsigned int idx;
struct {
uint32_t opcode;
@ -1277,41 +1384,44 @@ decode_3d(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
{ 0x0d, 1, 1, "3DSTATE_MODES_4" },
{ 0x0c, 1, 1, "3DSTATE_MODES_5" },
{ 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES" },
};
}, *opcode_3d;
switch ((data[0] & 0x1f000000) >> 24) {
opcode = (data[0] & 0x1f000000) >> 24;
switch (opcode) {
case 0x1f:
return decode_3d_primitive(data, count, hw_offset, failures);
case 0x1d:
return decode_3d_1d(data, count, hw_offset, failures, 0);
return decode_3d_1d(data, count, hw_offset, devid, failures);
case 0x1c:
return decode_3d_1c(data, count, hw_offset, failures);
}
for (opcode = 0; opcode < Elements(opcodes_3d); opcode++) {
if ((data[0] & 0x1f000000) >> 24 == opcodes_3d[opcode].opcode) {
for (idx = 0; idx < Elements(opcodes_3d); idx++) {
opcode_3d = &opcodes_3d[idx];
if (opcode == opcode_3d->opcode) {
unsigned int len = 1, i;
instr_out(data, hw_offset, 0, "%s\n", opcodes_3d[opcode].name);
if (opcodes_3d[opcode].max_len > 1) {
instr_out(data, hw_offset, 0, "%s\n", opcode_3d->name);
if (opcode_3d->max_len > 1) {
len = (data[0] & 0xff) + 2;
if (len < opcodes_3d[opcode].min_len ||
len > opcodes_3d[opcode].max_len)
if (len < opcode_3d->min_len ||
len > opcode_3d->max_len)
{
fprintf(out, "Bad count in %s\n", opcodes_3d[opcode].name);
fprintf(out, "Bad count in %s\n", opcode_3d->name);
}
}
for (i = 1; i < len; i++) {
if (i >= count)
BUFFER_FAIL(count, len, opcodes_3d[opcode].name);
BUFFER_FAIL(count, len, opcode_3d->name);
instr_out(data, hw_offset, i, "dword %d\n", i);
}
return len;
}
}
instr_out(data, hw_offset, 0, "3D UNKNOWN\n");
instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d opcode = 0x%x\n", opcode);
(*failures)++;
return 1;
}
@ -1401,12 +1511,87 @@ get_965_prim_type(uint32_t data)
default: return "fail";
}
}
static int
i965_decode_urb_fence(const uint32_t *data, uint32_t hw_offset, int len, int count,
int *failures)
{
uint32_t vs_fence, clip_fence, gs_fence, sf_fence, vfe_fence, cs_fence;
if (len != 3)
fprintf(out, "Bad count in URB_FENCE\n");
if (count < 3)
BUFFER_FAIL(count, len, "URB_FENCE");
vs_fence = data[1] & 0x3ff;
gs_fence = (data[1] >> 10) & 0x3ff;
clip_fence = (data[1] >> 20) & 0x3ff;
sf_fence = data[2] & 0x3ff;
vfe_fence = (data[2] >> 10) & 0x3ff;
cs_fence = (data[2] >> 20) & 0x7ff;
instr_out(data, hw_offset, 0, "URB_FENCE: %s%s%s%s%s%s\n",
(data[0] >> 13) & 1 ? "cs " : "",
(data[0] >> 12) & 1 ? "vfe " : "",
(data[0] >> 11) & 1 ? "sf " : "",
(data[0] >> 10) & 1 ? "clip " : "",
(data[0] >> 9) & 1 ? "gs " : "",
(data[0] >> 8) & 1 ? "vs " : "");
instr_out(data, hw_offset, 1,
"vs fence: %d, clip_fence: %d, gs_fence: %d\n",
vs_fence, clip_fence, gs_fence);
instr_out(data, hw_offset, 2,
"sf fence: %d, vfe_fence: %d, cs_fence: %d\n",
sf_fence, vfe_fence, cs_fence);
if (gs_fence < vs_fence)
fprintf(out, "gs fence < vs fence!\n");
if (clip_fence < gs_fence)
fprintf(out, "clip fence < gs fence!\n");
if (sf_fence < clip_fence)
fprintf(out, "sf fence < clip fence!\n");
if (cs_fence < sf_fence)
fprintf(out, "cs fence < sf fence!\n");
return len;
}
static void
state_base_out(const uint32_t *data, uint32_t hw_offset, unsigned int index,
char *name)
{
if (data[index] & 1) {
instr_out(data, hw_offset, index, "%s state base address 0x%08x\n",
name, data[index] & ~1);
} else {
instr_out(data, hw_offset, index, "%s state base not updated\n",
name);
}
}
static void
state_max_out(const uint32_t *data, uint32_t hw_offset, unsigned int index,
char *name)
{
if (data[index] & 1) {
if (data[index] == 1) {
instr_out(data, hw_offset, index,
"%s state upper bound disabled\n", name);
} else {
instr_out(data, hw_offset, index, "%s state upper bound 0x%08x\n",
name, data[index] & ~1);
}
} else {
instr_out(data, hw_offset, index, "%s state upper bound not updated\n",
name);
}
}
static int
decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures)
{
unsigned int opcode, len;
int i;
uint32_t opcode;
unsigned int idx, len;
int i, sba_len;
char *desc1 = NULL;
struct {
uint32_t opcode;
@ -1435,51 +1620,78 @@ decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures
{ 0x7907, 33, 33, "3DSTATE_POLY_STIPPLE_PATTERN" },
{ 0x7908, 3, 3, "3DSTATE_LINE_STIPPLE" },
{ 0x7909, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" },
{ 0x7909, 2, 2, "3DSTATE_CLEAR_PARAMS" },
{ 0x790a, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" },
{ 0x790b, 4, 4, "3DSTATE_GS_SVB_INDEX" },
{ 0x790d, 3, 3, "3DSTATE_MULTISAMPLE" },
{ 0x7b00, 6, 6, "3DPRIMITIVE" },
};
{ 0x7802, 4, 4, "3DSTATE_SAMPLER_STATE_POINTERS" },
{ 0x7805, 3, 3, "3DSTATE_URB" },
{ 0x780e, 4, 4, "3DSTATE_CC_STATE_POINTERS" },
{ 0x7810, 6, 6, "3DSTATE_VS_STATE" },
{ 0x7811, 7, 7, "3DSTATE_GS_STATE" },
{ 0x7812, 4, 4, "3DSTATE_CLIP_STATE" },
{ 0x7813, 20, 20, "3DSTATE_SF_STATE" },
{ 0x7814, 9, 9, "3DSTATE_WM_STATE" },
{ 0x7812, 4, 4, "3DSTATE_CLIP_STATE" },
{ 0x7815, 5, 5, "3DSTATE_CONSTANT_VS_STATE" },
{ 0x7816, 5, 5, "3DSTATE_CONSTANT_GS_STATE" },
{ 0x7817, 5, 5, "3DSTATE_CONSTANT_PS_STATE" },
{ 0x7818, 2, 2, "3DSTATE_SAMPLE_MASK" },
}, *opcode_3d;
len = (data[0] & 0x0000ffff) + 2;
switch ((data[0] & 0xffff0000) >> 16) {
opcode = (data[0] & 0xffff0000) >> 16;
switch (opcode) {
case 0x6000:
len = (data[0] & 0x000000ff) + 2;
return i965_decode_urb_fence(data, hw_offset, len, count, failures);
case 0x6001:
instr_out(data, hw_offset, 0, "CS_URB_STATE\n");
instr_out(data, hw_offset, 1, "entry_size: %d [%d bytes], n_entries: %d\n",
(data[1] >> 4) & 0x1f,
(((data[1] >> 4) & 0x1f) + 1) * 64,
data[1] & 0x7);
return len;
case 0x6002:
len = (data[0] & 0x000000ff) + 2;
instr_out(data, hw_offset, 0, "CONSTANT_BUFFER: %s\n",
(data[0] >> 8) & 1 ? "valid" : "invalid");
instr_out(data, hw_offset, 1, "offset: 0x%08x, length: %d bytes\n",
data[1] & ~0x3f, ((data[1] & 0x3f) + 1) * 64);
return len;
case 0x6101:
if (len != 6)
if (IS_GEN6(devid))
sba_len = 10;
else if (IS_IRONLAKE(devid))
sba_len = 8;
else
sba_len = 6;
if (len != sba_len)
fprintf(out, "Bad count in STATE_BASE_ADDRESS\n");
if (count < 6)
if (len != sba_len)
BUFFER_FAIL(count, len, "STATE_BASE_ADDRESS");
i = 0;
instr_out(data, hw_offset, 0,
"STATE_BASE_ADDRESS\n");
i++;
if (data[1] & 1) {
instr_out(data, hw_offset, 1, "General state at 0x%08x\n",
data[1] & ~1);
} else
instr_out(data, hw_offset, 1, "General state not updated\n");
state_base_out(data, hw_offset, i++, "general");
state_base_out(data, hw_offset, i++, "surface");
if (IS_GEN6(devid))
state_base_out(data, hw_offset, i++, "dynamic");
state_base_out(data, hw_offset, i++, "indirect");
if (IS_IRONLAKE(devid) || IS_GEN6(devid))
state_base_out(data, hw_offset, i++, "instruction");
if (data[2] & 1) {
instr_out(data, hw_offset, 2, "Surface state at 0x%08x\n",
data[2] & ~1);
} else
instr_out(data, hw_offset, 2, "Surface state not updated\n");
if (data[3] & 1) {
instr_out(data, hw_offset, 3, "Indirect state at 0x%08x\n",
data[3] & ~1);
} else
instr_out(data, hw_offset, 3, "Indirect state not updated\n");
if (data[4] & 1) {
instr_out(data, hw_offset, 4, "General state upper bound 0x%08x\n",
data[4] & ~1);
} else
instr_out(data, hw_offset, 4, "General state not updated\n");
if (data[5] & 1) {
instr_out(data, hw_offset, 5, "Indirect state upper bound 0x%08x\n",
data[5] & ~1);
} else
instr_out(data, hw_offset, 5, "Indirect state not updated\n");
state_max_out(data, hw_offset, i++, "general");
if (IS_GEN6(devid))
state_max_out(data, hw_offset, i++, "dynamic");
state_max_out(data, hw_offset, i++, "indirect");
if (IS_IRONLAKE(devid) || IS_GEN6(devid))
state_max_out(data, hw_offset, i++, "instruction");
return len;
case 0x7800:
@ -1498,18 +1710,33 @@ decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures
instr_out(data, hw_offset, 6, "CC state\n");
return len;
case 0x7801:
if (len != 6)
len = (data[0] & 0x000000ff) + 2;
if (len != 6 && len != 4)
fprintf(out, "Bad count in 3DSTATE_BINDING_TABLE_POINTERS\n");
if (count < 6)
BUFFER_FAIL(count, len, "3DSTATE_BINDING_TABLE_POINTERS");
if (len == 6) {
if (count < 6)
BUFFER_FAIL(count, len, "3DSTATE_BINDING_TABLE_POINTERS");
instr_out(data, hw_offset, 0,
"3DSTATE_BINDING_TABLE_POINTERS\n");
instr_out(data, hw_offset, 1, "VS binding table\n");
instr_out(data, hw_offset, 2, "GS binding table\n");
instr_out(data, hw_offset, 3, "Clip binding table\n");
instr_out(data, hw_offset, 4, "SF binding table\n");
instr_out(data, hw_offset, 5, "WM binding table\n");
} else {
if (count < 4)
BUFFER_FAIL(count, len, "3DSTATE_BINDING_TABLE_POINTERS");
instr_out(data, hw_offset, 0,
"3DSTATE_BINDING_TABLE_POINTERS\n");
instr_out(data, hw_offset, 1, "VS binding table\n");
instr_out(data, hw_offset, 2, "GS binding table\n");
instr_out(data, hw_offset, 3, "Clip binding table\n");
instr_out(data, hw_offset, 4, "SF binding table\n");
instr_out(data, hw_offset, 5, "WM binding table\n");
instr_out(data, hw_offset, 0,
"3DSTATE_BINDING_TABLE_POINTERS: VS mod %d, "
"GS mod %d, PS mod %d\n",
(data[0] & (1 << 8)) != 0,
(data[0] & (1 << 9)) != 0,
(data[0] & (1 << 10)) != 0);
instr_out(data, hw_offset, 1, "VS binding table\n");
instr_out(data, hw_offset, 2, "GS binding table\n");
instr_out(data, hw_offset, 3, "WM binding table\n");
}
return len;
@ -1560,6 +1787,18 @@ decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures
}
return len;
case 0x780d:
len = (data[0] & 0xff) + 2;
if (len != 4)
fprintf(out, "Bad count in 3DSTATE_VIEWPORT_STATE_POINTERS\n");
if (count < len)
BUFFER_FAIL(count, len, "3DSTATE_VIEWPORT_STATE_POINTERS");
instr_out(data, hw_offset, 0, "3DSTATE_VIEWPORT_STATE_POINTERS\n");
instr_out(data, hw_offset, 1, "clip\n");
instr_out(data, hw_offset, 2, "sf\n");
instr_out(data, hw_offset, 3, "cc\n");
return len;
case 0x780a:
len = (data[0] & 0xff) + 2;
if (len != 3)
@ -1592,7 +1831,7 @@ decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures
return len;
case 0x7905:
if (len != 5 && len != 6)
if (len < 5 || len > 7)
fprintf(out, "Bad count in 3DSTATE_DEPTH_BUFFER\n");
if (count < len)
BUFFER_FAIL(count, len, "3DSTATE_DEPTH_BUFFER");
@ -1609,11 +1848,38 @@ decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures
((data[3] & 0x0007ffc0) >> 6) + 1,
((data[3] & 0xfff80000) >> 19) + 1);
instr_out(data, hw_offset, 4, "volume depth\n");
if (len == 6)
if (len >= 6)
instr_out(data, hw_offset, 5, "\n");
if (len >= 7)
instr_out(data, hw_offset, 6, "render target view extent\n");
return len;
case 0x7a00:
len = (data[0] & 0xff) + 2;
if (len != 4)
fprintf(out, "Bad count in PIPE_CONTROL\n");
if (count < len)
BUFFER_FAIL(count, len, "PIPE_CONTROL");
switch ((data[0] >> 14) & 0x3) {
case 0: desc1 = "no write"; break;
case 1: desc1 = "qword write"; break;
case 2: desc1 = "PS_DEPTH_COUNT write"; break;
case 3: desc1 = "TIMESTAMP write"; break;
}
instr_out(data, hw_offset, 0,
"PIPE_CONTROL: %s, %sdepth stall, %sRC write flush, "
"%sinst flush\n",
desc1,
data[0] & (1 << 13) ? "" : "no ",
data[0] & (1 << 12) ? "" : "no ",
data[0] & (1 << 11) ? "" : "no ");
instr_out(data, hw_offset, 1, "destination address\n");
instr_out(data, hw_offset, 2, "immediate dword low\n");
instr_out(data, hw_offset, 3, "immediate dword high\n");
return len;
case 0x7b00:
len = (data[0] & 0xff) + 2;
if (len != 6)
@ -1633,39 +1899,41 @@ decode_3d_965(const uint32_t *data, int count, uint32_t hw_offset, int *failures
return len;
}
for (opcode = 0; opcode < Elements(opcodes_3d); opcode++) {
if ((data[0] & 0xffff0000) >> 16 == opcodes_3d[opcode].opcode) {
for (idx = 0; idx < Elements(opcodes_3d); idx++) {
opcode_3d = &opcodes_3d[idx];
if ((data[0] & 0xffff0000) >> 16 == opcode_3d->opcode) {
unsigned int i;
len = 1;
instr_out(data, hw_offset, 0, "%s\n", opcodes_3d[opcode].name);
if (opcodes_3d[opcode].max_len > 1) {
instr_out(data, hw_offset, 0, "%s\n", opcode_3d->name);
if (opcode_3d->max_len > 1) {
len = (data[0] & 0xff) + 2;
if (len < opcodes_3d[opcode].min_len ||
len > opcodes_3d[opcode].max_len)
if (len < opcode_3d->min_len ||
len > opcode_3d->max_len)
{
fprintf(out, "Bad count in %s\n", opcodes_3d[opcode].name);
fprintf(out, "Bad count in %s\n", opcode_3d->name);
}
}
for (i = 1; i < len; i++) {
if (i >= count)
BUFFER_FAIL(count, len, opcodes_3d[opcode].name);
BUFFER_FAIL(count, len, opcode_3d->name);
instr_out(data, hw_offset, i, "dword %d\n", i);
}
return len;
}
}
instr_out(data, hw_offset, 0, "3D UNKNOWN\n");
instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_965 opcode = 0x%x\n", opcode);
(*failures)++;
return 1;
}
static int
decode_3d_i830(const uint32_t *data, int count, uint32_t hw_offset, int *failures)
decode_3d_i830(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures)
{
unsigned int opcode;
unsigned int idx;
uint32_t opcode;
struct {
uint32_t opcode;
@ -1689,41 +1957,44 @@ decode_3d_i830(const uint32_t *data, int count, uint32_t hw_offset, int *failure
{ 0x0f, 1, 1, "3DSTATE_MODES_2" },
{ 0x15, 1, 1, "3DSTATE_FOG_COLOR" },
{ 0x16, 1, 1, "3DSTATE_MODES_4" },
};
}, *opcode_3d;
switch ((data[0] & 0x1f000000) >> 24) {
opcode = (data[0] & 0x1f000000) >> 24;
switch (opcode) {
case 0x1f:
return decode_3d_primitive(data, count, hw_offset, failures);
case 0x1d:
return decode_3d_1d(data, count, hw_offset, failures, 1);
return decode_3d_1d(data, count, hw_offset, devid, failures);
case 0x1c:
return decode_3d_1c(data, count, hw_offset, failures);
}
for (opcode = 0; opcode < Elements(opcodes_3d); opcode++) {
if ((data[0] & 0x1f000000) >> 24 == opcodes_3d[opcode].opcode) {
for (idx = 0; idx < Elements(opcodes_3d); idx++) {
opcode_3d = &opcodes_3d[idx];
if ((data[0] & 0x1f000000) >> 24 == opcode_3d->opcode) {
unsigned int len = 1, i;
instr_out(data, hw_offset, 0, "%s\n", opcodes_3d[opcode].name);
if (opcodes_3d[opcode].max_len > 1) {
instr_out(data, hw_offset, 0, "%s\n", opcode_3d->name);
if (opcode_3d->max_len > 1) {
len = (data[0] & 0xff) + 2;
if (len < opcodes_3d[opcode].min_len ||
len > opcodes_3d[opcode].max_len)
if (len < opcode_3d->min_len ||
len > opcode_3d->max_len)
{
fprintf(out, "Bad count in %s\n", opcodes_3d[opcode].name);
fprintf(out, "Bad count in %s\n", opcode_3d->name);
}
}
for (i = 1; i < len; i++) {
if (i >= count)
BUFFER_FAIL(count, len, opcodes_3d[opcode].name);
BUFFER_FAIL(count, len, opcode_3d->name);
instr_out(data, hw_offset, i, "dword %d\n", i);
}
return len;
}
}
instr_out(data, hw_offset, 0, "3D UNKNOWN\n");
instr_out(data, hw_offset, 0, "3D UNKNOWN: 3d_i830 opcode = 0x%x\n", opcode);
(*failures)++;
return 1;
}
@ -1736,8 +2007,12 @@ decode_3d_i830(const uint32_t *data, int count, uint32_t hw_offset, int *failure
* \param hw_offset hardware address for the buffer
*/
int
intel_decode(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid)
intel_decode(const uint32_t *data, int count,
uint32_t hw_offset,
uint32_t devid,
uint32_t ignore_end_of_batchbuffer)
{
int ret;
int index = 0;
int failures = 0;
@ -1746,8 +2021,23 @@ intel_decode(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid
while (index < count) {
switch ((data[index] & 0xe0000000) >> 29) {
case 0x0:
index += decode_mi(data + index, count - index,
ret = decode_mi(data + index, count - index,
hw_offset + index * 4, &failures);
/* If MI_BATCHBUFFER_END happened, then dump the rest of the
* output in case we some day want it in debugging, but don't
* decode it since it'll just confuse in the common case.
*/
if (ret == -1) {
if (ignore_end_of_batchbuffer) {
index++;
} else {
for (index = index + 1; index < count; index++) {
instr_out(data, hw_offset, index, "\n");
}
}
} else
index += ret;
break;
case 0x2:
index += decode_2d(data + index, count - index,
@ -1756,13 +2046,16 @@ intel_decode(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid
case 0x3:
if (IS_965(devid)) {
index += decode_3d_965(data + index, count - index,
hw_offset + index * 4, &failures);
hw_offset + index * 4,
devid, &failures);
} else if (IS_9XX(devid)) {
index += decode_3d(data + index, count - index,
hw_offset + index * 4, &failures);
hw_offset + index * 4,
devid, &failures);
} else {
index += decode_3d_i830(data + index, count - index,
hw_offset + index * 4, &failures);
hw_offset + index * 4,
devid, &failures);
}
break;
default:

2
src/gallium/drivers/i965/intel_decode.h
View file

@ -27,5 +27,5 @@
#include "pipe/p_compiler.h"
int intel_decode(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid);
int intel_decode(const uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, uint32_t ignore_end_of_batchbuffer);
void intel_decode_context_reset(void);

79
src/gallium/drivers/noop/noop_pipe.c
View file

@ -30,10 +30,16 @@
#include <util/u_inlines.h>
#include <util/u_format.h>
#include "noop_public.h"
#include "state_tracker/sw_winsys.h"
DEBUG_GET_ONCE_BOOL_OPTION(noop, "GALLIUM_NOOP", FALSE)
void noop_init_state_functions(struct pipe_context *ctx);
struct noop_pipe_screen {
struct pipe_screen pscreen;
struct pipe_screen *oscreen;
};
/*
* query
*/
@ -108,52 +114,29 @@ static struct pipe_resource *noop_resource_create(struct pipe_screen *screen,
FREE(nresource);
return NULL;
}
#if 0
if (nresource->base.bind & (PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
PIPE_BIND_SHARED)) {
struct sw_winsys *winsys = (struct sw_winsys *)screen->winsys;
unsigned stride;
nresource->dt = winsys->displaytarget_create(winsys, nresource->base.bind,
nresource->base.format,
nresource->base.width0,
nresource->base.height0,
16, &stride);
}
#endif
return &nresource->base;
}
static struct pipe_resource *noop_resource_from_handle(struct pipe_screen * screen,
static struct pipe_resource *noop_resource_from_handle(struct pipe_screen *screen,
const struct pipe_resource *templ,
struct winsys_handle *whandle)
struct winsys_handle *handle)
{
struct sw_winsys *winsys = (struct sw_winsys *)screen->winsys;
struct noop_resource *nresource;
struct sw_displaytarget *dt;
unsigned stride;
struct noop_pipe_screen *noop_screen = (struct noop_pipe_screen*)screen;
struct pipe_screen *oscreen = noop_screen->oscreen;
struct pipe_resource *result;
struct noop_resource *noop_resource;
dt = winsys->displaytarget_from_handle(winsys, templ, whandle, &stride);
if (dt == NULL) {
return NULL;
}
nresource = (struct noop_resource *)noop_resource_create(screen, templ);
nresource->dt = dt;
return &nresource->base;
result = oscreen->resource_from_handle(oscreen, templ, handle);
noop_resource = noop_resource_create(screen, result);
pipe_resource_reference(&result, NULL);
return noop_resource;
}
static boolean noop_resource_get_handle(struct pipe_screen *screen,
struct pipe_resource *resource,
struct winsys_handle *handle)
{
struct sw_winsys *winsys = (struct sw_winsys *)screen->winsys;
struct noop_resource *nresource = (struct noop_resource *)resource;
if (nresource->dt == NULL)
return FALSE;
return winsys->displaytarget_get_handle(winsys, nresource->dt, handle);
return FALSE;
}
static void noop_resource_destroy(struct pipe_screen *screen,
@ -161,11 +144,6 @@ static void noop_resource_destroy(struct pipe_screen *screen,
{
struct noop_resource *nresource = (struct noop_resource *)resource;
if (nresource->dt) {
/* display target */
struct sw_winsys *winsys = (struct sw_winsys *)screen->winsys;
winsys->displaytarget_destroy(winsys, nresource->dt);
}
free(nresource->data);
FREE(resource);
}
@ -483,19 +461,30 @@ static boolean noop_is_format_supported(struct pipe_screen* screen,
static void noop_destroy_screen(struct pipe_screen *screen)
{
struct noop_pipe_screen *noop_screen = (struct noop_pipe_screen*)screen;
struct pipe_screen *oscreen = noop_screen->oscreen;
oscreen->destroy(oscreen);
FREE(screen);
}
struct pipe_screen *noop_screen_create(struct sw_winsys *winsys)
struct pipe_screen *noop_screen_create(struct pipe_screen *oscreen)
{
struct noop_pipe_screen *noop_screen;
struct pipe_screen *screen;
screen = CALLOC_STRUCT(pipe_screen);
if (screen == NULL) {
return NULL;
if (!debug_get_option_noop()) {
return oscreen;
}
screen->winsys = (struct pipe_winsys*)winsys;
noop_screen = CALLOC_STRUCT(noop_pipe_screen);
if (noop_screen == NULL) {
return NULL;
}
noop_screen->oscreen = oscreen;
screen = &noop_screen->pscreen;
screen->winsys = oscreen->winsys;
screen->destroy = noop_destroy_screen;
screen->get_name = noop_get_name;
screen->get_vendor = noop_get_vendor;

5
src/gallium/drivers/noop/noop_public.h
View file

@ -23,8 +23,7 @@
#ifndef NOOP_PUBLIC_H
#define NOOP_PUBLIC_H
struct sw_winsys;
struct pipe_screen *noop_screen_create(struct sw_winsys *winsys);
struct pipe_screen;
struct pipe_screen *noop_screen_create(struct pipe_screen *screen);
#endif

9
src/gallium/drivers/nv50/nv50_state.c
View file

@ -721,17 +721,16 @@ nv50_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
struct nv50_context *nv50 = nv50_context(pipe);
if (shader == PIPE_SHADER_VERTEX) {
nv50->constbuf[PIPE_SHADER_VERTEX] = buf;
nv50->dirty |= NV50_NEW_VERTPROG_CB;
} else
if (shader == PIPE_SHADER_FRAGMENT) {
nv50->constbuf[PIPE_SHADER_FRAGMENT] = buf;
nv50->dirty |= NV50_NEW_FRAGPROG_CB;
} else
if (shader == PIPE_SHADER_GEOMETRY) {
nv50->constbuf[PIPE_SHADER_GEOMETRY] = buf;
} else {
assert(shader == PIPE_SHADER_GEOMETRY);
nv50->dirty |= NV50_NEW_GEOMPROG_CB;
}
pipe_resource_reference(&nv50->constbuf[shader], buf);
}
static void

3
src/gallium/drivers/nvc0/Makefile
View file

@ -28,6 +28,7 @@ C_SOURCES = \
nvc0_push.c \
nvc0_push2.c \
nvc0_fence.c \
nvc0_mm.c
nvc0_mm.c \
nvc0_query.c
include ../../Makefile.template

3
src/gallium/drivers/nvc0/SConscript
View file

@ -29,7 +29,8 @@ nvc0 = env.ConvenienceLibrary(
'nvc0_push.c',
'nvc0_push2.c',
'nvc0_fence.c',
'nvc0_mm.c'
'nvc0_mm.c',
'nvc0_query.c'
])
Export('nvc0')

93
src/gallium/drivers/nvc0/nvc0_3d.xml.h
View file

@ -8,15 +8,15 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
- nvc0_3d.xml ( 28058 bytes, from 2010-11-26 18:05:20)
- nvc0_3d.xml ( 30401 bytes, from 2011-01-08 18:09:11)
- copyright.xml ( 6452 bytes, from 2010-11-25 23:28:20)
- nv_defs.xml ( 4437 bytes, from 2010-07-06 07:43:58)
- nv_3ddefs.xml ( 16394 bytes, from 2010-10-09 08:27:14)
- nv_object.xml ( 11547 bytes, from 2010-11-26 16:41:56)
- nv_3ddefs.xml ( 16394 bytes, from 2010-12-17 15:10:40)
- nv_object.xml ( 11898 bytes, from 2010-12-23 14:14:20)
- nvchipsets.xml ( 3074 bytes, from 2010-11-07 00:36:28)
- nv50_defs.xml ( 4482 bytes, from 2010-10-03 13:18:37)
- nv50_defs.xml ( 4487 bytes, from 2010-12-10 00:37:17)
Copyright (C) 2006-2010 by the following authors:
Copyright (C) 2006-2011 by the following authors:
- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
- Ben Skeggs (darktama, darktama_)
- B. R. <koala_br@users.sourceforge.net> (koala_br)
@ -248,6 +248,24 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_CLIPID_REGION_VERT_H__MASK 0xffff0000
#define NVC0_3D_CLIPID_REGION_VERT_H__SHIFT 16
#define NVC0_3D_COUNTER_ENABLE 0x00000d68
#define NVC0_3D_COUNTER_ENABLE_UNK00 0x00000001
#define NVC0_3D_COUNTER_ENABLE_UNK01 0x00000002
#define NVC0_3D_COUNTER_ENABLE_UNK02 0x00000004
#define NVC0_3D_COUNTER_ENABLE_UNK03 0x00000008
#define NVC0_3D_COUNTER_ENABLE_UNK04 0x00000010
#define NVC0_3D_COUNTER_ENABLE_EMITTED_PRIMITIVES 0x00000020
#define NVC0_3D_COUNTER_ENABLE_UNK06 0x00000040
#define NVC0_3D_COUNTER_ENABLE_UNK07 0x00000080
#define NVC0_3D_COUNTER_ENABLE_UNK08 0x00000100
#define NVC0_3D_COUNTER_ENABLE_UNK09 0x00000200
#define NVC0_3D_COUNTER_ENABLE_GENERATED_PRIMITIVES 0x00000400
#define NVC0_3D_COUNTER_ENABLE_UNK0B 0x00000800
#define NVC0_3D_COUNTER_ENABLE_UNK0C 0x00001000
#define NVC0_3D_COUNTER_ENABLE_UNK0D 0x00002000
#define NVC0_3D_COUNTER_ENABLE_UNK0E 0x00004000
#define NVC0_3D_COUNTER_ENABLE_UNK0F 0x00008000
#define NVC0_3D_VERTEX_BUFFER_FIRST 0x00000d74
#define NVC0_3D_VERTEX_BUFFER_COUNT 0x00000d78
@ -498,14 +516,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_BLEND_COLOR__LEN 0x00000004
#define NVC0_3D_TSC_FLUSH 0x00001330
#define NVC0_3D_TSC_FLUSH_UNK0 0x00000001
#define NVC0_3D_TSC_FLUSH_UNK1__MASK 0x03fffff0
#define NVC0_3D_TSC_FLUSH_UNK1__SHIFT 4
#define NVC0_3D_TSC_FLUSH_SPECIFIC 0x00000001
#define NVC0_3D_TSC_FLUSH_ENTRY__MASK 0x03fffff0
#define NVC0_3D_TSC_FLUSH_ENTRY__SHIFT 4
#define NVC0_3D_TIC_FLUSH 0x00001334
#define NVC0_3D_TIC_FLUSH_UNK0 0x00000001
#define NVC0_3D_TIC_FLUSH_UNK1__MASK 0x03fffff0
#define NVC0_3D_TIC_FLUSH_UNK1__SHIFT 4
#define NVC0_3D_TIC_FLUSH_SPECIFIC 0x00000001
#define NVC0_3D_TIC_FLUSH_ENTRY__MASK 0x03fffff0
#define NVC0_3D_TIC_FLUSH_ENTRY__SHIFT 4
#define NVC0_3D_TEX_CACHE_CTL 0x00001338
#define NVC0_3D_TEX_CACHE_CTL_UNK1__MASK 0x00000030
@ -630,7 +648,25 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_POINT_SPRITE_ENABLE 0x00001520
#define NVC0_3D_SAMPLECNT_RESET 0x00001530
#define NVC0_3D_COUNTER_RESET 0x00001530
#define NVC0_3D_COUNTER_RESET_SAMPLECNT 0x00000001
#define NVC0_3D_COUNTER_RESET_UNK02 0x00000002
#define NVC0_3D_COUNTER_RESET_UNK03 0x00000003
#define NVC0_3D_COUNTER_RESET_UNK04 0x00000004
#define NVC0_3D_COUNTER_RESET_EMITTED_PRIMITIVES 0x00000010
#define NVC0_3D_COUNTER_RESET_UNK11 0x00000011
#define NVC0_3D_COUNTER_RESET_UNK12 0x00000012
#define NVC0_3D_COUNTER_RESET_UNK13 0x00000013
#define NVC0_3D_COUNTER_RESET_UNK15 0x00000015
#define NVC0_3D_COUNTER_RESET_UNK16 0x00000016
#define NVC0_3D_COUNTER_RESET_UNK17 0x00000017
#define NVC0_3D_COUNTER_RESET_UNK18 0x00000018
#define NVC0_3D_COUNTER_RESET_UNK1A 0x0000001a
#define NVC0_3D_COUNTER_RESET_UNK1B 0x0000001b
#define NVC0_3D_COUNTER_RESET_UNK1C 0x0000001c
#define NVC0_3D_COUNTER_RESET_UNK1D 0x0000001d
#define NVC0_3D_COUNTER_RESET_UNK1E 0x0000001e
#define NVC0_3D_COUNTER_RESET_GENERATED_PRIMITIVES 0x0000001f
#define NVC0_3D_MULTISAMPLE_ZETA_ENABLE 0x00001534
@ -960,11 +996,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_QUERY_SEQUENCE 0x00001b08
#define NVC0_3D_QUERY_GET 0x00001b0c
#define NVC0_3D_QUERY_GET_FENCE 0x1000f010
#define NVC0_3D_QUERY_GET_SAMPLE_COUNT 0x0100f002
#define NVC0_3D_QUERY_GET_TFB 0x05805002
#define NVC0_3D_QUERY_GET_GENERATED_PRIMS 0x06805002
#define NVC0_3D_QUERY_GET_UNK00005002 0x00005002
#define NVC0_3D_QUERY_GET_MODE__MASK 0x00000003
#define NVC0_3D_QUERY_GET_MODE__SHIFT 0
#define NVC0_3D_QUERY_GET_MODE_WRITE_UNK0 0x00000000
#define NVC0_3D_QUERY_GET_MODE_SYNC 0x00000001
#define NVC0_3D_QUERY_GET_MODE_WRITE_UNK2 0x00000002
#define NVC0_3D_QUERY_GET_FENCE 0x00000010
#define NVC0_3D_QUERY_GET_STREAM__MASK 0x000000e0
#define NVC0_3D_QUERY_GET_STREAM__SHIFT 5
#define NVC0_3D_QUERY_GET_UNK8 0x00000100
#define NVC0_3D_QUERY_GET_UNIT__MASK 0x0000f000
#define NVC0_3D_QUERY_GET_UNIT__SHIFT 12
#define NVC0_3D_QUERY_GET_SYNC_COND__MASK 0x00010000
#define NVC0_3D_QUERY_GET_SYNC_COND__SHIFT 16
#define NVC0_3D_QUERY_GET_SYNC_COND_NEQUAL 0x00000000
#define NVC0_3D_QUERY_GET_SYNC_COND_GREATER 0x00010000
#define NVC0_3D_QUERY_GET_INTR 0x00100000
#define NVC0_3D_QUERY_GET_UNK21 0x00200000
#define NVC0_3D_QUERY_GET_SELECT__MASK 0x0f800000
#define NVC0_3D_QUERY_GET_SELECT__SHIFT 23
#define NVC0_3D_QUERY_GET_SELECT_ZERO 0x00000000
#define NVC0_3D_QUERY_GET_SELECT_SAMPLECNT 0x01000000
#define NVC0_3D_QUERY_GET_SELECT_EMITTED_PRIMS 0x05800000
#define NVC0_3D_QUERY_GET_SELECT_GENERATED_PRIMS 0x09000000
#define NVC0_3D_QUERY_GET_SHORT 0x10000000
#define NVC0_3D_VERTEX_ARRAY_FETCH(i0) (0x00001c00 + 0x10*(i0))
#define NVC0_3D_VERTEX_ARRAY_FETCH__ESIZE 0x00000010
@ -1026,6 +1081,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_TEX_LIMITS__ESIZE 0x00000010
#define NVC0_3D_TEX_LIMITS__LEN 0x00000005
#define NVC0_3D_FIRMWARE(i0) (0x00002300 + 0x4*(i0))
#define NVC0_3D_FIRMWARE__ESIZE 0x00000004
#define NVC0_3D_FIRMWARE__LEN 0x00000020
#define NVC0_3D_CB_SIZE 0x00002380
#define NVC0_3D_CB_ADDRESS_HIGH 0x00002384

3
src/gallium/drivers/nvc0/nvc0_buffer.c
View file

@ -52,8 +52,7 @@ static INLINE void
release_allocation(struct nvc0_mm_allocation **mm, struct nvc0_fence *fence)
{
if (fence && fence->state != NVC0_FENCE_STATE_SIGNALLED) {
(*mm)->next = fence->buffers;
fence->buffers = (*mm);
nvc0_fence_sched_release(fence, *mm);
} else {
nvc0_mm_free(*mm);
}

1
src/gallium/drivers/nvc0/nvc0_context.c
View file

@ -92,6 +92,7 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
screen->base.channel->user_private = nvc0;
nvc0_init_query_functions(nvc0);
nvc0_init_surface_functions(nvc0);
nvc0_init_state_functions(nvc0);
nvc0_init_resource_functions(&nvc0->pipe);

3
src/gallium/drivers/nvc0/nvc0_context.h
View file

@ -166,6 +166,9 @@ extern struct draw_stage *nvc0_draw_render_stage(struct nvc0_context *);
boolean nvc0_program_translate(struct nvc0_program *);
void nvc0_program_destroy(struct nvc0_context *, struct nvc0_program *);
/* nvc0_query.c */
void nvc0_init_query_functions(struct nvc0_context *);
/* nvc0_shader_state.c */
void nvc0_vertprog_validate(struct nvc0_context *);
void nvc0_tctlprog_validate(struct nvc0_context *);

3
src/gallium/drivers/nvc0/nvc0_fence.c
View file

@ -59,7 +59,8 @@ nvc0_fence_emit(struct nvc0_fence *fence)
OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
OUT_RING (chan, fence->sequence);
OUT_RING (chan, NVC0_3D_QUERY_GET_FENCE);
OUT_RING (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
(0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
++fence->ref;

24
src/gallium/drivers/nvc0/nvc0_push.c
View file

@ -75,13 +75,15 @@ emit_vertices_i08(struct push_context *ctx, unsigned start, unsigned count)
BEGIN_RING_NI(ctx->chan, RING_3D(VERTEX_DATA), size);
ctx->translate->run_elts8(ctx->translate, elts, push, 0, ctx->chan->cur);
ctx->translate->run_elts8(ctx->translate, elts, nr, 0, ctx->chan->cur);
ctx->chan->cur += size;
count -= push;
elts += push;
count -= nr;
elts += nr;
if (nr != push) {
count--;
elts++;
BEGIN_RING(ctx->chan, RING_3D(VERTEX_END_GL), 2);
OUT_RING (ctx->chan, 0);
OUT_RING (ctx->chan, ctx->prim);
@ -106,13 +108,15 @@ emit_vertices_i16(struct push_context *ctx, unsigned start, unsigned count)
BEGIN_RING_NI(ctx->chan, RING_3D(VERTEX_DATA), size);
ctx->translate->run_elts16(ctx->translate, elts, push, 0, ctx->chan->cur);
ctx->translate->run_elts16(ctx->translate, elts, nr, 0, ctx->chan->cur);
ctx->chan->cur += size;
count -= push;
elts += push;
count -= nr;
elts += nr;
if (nr != push) {
count--;
elts++;
BEGIN_RING(ctx->chan, RING_3D(VERTEX_END_GL), 2);
OUT_RING (ctx->chan, 0);
OUT_RING (ctx->chan, ctx->prim);
@ -137,13 +141,15 @@ emit_vertices_i32(struct push_context *ctx, unsigned start, unsigned count)
BEGIN_RING_NI(ctx->chan, RING_3D(VERTEX_DATA), size);
ctx->translate->run_elts(ctx->translate, elts, push, 0, ctx->chan->cur);
ctx->translate->run_elts(ctx->translate, elts, nr, 0, ctx->chan->cur);
ctx->chan->cur += size;
count -= push;
elts += push;
count -= nr;
elts += nr;
if (nr != push) {
count--;
elts++;
BEGIN_RING(ctx->chan, RING_3D(VERTEX_END_GL), 2);
OUT_RING (ctx->chan, 0);
OUT_RING (ctx->chan, ctx->prim);

337
src/gallium/drivers/nvc0/nvc0_query.c Normal file
View file

@ -0,0 +1,337 @@
/*
* Copyright 2011 Nouveau Project
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors: Christoph Bumiller
*/
#include "nvc0_context.h"
#include "nouveau/nv_object.xml.h"
/* XXX: Nested queries, and simultaneous queries on multiple gallium contexts
* (since we use only a single GPU channel per screen) will not work properly.
*
* The first is not that big of an issue because OpenGL does not allow nested
* queries anyway.
*/
struct nvc0_query {
uint32_t *data;
uint32_t type;
uint32_t sequence;
struct nouveau_bo *bo;
uint32_t base;
uint32_t offset; /* base + i * 16 */
boolean ready;
boolean is64bit;
struct nvc0_mm_allocation *mm;
};
#define NVC0_QUERY_ALLOC_SPACE 128
static INLINE struct nvc0_query *
nvc0_query(struct pipe_query *pipe)
{
return (struct nvc0_query *)pipe;
}
static boolean
nvc0_query_allocate(struct nvc0_context *nvc0, struct nvc0_query *q, int size)
{
struct nvc0_screen *screen = nvc0->screen;
int ret;
if (q->bo) {
nouveau_bo_ref(NULL, &q->bo);
if (q->mm) {
if (q->ready)
nvc0_mm_free(q->mm);
else
nvc0_fence_sched_release(screen->fence.current, q->mm);
}
}
if (size) {
q->mm = nvc0_mm_allocate(screen->mm_GART, size, &q->bo, &q->base);
if (!q->bo)
return FALSE;
q->offset = q->base;
ret = nouveau_bo_map_range(q->bo, q->base, size, NOUVEAU_BO_RD |
NOUVEAU_BO_NOSYNC);
if (ret) {
nvc0_query_allocate(nvc0, q, 0);
return FALSE;
}
q->data = q->bo->map;
nouveau_bo_unmap(q->bo);
}
return TRUE;
}
static void
nvc0_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
{
nvc0_query_allocate(nvc0_context(pipe), nvc0_query(pq), 0);
FREE(nvc0_query(pq));
}
static struct pipe_query *
nvc0_query_create(struct pipe_context *pipe, unsigned type)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
struct nvc0_query *q;
q = CALLOC_STRUCT(nvc0_query);
if (!q)
return NULL;
if (!nvc0_query_allocate(nvc0, q, NVC0_QUERY_ALLOC_SPACE)) {
FREE(q);
return NULL;
}
q->is64bit = (type == PIPE_QUERY_PRIMITIVES_GENERATED ||
type == PIPE_QUERY_PRIMITIVES_EMITTED ||
type == PIPE_QUERY_SO_STATISTICS);
q->type = type;
if (q->type == PIPE_QUERY_OCCLUSION_COUNTER) {
q->offset -= 16;
q->data -= 16 / sizeof(*q->data); /* we advance before query_begin ! */
}
return (struct pipe_query *)q;
}
static void
nvc0_query_get(struct nouveau_channel *chan, struct nvc0_query *q,
unsigned offset, uint32_t get)
{
offset += q->offset;
MARK_RING (chan, 5, 2);
BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
OUT_RELOCh(chan, q->bo, offset, NOUVEAU_BO_GART | NOUVEAU_BO_WR);
OUT_RELOCl(chan, q->bo, offset, NOUVEAU_BO_GART | NOUVEAU_BO_WR);
OUT_RING (chan, q->sequence);
OUT_RING (chan, get);
}
static void
nvc0_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
struct nouveau_channel *chan = nvc0->screen->base.channel;
struct nvc0_query *q = nvc0_query(pq);
/* For occlusion queries we have to change the storage, because a previous
* query might set the initial render conition to FALSE even *after* we re-
* initialized it to TRUE.
*/
if (q->type == PIPE_QUERY_OCCLUSION_COUNTER) {
q->offset += 16;
q->data += 16 / sizeof(*q->data);
if (q->offset - q->base == NVC0_QUERY_ALLOC_SPACE)
nvc0_query_allocate(nvc0, q, NVC0_QUERY_ALLOC_SPACE);
/* XXX: can we do this with the GPU, and sync with respect to a previous
* query ?
*/
q->data[1] = 1; /* initial render condition = TRUE */
}
if (!q->is64bit)
q->data[0] = q->sequence++; /* the previously used one */
switch (q->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
IMMED_RING(chan, RING_3D(COUNTER_RESET), NVC0_3D_COUNTER_RESET_SAMPLECNT);
IMMED_RING(chan, RING_3D(SAMPLECNT_ENABLE), 1);
break;
case PIPE_QUERY_PRIMITIVES_GENERATED: /* store before & after instead ? */
IMMED_RING(chan, RING_3D(COUNTER_RESET),
NVC0_3D_COUNTER_RESET_GENERATED_PRIMITIVES);
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
IMMED_RING(chan, RING_3D(COUNTER_RESET),
NVC0_3D_COUNTER_RESET_EMITTED_PRIMITIVES);
break;
case PIPE_QUERY_SO_STATISTICS:
BEGIN_RING_NI(chan, RING_3D(COUNTER_RESET), 2);
OUT_RING (chan, NVC0_3D_COUNTER_RESET_EMITTED_PRIMITIVES);
OUT_RING (chan, NVC0_3D_COUNTER_RESET_GENERATED_PRIMITIVES);
break;
case PIPE_QUERY_TIMESTAMP_DISJOINT:
case PIPE_QUERY_TIME_ELAPSED:
nvc0_query_get(chan, q, 0x10, 0x00005002);
break;
default:
break;
}
q->ready = FALSE;
}
static void
nvc0_query_end(struct pipe_context *pipe, struct pipe_query *pq)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
struct nouveau_channel *chan = nvc0->screen->base.channel;
struct nvc0_query *q = nvc0_query(pq);
const int index = 0; /* for multiple vertex streams */
switch (q->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
nvc0_query_get(chan, q, 0, 0x0100f002);
BEGIN_RING(chan, RING_3D(SAMPLECNT_ENABLE), 1);
OUT_RING (chan, 0);
break;
case PIPE_QUERY_PRIMITIVES_GENERATED:
nvc0_query_get(chan, q, 0, 0x09005002 | (index << 5));
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
nvc0_query_get(chan, q, 0, 0x05805002 | (index << 5));
break;
case PIPE_QUERY_SO_STATISTICS:
nvc0_query_get(chan, q, 0x00, 0x05805002 | (index << 5));
nvc0_query_get(chan, q, 0x10, 0x09005002 | (index << 5));
break;
case PIPE_QUERY_TIMESTAMP_DISJOINT:
case PIPE_QUERY_TIME_ELAPSED:
nvc0_query_get(chan, q, 0, 0x00005002);
break;
case PIPE_QUERY_GPU_FINISHED:
nvc0_query_get(chan, q, 0, 0x1000f010);
break;
default:
assert(0);
break;
}
}
static INLINE boolean
nvc0_query_ready(struct nvc0_query *q)
{
return q->ready || (!q->is64bit && (q->data[0] == q->sequence));
}
static INLINE boolean
nvc0_query_wait(struct nvc0_query *q)
{
int ret = nouveau_bo_map(q->bo, NOUVEAU_BO_RD);
if (ret)
return FALSE;
nouveau_bo_unmap(q->bo);
return TRUE;
}
static boolean
nvc0_query_result(struct pipe_context *pipe, struct pipe_query *pq,
boolean wait, void *result)
{
struct nvc0_query *q = nvc0_query(pq);
uint64_t *res64 = result;
uint32_t *res32 = result;
boolean *res8 = result;
uint64_t *data64 = (uint64_t *)q->data;
if (q->type == PIPE_QUERY_GPU_FINISHED) {
res8[0] = nvc0_query_ready(q);
return TRUE;
}
if (!q->ready) /* update ? */
q->ready = nvc0_query_ready(q);
if (!q->ready) {
struct nouveau_channel *chan = nvc0_context(pipe)->screen->base.channel;
if (!wait) {
if (nouveau_bo_pending(q->bo) & NOUVEAU_BO_WR) /* for daft apps */
FIRE_RING(chan);
return FALSE;
}
if (!nvc0_query_wait(q))
return FALSE;
}
q->ready = TRUE;
switch (q->type) {
case PIPE_QUERY_OCCLUSION_COUNTER: /* u32 sequence, u32 count, u64 time */
res32[0] = q->data[1];
break;
case PIPE_QUERY_PRIMITIVES_GENERATED: /* u64 count, u64 time */
case PIPE_QUERY_PRIMITIVES_EMITTED: /* u64 count, u64 time */
res64[0] = data64[0];
break;
case PIPE_QUERY_SO_STATISTICS:
res64[0] = data64[0];
res64[1] = data64[1];
break;
case PIPE_QUERY_TIMESTAMP_DISJOINT: /* u32 sequence, u32 0, u64 time */
res64[0] = 1000000000;
res8[8] = (data64[0] == data64[2]) ? FALSE : TRUE;
break;
case PIPE_QUERY_TIME_ELAPSED:
res64[0] = data64[1] - data64[3];
break;
default:
return FALSE;
}
return TRUE;
}
static void
nvc0_render_condition(struct pipe_context *pipe,
struct pipe_query *pq, uint mode)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
struct nouveau_channel *chan = nvc0->screen->base.channel;
struct nvc0_query *q;
if (!pq) {
IMMED_RING(chan, RING_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
return;
}
q = nvc0_query(pq);
if (mode == PIPE_RENDER_COND_WAIT ||
mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
BEGIN_RING(chan, RING_3D_(NV84_SUBCHAN_QUERY_ADDRESS_HIGH), 4);
OUT_RELOCh(chan, q->bo, q->offset, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RELOCl(chan, q->bo, q->offset, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RING (chan, q->sequence);
OUT_RING (chan, 0x00001001);
}
BEGIN_RING(chan, RING_3D(COND_ADDRESS_HIGH), 3);
OUT_RELOCh(chan, q->bo, q->offset, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RELOCl(chan, q->bo, q->offset, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
OUT_RING (chan, NVC0_3D_COND_MODE_RES_NON_ZERO);
}
void
nvc0_init_query_functions(struct nvc0_context *nvc0)
{
nvc0->pipe.create_query = nvc0_query_create;
nvc0->pipe.destroy_query = nvc0_query_destroy;
nvc0->pipe.begin_query = nvc0_query_begin;
nvc0->pipe.end_query = nvc0_query_end;
nvc0->pipe.get_query_result = nvc0_query_result;
nvc0->pipe.render_condition = nvc0_render_condition;
}

2
src/gallium/drivers/nvc0/nvc0_screen.c
View file

@ -92,9 +92,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 1;
case PIPE_CAP_MAX_RENDER_TARGETS:
return 8;
case PIPE_CAP_TIMER_QUERY:
case PIPE_CAP_OCCLUSION_QUERY:
return 1;
case PIPE_CAP_TIMER_QUERY:
case PIPE_CAP_STREAM_OUTPUT:
return 0;
case PIPE_CAP_BLEND_EQUATION_SEPARATE:

7
src/gallium/drivers/nvc0/nvc0_screen.h
View file

@ -86,6 +86,13 @@ struct nvc0_mm_allocation {
uint32_t offset;
};
static INLINE void
nvc0_fence_sched_release(struct nvc0_fence *nf, struct nvc0_mm_allocation *mm)
{
mm->next = nf->buffers;
nf->buffers = mm;
}
extern struct nvc0_mman *
nvc0_mm_create(struct nouveau_device *, uint32_t domain, uint32_t storage_type);

3
src/gallium/drivers/nvc0/nvc0_vbo.c
View file

@ -584,6 +584,9 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
if (info->primitive_restart) {
BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
OUT_RING (chan, info->restart_index);
if (info->restart_index > 65535)
shorten = FALSE;
}
nvc0_draw_elements(nvc0, shorten,

2
src/gallium/drivers/nvfx/nvfx_state.c
View file

@ -304,7 +304,7 @@ nvfx_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
{
struct nvfx_context *nvfx = nvfx_context(pipe);
nvfx->constbuf[shader] = buf;
pipe_resource_reference(&nvfx->constbuf[shader], buf);
nvfx->constbuf_nr[shader] = buf ? (buf->width0 / (4 * sizeof(float))) : 0;
if (shader == PIPE_SHADER_VERTEX) {

62
src/gallium/drivers/r300/r300_blit.c
View file

@ -179,6 +179,12 @@ static void r300_clear(struct pipe_context* pipe,
boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
uint32_t hyperz_dcv = hyperz->zb_depthclearvalue;
/* Decompress zbuffers that are bound as textures. If we didn't flush here,
* it would happen inside the blitter when updating derived state,
* causing a blitter operation to be called from inside the blitter,
* which would overwrite saved states and they would never get restored. */
r300_flush_depth_textures(r300);
/* Enable fast Z clear.
* The zbuffer must be in micro-tiled mode, otherwise it locks up. */
if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && can_hyperz) {
@ -274,6 +280,12 @@ static void r300_clear_render_target(struct pipe_context *pipe,
{
struct r300_context *r300 = r300_context(pipe);
/* Decompress zbuffers that are bound as textures. If we didn't flush here,
* it would happen inside the blitter when updating derived state,
* causing a blitter operation to be called from inside the blitter,
* which would overwrite saved states and they would never get restored. */
r300_flush_depth_textures(r300);
r300_blitter_begin(r300, R300_CLEAR_SURFACE);
util_blitter_clear_render_target(r300->blitter, dst, rgba,
dstx, dsty, width, height);
@ -291,6 +303,12 @@ static void r300_clear_depth_stencil(struct pipe_context *pipe,
{
struct r300_context *r300 = r300_context(pipe);
/* Decompress zbuffers that are bound as textures. If we didn't flush here,
* it would happen inside the blitter when updating derived state,
* causing a blitter operation to be called from inside the blitter,
* which would overwrite saved states and they would never get restored. */
r300_flush_depth_textures(r300);
r300_blitter_begin(r300, R300_CLEAR_SURFACE);
util_blitter_clear_depth_stencil(r300->blitter, dst, clear_flags, depth, stencil,
dstx, dsty, width, height);
@ -298,10 +316,10 @@ static void r300_clear_depth_stencil(struct pipe_context *pipe,
}
/* Flush a depth stencil buffer. */
void r300_flush_depth_stencil(struct pipe_context *pipe,
struct pipe_resource *dst,
unsigned level,
unsigned layer)
static void r300_flush_depth_stencil(struct pipe_context *pipe,
struct pipe_resource *dst,
unsigned level,
unsigned layer)
{
struct r300_context *r300 = r300_context(pipe);
struct pipe_surface *dstsurf, surf_tmpl;
@ -320,6 +338,7 @@ void r300_flush_depth_stencil(struct pipe_context *pipe,
dstsurf = pipe->create_surface(pipe, dst, &surf_tmpl);
r300->z_decomp_rd = TRUE;
r300_blitter_begin(r300, R300_CLEAR_SURFACE);
util_blitter_flush_depth_stencil(r300->blitter, dstsurf);
r300_blitter_end(r300);
@ -329,6 +348,39 @@ void r300_flush_depth_stencil(struct pipe_context *pipe,
pipe_surface_reference(&dstsurf, NULL);
}
/* We can't use compressed zbuffers as samplers. */
void r300_flush_depth_textures(struct r300_context *r300)
{
struct r300_textures_state *state =
(struct r300_textures_state*)r300->textures_state.state;
unsigned i, level;
unsigned count = MIN2(state->sampler_view_count,
state->sampler_state_count);
if (r300->z_decomp_rd)
return;
for (i = 0; i < count; i++)
if (state->sampler_views[i] && state->sampler_states[i]) {
struct pipe_resource *tex = state->sampler_views[i]->base.texture;
if (tex->target == PIPE_TEXTURE_3D ||
tex->target == PIPE_TEXTURE_CUBE)
continue;
/* Ignore non-depth textures.
* Also ignore reinterpreted depth textures, e.g. resource_copy. */
if (!util_format_is_depth_or_stencil(tex->format))
continue;
for (level = 0; level <= tex->last_level; level++)
if (r300_texture(tex)->zmask_in_use[level]) {
/* We don't handle 3D textures and cubemaps yet. */
r300_flush_depth_stencil(&r300->context, tex, level, 0);
}
}
}
/* Copy a block of pixels from one surface to another using HW. */
static void r300_hw_copy_region(struct pipe_context* pipe,
struct pipe_resource *dst,
@ -360,6 +412,7 @@ static void r300_resource_copy_region(struct pipe_context *pipe,
enum pipe_format old_format = dst->format;
enum pipe_format new_format = old_format;
boolean is_depth;
if (!pipe->screen->is_format_supported(pipe->screen,
old_format, src->target,
src->nr_samples,
@ -390,6 +443,7 @@ static void r300_resource_copy_region(struct pipe_context *pipe,
if (is_depth) {
r300_flush_depth_stencil(pipe, src, src_level, src_box->z);
}
if (old_format != new_format) {
r300_texture_reinterpret_format(pipe->screen,
dst, new_format);

38
src/gallium/drivers/r300/r300_context.h
View file

@ -656,6 +656,22 @@ static INLINE struct r300_fragment_shader *r300_fs(struct r300_context *r300)
return (struct r300_fragment_shader*)r300->fs.state;
}
static INLINE void r300_mark_atom_dirty(struct r300_context *r300,
struct r300_atom *atom)
{
atom->dirty = TRUE;
if (!r300->first_dirty) {
r300->first_dirty = atom;
r300->last_dirty = atom+1;
} else {
if (atom < r300->first_dirty)
r300->first_dirty = atom;
else if (atom+1 > r300->last_dirty)
r300->last_dirty = atom+1;
}
}
struct pipe_context* r300_create_context(struct pipe_screen* screen,
void *priv);
@ -672,10 +688,7 @@ void r300_init_state_functions(struct r300_context* r300);
void r300_init_resource_functions(struct r300_context* r300);
/* r300_blit.c */
void r300_flush_depth_stencil(struct pipe_context *pipe,
struct pipe_resource *dst,
unsigned level,
unsigned layer);
void r300_flush_depth_textures(struct r300_context *r300);
/* r300_query.c */
void r300_resume_query(struct r300_context *r300,
@ -710,21 +723,8 @@ void r300_mark_fb_state_dirty(struct r300_context *r300,
enum r300_fb_state_change change);
void r300_mark_fs_code_dirty(struct r300_context *r300);
static INLINE void r300_mark_atom_dirty(struct r300_context *r300,
struct r300_atom *atom)
{
atom->dirty = TRUE;
if (!r300->first_dirty) {
r300->first_dirty = atom;
r300->last_dirty = atom+1;
} else {
if (atom < r300->first_dirty)
r300->first_dirty = atom;
if (atom+1 > r300->last_dirty)
r300->last_dirty = atom+1;
}
}
/* r300_state_derived.c */
void r300_update_derived_state(struct r300_context* r300);
/* r300_debug.c */
void r500_dump_rs_block(struct r300_rs_block *rs);

1
src/gallium/drivers/r300/r300_debug.c
View file

@ -41,6 +41,7 @@ static const struct debug_named_value debug_options[] = {
{ "fb", DBG_FB, "Log framebuffer" },
{ "cbzb", DBG_CBZB, "Log fast color clear info" },
{ "hyperz", DBG_HYPERZ, "Log HyperZ info" },
{ "upload", DBG_UPLOAD, "Log user buffer upload info" },
{ "scissor", DBG_SCISSOR, "Log scissor info" },
{ "fakeocc", DBG_FAKE_OCC, "Use fake occlusion queries" },
{ "anisohq", DBG_ANISOHQ, "Use high quality anisotropic filtering" },

9
src/gallium/drivers/r300/r300_render.c
View file

@ -39,7 +39,6 @@
#include "r300_screen_buffer.h"
#include "r300_emit.h"
#include "r300_reg.h"
#include "r300_state_derived.h"
#include <limits.h>
@ -569,8 +568,6 @@ static void r300_draw_range_elements(struct pipe_context* pipe,
r300_translate_index_buffer(r300, &indexBuffer, &indexSize, index_offset,
&start, count);
r300_update_derived_state(r300);
/* Fallback for misaligned ushort indices. */
if (indexSize == 2 && (start & 1) &&
!r300_is_user_buffer(indexBuffer)) {
@ -643,8 +640,6 @@ static void r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0);
unsigned short_count;
r300_update_derived_state(r300);
if (immd_is_good_idea(r300, count)) {
r300_emit_draw_arrays_immediate(r300, mode, start, count);
} else {
@ -720,6 +715,8 @@ static void r300_draw_vbo(struct pipe_context* pipe,
return;
}
r300_update_derived_state(r300);
/* Set up the fallback for an incompatible vertex layout if needed. */
if (r300->incompatible_vb_layout || r300->velems->incompatible_layout) {
r300_begin_vertex_translate(r300, real_min_index, real_max_index);
@ -737,6 +734,8 @@ static void r300_draw_vbo(struct pipe_context* pipe,
min_index = MAX2(min_index, info->start);
max_index = MIN2(max_index, info->start + count - 1);
r300_update_derived_state(r300);
/* Set up the fallback for an incompatible vertex layout if needed. */
if (r300->incompatible_vb_layout || r300->velems->incompatible_layout) {
r300_begin_vertex_translate(r300, min_index, max_index);

1
src/gallium/drivers/r300/r300_screen.h
View file

@ -93,6 +93,7 @@ r300_winsys_screen(struct pipe_screen *screen) {
#define DBG_CBZB (1 << 11)
#define DBG_HYPERZ (1 << 12)
#define DBG_SCISSOR (1 << 13)
#define DBG_UPLOAD (1 << 14)
/* Features. */
#define DBG_ANISOHQ (1 << 16)
#define DBG_NO_TILING (1 << 17)

11
src/gallium/drivers/r300/r300_screen_buffer.c
View file

@ -87,13 +87,14 @@ void r300_upload_user_buffers(struct r300_context *r300,
int i, nr = r300->velems->count;
unsigned count = max_index + 1 - min_index;
boolean flushed;
boolean uploaded[16] = {0};
for (i = 0; i < nr; i++) {
unsigned index = r300->velems->velem[i].vertex_buffer_index;
struct pipe_vertex_buffer *vb = &r300->vertex_buffer[index];
struct r300_buffer *userbuf = r300_buffer(vb->buffer);
if (userbuf && userbuf->user_buffer) {
if (userbuf && userbuf->user_buffer && !uploaded[index]) {
unsigned first, size;
if (vb->stride) {
@ -104,6 +105,12 @@ void r300_upload_user_buffers(struct r300_context *r300,
size = r300->velems->hw_format_size[i];
}
DBG(r300, DBG_UPLOAD,
"Uploading %i bytes, index: %i, buffer: %p, userptr: %p "
"offset: %i, stride: %i.\n",
size, index, userbuf, userbuf->user_buffer,
vb->buffer_offset, vb->stride);
u_upload_data(r300->upload_vb, first, size,
userbuf->user_buffer + first,
&vb->buffer_offset,
@ -118,10 +125,12 @@ void r300_upload_user_buffers(struct r300_context *r300,
r300->upload_vb_validated = FALSE;
r300->validate_buffers = TRUE;
}
uploaded[index] = TRUE;
} else {
assert(r300->valid_vertex_buffer[index]);
}
}
DBG(r300, DBG_UPLOAD, "-------\n");
}
static void r300_buffer_destroy(struct pipe_screen *screen,

34
src/gallium/drivers/r300/r300_state_derived.c
View file

@ -32,7 +32,6 @@
#include "r300_hyperz.h"
#include "r300_screen.h"
#include "r300_shader_semantics.h"
#include "r300_state_derived.h"
#include "r300_state_inlines.h"
#include "r300_texture.h"
#include "r300_vs.h"
@ -863,39 +862,6 @@ static void r300_merge_textures_and_samplers(struct r300_context* r300)
}
}
/* We can't use compressed zbuffers as samplers. */
static void r300_flush_depth_textures(struct r300_context *r300)
{
struct r300_textures_state *state =
(struct r300_textures_state*)r300->textures_state.state;
unsigned i, level;
unsigned count = MIN2(state->sampler_view_count,
state->sampler_state_count);
if (r300->z_decomp_rd)
return;
for (i = 0; i < count; i++)
if (state->sampler_views[i] && state->sampler_states[i]) {
struct pipe_resource *tex = state->sampler_views[i]->base.texture;
if (tex->target == PIPE_TEXTURE_3D ||
tex->target == PIPE_TEXTURE_CUBE)
continue;
/* Ignore non-depth textures.
* Also ignore reinterpreted depth textures, e.g. resource_copy. */
if (!util_format_is_depth_or_stencil(tex->format))
continue;
for (level = 0; level <= tex->last_level; level++)
if (r300_texture(tex)->zmask_in_use[level]) {
/* We don't handle 3D textures and cubemaps yet. */
r300_flush_depth_stencil(&r300->context, tex, level, 0);
}
}
}
void r300_update_derived_state(struct r300_context* r300)
{
r300_flush_depth_textures(r300);

30
src/gallium/drivers/r300/r300_state_derived.h
View file

@ -1,30 +0,0 @@
/*
* Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef R300_STATE_DERIVED_H
#define R300_STATE_DERIVED_H
struct r300_context;
void r300_update_derived_state(struct r300_context* r300);
#endif /* R300_STATE_DERIVED_H */

3
src/gallium/drivers/r600/r600.h
View file

@ -248,10 +248,7 @@ struct r600_context {
u32 *pm4;
struct list_head query_list;
unsigned num_query_running;
unsigned fence;
struct list_head fenced_bo;
unsigned *cfence;
struct r600_bo *fence_bo;
};
struct r600_draw {

2
src/gallium/state_trackers/egl/x11/native_dri2.c
View file

@ -799,7 +799,7 @@ dri2_display_hash_table_hash(void *key)
static int
dri2_display_hash_table_compare(void *key1, void *key2)
{
return (key1 - key2);
return ((char *) key1 - (char *) key2);
}
struct native_display *

34
src/gallium/targets/dri-noop/Makefile
View file

@ -1,34 +0,0 @@
TOP = ../../../..
include $(TOP)/configs/current
LIBNAME = noop_dri.so
DRIVER_DEFINES = \
-D__NOT_HAVE_DRM_H
PIPE_DRIVERS = \
$(TOP)/src/gallium/state_trackers/dri/sw/libdrisw.a \
$(TOP)/src/gallium/winsys/sw/dri/libswdri.a \
$(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \
$(TOP)/src/gallium/drivers/trace/libtrace.a \
$(TOP)/src/gallium/drivers/rbug/librbug.a \
$(TOP)/src/gallium/drivers/noop/libnoop.a
SWRAST_COMMON_GALLIUM_SOURCES = \
$(TOP)/src/mesa/drivers/dri/common/utils.c \
$(TOP)/src/mesa/drivers/dri/common/drisw_util.c \
$(TOP)/src/mesa/drivers/dri/common/xmlconfig.c
C_SOURCES = \
swrast_drm_api.c \
$(SWRAST_COMMON_GALLIUM_SOURCES) \
$(DRIVER_SOURCES)
ASM_SOURCES =
include ../Makefile.dri
INCLUDES += \
-I$(TOP)/src/gallium/winsys/sw/dri
symlinks:

31
src/gallium/targets/dri-noop/SConscript
View file

@ -1,31 +0,0 @@
Import('*')
env = drienv.Clone()
env.Append(CPPPATH = [
'#/src/gallium/winsys/sw/dri',
])
env.Prepend(LIBS = [
st_drisw,
ws_dri,
noop,
mesa,
glsl,
gallium,
COMMON_DRI_SW_OBJECTS
])
env.Prepend(LIBS = [noop])
swrastg_sources = [
'swrast_drm_api.c'
]
module = env.LoadableModule(
target ='noop_dri.so',
source = swrastg_sources,
SHLIBPREFIX = '',
)
env.Alias('dri-noop', module)

63
src/gallium/targets/dri-noop/swrast_drm_api.c
View file

@ -1,63 +0,0 @@
/**************************************************************************
*
* Copyright 2009, VMware, Inc.
* All Rights Reserved.
* Copyright 2010 George Sapountzis <gsapountzis@gmail.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#include "pipe/p_compiler.h"
#include "util/u_memory.h"
#include "dri_sw_winsys.h"
#include "noop/noop_public.h"
#include "target-helpers/inline_debug_helper.h"
#include "target-helpers/inline_sw_helper.h"
struct pipe_screen *
drisw_create_screen(struct drisw_loader_funcs *lf)
{
struct sw_winsys *winsys = NULL;
struct pipe_screen *screen = NULL;
winsys = dri_create_sw_winsys(lf);
if (winsys == NULL)
return NULL;
screen = noop_screen_create(winsys);
if (!screen)
goto fail;
screen = debug_screen_wrap(screen);
return screen;
fail:
if (winsys)
winsys->destroy(winsys);
return NULL;
}
/* vim: set sw=3 ts=8 sts=3 expandtab: */

5
src/gallium/targets/dri-r600/Makefile
View file

@ -9,7 +9,8 @@ PIPE_DRIVERS = \
$(TOP)/src/gallium/winsys/r600/drm/libr600winsys.a \
$(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \
$(TOP)/src/gallium/drivers/trace/libtrace.a \
$(TOP)/src/gallium/drivers/rbug/librbug.a
$(TOP)/src/gallium/drivers/rbug/librbug.a \
$(TOP)/src/gallium/drivers/noop/libnoop.a
C_SOURCES = \
target.c \
@ -17,7 +18,7 @@ C_SOURCES = \
$(DRIVER_SOURCES)
DRIVER_DEFINES = \
-DGALLIUM_RBUG -DGALLIUM_TRACE
-DGALLIUM_RBUG -DGALLIUM_TRACE -DGALLIUM_NOOP
include ../Makefile.dri

2
src/gallium/targets/dri-r600/target.c
View file

@ -1,5 +1,5 @@
#include "state_tracker/drm_driver.h"
#include "target-helpers/inline_debug_helper.h"
#include "target-helpers/inline_noop_helper.h"
#include "r600/drm/r600_drm_public.h"
#include "r600/r600_public.h"

25
src/gallium/targets/egl/Makefile
View file

@ -57,12 +57,6 @@ endif
ifneq ($(filter $(GL_LIB), $(EGL_CLIENT_APIS)),)
egl_CPPFLAGS += $(API_DEFINES)
endif
ifneq ($(filter $(GLESv1_CM_LIB), $(EGL_CLIENT_APIS)),)
egl_CPPFLAGS += -DFEATURE_ES1=1
endif
ifneq ($(filter $(GLESv2_LIB), $(EGL_CLIENT_APIS)),)
egl_CPPFLAGS += -DFEATURE_ES2=1
endif
ifneq ($(filter $(VG_LIB), $(EGL_CLIENT_APIS)),)
egl_CPPFLAGS += -DFEATURE_VG=1
endif
@ -89,6 +83,7 @@ nouveau_LIBS := \
$(TOP)/src/gallium/winsys/nouveau/drm/libnouveaudrm.a \
$(TOP)/src/gallium/drivers/nvfx/libnvfx.a \
$(TOP)/src/gallium/drivers/nv50/libnv50.a \
$(TOP)/src/gallium/drivers/nvc0/libnvc0.a \
$(TOP)/src/gallium/drivers/nouveau/libnouveau.a
# r300 pipe driver
@ -127,20 +122,10 @@ endif
# OpenGL state tracker
GL_CPPFLAGS := -I$(TOP)/src/mesa $(API_DEFINES)
# do not link to $(GL_LIB) as the it supports GLES too
# cannot not link to $(GL_LIB) as the app might want GLES
GL_SYS := $(DRI_LIB_DEPS)
GL_LIBS := $(TOP)/src/mesa/libmesagallium.a
# OpenGL ES 1.x state tracker
GLESv1_CM_CPPFLAGS := -I$(TOP)/src/mesa
GLESv1_CM_SYS := $(DRI_LIB_DEPS) -l$(GLESv1_CM_LIB)
GLESv1_CM_LIBS := $(TOP)/src/mesa/libes1gallium.a
# OpenGL ES 2.x state tracker
GLESv2_CPPFLAGS := -I$(TOP)/src/mesa
GLESv2_SYS := $(DRI_LIB_DEPS) -l$(GLESv2_LIB)
GLESv2_LIBS := $(TOP)/src/mesa/libes2gallium.a
# OpenVG state tracker
OpenVG_CPPFLAGS := -I$(TOP)/src/gallium/state_trackers/vega
OpenVG_SYS := -lm -l$(VG_LIB)
@ -225,12 +210,6 @@ $(OUTPUT_PATH)/$(PIPE_PREFIX)swrast.so: pipe_swrast.o $(swrast_LIBS)
$(OUTPUT_PATH)/$(ST_PREFIX)$(GL_LIB).so: st_GL.o $(GL_LIBS)
$(call mklib-cxx,GL)
$(OUTPUT_PATH)/$(ST_PREFIX)$(GLESv1_CM_LIB).so: st_GLESv1_CM.o $(GLESv1_CM_LIBS)
$(call mklib-cxx,GLESv1_CM)
$(OUTPUT_PATH)/$(ST_PREFIX)$(GLESv2_LIB).so: st_GLESv2.o $(GLESv2_LIBS)
$(call mklib-cxx,GLESv2)
$(OUTPUT_PATH)/$(ST_PREFIX)$(VG_LIB).so: st_OpenVG.o $(OpenVG_LIBS)
$(call mklib,OpenVG)

14
src/gallium/targets/egl/egl.c
View file

@ -205,19 +205,7 @@ get_st_api_full(enum st_api_type api, enum st_profile_type profile)
switch (api) {
case ST_API_OPENGL:
symbol = ST_CREATE_OPENGL_SYMBOL;
switch (profile) {
case ST_PROFILE_OPENGL_ES1:
names[count++] = "GLESv1_CM";
names[count++] = "GL";
break;
case ST_PROFILE_OPENGL_ES2:
names[count++] = "GLESv2";
names[count++] = "GL";
break;
default:
names[count++] = "GL";
break;
}
names[count++] = "GL";
break;
case ST_API_OPENVG:
symbol = ST_CREATE_OPENVG_SYMBOL;

8
src/gallium/targets/egl/st_GLESv1_CM.c
View file

@ -1,8 +0,0 @@
#include "state_tracker/st_gl_api.h"
#include "egl.h"
PUBLIC struct st_api *
st_api_create_OpenGL(void)
{
return st_gl_api_create();
}

8
src/gallium/targets/egl/st_GLESv2.c
View file

@ -1,8 +0,0 @@
#include "state_tracker/st_gl_api.h"
#include "egl.h"
PUBLIC struct st_api *
st_api_create_OpenGL(void)
{
return st_gl_api_create();
}

4
src/gallium/winsys/i965/drm/i965_drm_buffer.c
View file

@ -325,7 +325,7 @@ i965_libdrm_bo_subdata(struct brw_winsys_buffer *buffer,
brw_dump_data( idws->base.pci_id,
data_type,
buf->bo->offset + offset,
data, size );
data, size, buffer->sws->gen );
/* XXX: use bo_map_gtt/memcpy/unmap_gtt under some circumstances???
*/
@ -464,7 +464,7 @@ i965_libdrm_bo_flush_range(struct brw_winsys_buffer *buffer,
buf->data_type,
buf->bo->offset + offset,
(char*)buf->bo->virtual + offset,
length );
length, buffer->sws->gen );
}
static void

5
src/gallium/winsys/r600/drm/evergreen_hw_context.c
View file

@ -621,10 +621,7 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
/* save 16dwords space for fence mecanism */
ctx->pm4_ndwords -= 16;
r = r600_context_init_fence(ctx);
if (r) {
goto out_err;
}
LIST_INITHEAD(&ctx->fenced_bo);
/* init dirty list */
LIST_INITHEAD(&ctx->dirty);

22
src/gallium/winsys/r600/drm/r600_drm.c
View file

@ -30,6 +30,7 @@
#include <sys/ioctl.h>
#include "util/u_inlines.h"
#include "util/u_debug.h"
#include <pipebuffer/pb_bufmgr.h>
#include "r600.h"
#include "r600_priv.h"
#include "r600_drm_public.h"
@ -125,6 +126,18 @@ static int radeon_drm_get_tiling(struct radeon *radeon)
return 0;
}
static int radeon_init_fence(struct radeon *radeon)
{
radeon->fence = 1;
radeon->fence_bo = r600_bo(radeon, 4096, 0, 0, 0);
if (radeon->fence_bo == NULL) {
return -ENOMEM;
}
radeon->cfence = r600_bo_map(radeon, radeon->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL);
*radeon->cfence = 0;
return 0;
}
static struct radeon *radeon_new(int fd, unsigned device)
{
struct radeon *radeon;
@ -198,6 +211,11 @@ static struct radeon *radeon_new(int fd, unsigned device)
if (radeon->bomgr == NULL) {
return NULL;
}
r = radeon_init_fence(radeon);
if (r) {
radeon_decref(radeon);
return NULL;
}
return radeon;
}
@ -214,6 +232,10 @@ struct radeon *radeon_decref(struct radeon *radeon)
return NULL;
}
if (radeon->fence_bo) {
r600_bo_reference(radeon, &radeon->fence_bo, NULL);
}
if (radeon->bomgr)
r600_bomgr_destroy(radeon->bomgr);

48
src/gallium/winsys/r600/drm/r600_hw_context.c
View file

@ -40,27 +40,13 @@
#define GROUP_FORCE_NEW_BLOCK 0
int r600_context_init_fence(struct r600_context *ctx)
{
ctx->fence = 1;
ctx->fence_bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
if (ctx->fence_bo == NULL) {
return -ENOMEM;
}
ctx->cfence = r600_bo_map(ctx->radeon, ctx->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL);
*ctx->cfence = 0;
ctx->radeon->cfence = ctx->cfence;
LIST_INITHEAD(&ctx->fenced_bo);
return 0;
}
static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
{
for (int i = 0; i < ctx->creloc; i++) {
if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
LIST_DELINIT(&ctx->bo[i]->fencedlist);
LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
ctx->bo[i]->fence = ctx->fence;
ctx->bo[i]->fence = ctx->radeon->fence;
ctx->bo[i]->ctx = ctx;
}
}
@ -71,7 +57,7 @@ static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsig
struct radeon_bo *tmp;
LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
if (bo->fence <= *ctx->cfence) {
if (bo->fence <= *ctx->radeon->cfence) {
LIST_DELINIT(&bo->fencedlist);
bo->fence = 0;
} else {
@ -632,9 +618,6 @@ void r600_context_fini(struct r600_context *ctx)
free(ctx->pm4);
r600_context_clear_fenced_bo(ctx);
if (ctx->fence_bo) {
r600_bo_reference(ctx->radeon, &ctx->fence_bo, NULL);
}
memset(ctx, 0, sizeof(struct r600_context));
}
@ -763,10 +746,7 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
/* save 16dwords space for fence mecanism */
ctx->pm4_ndwords -= 16;
r = r600_context_init_fence(ctx);
if (r) {
goto out_err;
}
LIST_INITHEAD(&ctx->fenced_bo);
/* init dirty list */
LIST_INITHEAD(&ctx->dirty);
@ -814,7 +794,7 @@ void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *r
ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
ctx->reloc[ctx->creloc].flags = 0;
radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
rbo->fence = ctx->fence;
rbo->fence = ctx->radeon->fence;
ctx->creloc++;
/* set PKT3 to point to proper reloc */
*pm4 = bo->reloc_id;
@ -837,7 +817,7 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat
/* find relocation */
id = block->pm4_bo_index[id];
r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
state->regs[i].bo->fence = ctx->fence;
state->regs[i].bo->fence = ctx->radeon->fence;
}
if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
block->status |= R600_BLOCK_STATUS_ENABLED;
@ -877,13 +857,13 @@ static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx
*/
r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
state->regs[0].bo->fence = ctx->fence;
state->regs[0].bo->fence = ctx->radeon->fence;
} else {
/* TEXTURE RESOURCE */
r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
state->regs[2].bo->fence = ctx->fence;
state->regs[3].bo->fence = ctx->fence;
state->regs[2].bo->fence = ctx->radeon->fence;
state->regs[3].bo->fence = ctx->radeon->fence;
}
if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
block->status |= R600_BLOCK_STATUS_ENABLED;
@ -1123,11 +1103,11 @@ void r600_context_flush(struct r600_context *ctx)
ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
ctx->pm4[ctx->pm4_cdwords++] = 0;
ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
ctx->pm4[ctx->pm4_cdwords++] = ctx->fence;
ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
ctx->pm4[ctx->pm4_cdwords++] = 0;
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
ctx->pm4[ctx->pm4_cdwords++] = 0;
r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->fence_bo);
r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
#if 1
/* emit cs */
@ -1144,18 +1124,18 @@ void r600_context_flush(struct r600_context *ctx)
r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
sizeof(struct drm_radeon_cs));
#else
*ctx->cfence = ctx->fence;
*ctx->radeon->cfence = ctx->radeon->fence;
#endif
r600_context_update_fenced_list(ctx);
fence = ctx->fence + 1;
if (fence < ctx->fence) {
fence = ctx->radeon->fence + 1;
if (fence < ctx->radeon->fence) {
/* wrap around */
fence = 1;
r600_context_fence_wraparound(ctx, fence);
}
ctx->fence = fence;
ctx->radeon->fence = fence;
/* restart */
for (int i = 0; i < ctx->creloc; i++) {

3
src/gallium/winsys/r600/drm/r600_priv.h
View file

@ -36,6 +36,7 @@
#include "r600.h"
struct r600_bomgr;
struct r600_bo;
struct radeon {
int fd;
@ -45,7 +46,9 @@ struct radeon {
enum chip_class chip_class;
struct r600_tiling_info tiling_info;
struct r600_bomgr *bomgr;
unsigned fence;
unsigned *cfence;
struct r600_bo *fence_bo;
};
struct r600_reg {

4
src/gallium/winsys/r600/drm/radeon_bo.c
View file

@ -156,7 +156,7 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo)
if (!bo->shared) {
if (!bo->fence)
return 0;
if (bo->fence <= *bo->ctx->cfence) {
if (bo->fence <= *radeon->cfence) {
LIST_DELINIT(&bo->fencedlist);
bo->fence = 0;
return 0;
@ -181,7 +181,7 @@ int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain
if (!bo->shared) {
if (!bo->fence)
return 0;
if (bo->fence <= *bo->ctx->cfence) {
if (bo->fence <= *radeon->cfence) {
LIST_DELINIT(&bo->fencedlist);
bo->fence = 0;
return 0;

1
src/glsl/.gitignore vendored
View file

@ -1,2 +1,3 @@
glsl_compiler
glsl_parser.output
builtin_function.cpp

19
src/glsl/Makefile
View file

@ -24,7 +24,6 @@ CXX_SOURCES = \
ast_function.cpp \
ast_to_hir.cpp \
ast_type.cpp \
builtin_function.cpp \
glsl_lexer.cpp \
glsl_parser.cpp \
glsl_parser_extras.cpp \
@ -130,8 +129,8 @@ ALL_SOURCES = \
default: depend lib$(LIBNAME).a $(APPS)
lib$(LIBNAME).a: $(OBJECTS) Makefile $(TOP)/src/glsl/Makefile.template
$(MKLIB) -cplusplus -o $(LIBNAME) -static $(OBJECTS)
lib$(LIBNAME).a: $(OBJECTS) builtin_function.o Makefile $(TOP)/src/glsl/Makefile.template
$(MKLIB) -cplusplus -o $(LIBNAME) -static $(OBJECTS) builtin_function.o
depend: $(ALL_SOURCES) Makefile
rm -f depend
@ -140,7 +139,7 @@ depend: $(ALL_SOURCES) Makefile
# Remove .o and backup files
clean:
rm -f $(GLCPP_OBJECTS) $(GLSL2_OBJECTS) $(OBJECTS) lib$(LIBNAME).a depend depend.bak
rm -f $(GLCPP_OBJECTS) $(GLSL2_OBJECTS) $(OBJECTS) lib$(LIBNAME).a depend depend.bak builtin_function.cpp builtin_function.o builtin_stubs.o builtin_compiler
-rm -f $(APPS)
# Dummy target
@ -174,13 +173,11 @@ glcpp/glcpp-lex.c: glcpp/glcpp-lex.l
glcpp/glcpp-parse.c: glcpp/glcpp-parse.y
bison -v -o "$@" --defines=glcpp/glcpp-parse.h $<
builtins: builtin_function.cpp builtins/profiles/* builtins/ir/* builtins/tools/generate_builtins.py builtins/tools/texture_builtins.py
@echo Bootstrapping the compiler...
cp builtins/tools/builtin_function.cpp .
make glsl_compiler
builtin_compiler: $(GLSL2_OBJECTS) $(OBJECTS) builtin_stubs.o
$(APP_CXX) $(INCLUDES) $(CFLAGS) $(LDFLAGS) $(TALLOC_LIBS) $(OBJECTS) $(GLSL2_OBJECTS) builtin_stubs.o -o builtin_compiler
builtin_function.cpp: builtins/profiles/* builtins/ir/* builtins/tools/generate_builtins.py builtins/tools/texture_builtins.py builtin_compiler
@echo Regenerating builtin_function.cpp...
$(PYTHON2) $(PYTHON_FLAGS) builtins/tools/generate_builtins.py > builtin_function.cpp
@echo Rebuilding the real compiler...
make glsl_compiler
$(PYTHON2) $(PYTHON_FLAGS) builtins/tools/generate_builtins.py $(PWD)/builtin_compiler > builtin_function.cpp
-include depend

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