diff --git a/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp b/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp index 704bf5b6d3b..34c85b115a5 100644 --- a/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp +++ b/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp @@ -1334,7 +1334,8 @@ visit_load_interpolated_input(isel_context* ctx, nir_intrinsic_instr* instr) { Temp dst = get_ssa_temp(ctx, &instr->def); Temp coords = get_ssa_temp(ctx, instr->src[0].ssa); - unsigned idx = nir_intrinsic_base(instr); + unsigned idx = + ac_nir_get_io_driver_location(ctx->shader, nir_intrinsic_io_semantics(instr).location, true); unsigned component = nir_intrinsic_component(instr); bool high_16bits = nir_intrinsic_io_semantics(instr).high_16bits; Temp prim_mask = get_arg(ctx, ctx->args->prim_mask); @@ -1470,9 +1471,10 @@ visit_load_fs_input(isel_context* ctx, nir_intrinsic_instr* instr) Temp prim_mask = get_arg(ctx, ctx->args->prim_mask); - unsigned idx = nir_intrinsic_base(instr); + nir_io_semantics sem = nir_intrinsic_io_semantics(instr); + unsigned idx = ac_nir_get_io_driver_location(ctx->shader, sem.location, true); unsigned component = nir_intrinsic_component(instr); - bool high_16bits = nir_intrinsic_io_semantics(instr).high_16bits; + bool high_16bits = sem.high_16bits; unsigned vertex_id = 0; /* P0 */ if (instr->intrinsic == nir_intrinsic_load_input_vertex) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index aa83d3b2531..6d3c1622de8 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -2634,7 +2634,8 @@ static LLVMValueRef visit_load_input(struct ac_nir_context *ctx, nir_intrinsic_i if (instr->intrinsic == nir_intrinsic_load_input_vertex) vertex_id = nir_src_as_uint(instr->src[0]); - unsigned base = nir_intrinsic_base(instr); + nir_shader *nir = nir_cf_node_get_function(&instr->instr.block->cf_node)->function->shader; + unsigned base = ac_nir_get_io_driver_location(nir, sem.location, true); LLVMValueRef attr_number = LLVMConstInt(ctx->ac.i32, base, false); LLVMTypeRef dest_type = get_def_type(ctx, &instr->def); LLVMValueRef values[8]; @@ -2823,7 +2824,9 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins assert(offset[0].i32 == 0); LLVMValueRef interp_param = get_src(ctx, instr->src[0]); - unsigned index = nir_intrinsic_base(instr); + nir_shader *nir = nir_cf_node_get_function(&instr->instr.block->cf_node)->function->shader; + unsigned index = + ac_nir_get_io_driver_location(nir, nir_intrinsic_io_semantics(instr).location, true); unsigned component = nir_intrinsic_component(instr); result = load_interpolated_input(ctx, interp_param, index, component, instr->def.num_components, instr->def.bit_size, diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 1b443e24936..4296c59ee8c 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -69,7 +69,7 @@ gather_load_fs_input_info(const nir_shader *nir, const nir_intrinsic_instr *intr { const nir_io_semantics io_sem = nir_intrinsic_io_semantics(intrin); const unsigned location = io_sem.location; - const unsigned mapped_location = nir_intrinsic_base(intrin); + const unsigned mapped_location = ac_nir_get_io_driver_location(nir, io_sem.location, true); const unsigned attrib_count = io_sem.num_slots; const unsigned component = nir_intrinsic_component(intrin); diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c index c4a4aeb1a81..2fce5c1a554 100644 --- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c +++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c @@ -592,8 +592,8 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s /* Load point coordinates (x, y) which are written by the hw after the interpolated inputs */ nir_def *baryc = intrin->src[0].ssa; replacement = nir_load_interpolated_input(b, 2, 32, baryc, nir_imm_int(b, 0), - .base = si_get_ps_num_interp(shader), - .component = 2); + .component = 2, + .io_semantics.location = VARYING_SLOT_PARAM_GEN_AMD); break; } case nir_intrinsic_load_poly_line_smooth_enabled: diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c index 068261b9e59..c2b4cf4dbce 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_info.c @@ -205,7 +205,7 @@ static void gather_io_instrinsic(const nir_shader *nir, struct si_shader_info *i unsigned num_slots = indirect ? nir_intrinsic_io_semantics(intr).num_slots : 1; unsigned driver_location; - if (nir->info.stage == MESA_SHADER_FRAGMENT && !is_input) + if (nir->info.stage == MESA_SHADER_FRAGMENT) driver_location = ac_nir_get_io_driver_location(nir, semantic, is_input); else driver_location = nir_intrinsic_base(intr); diff --git a/src/gallium/drivers/radeonsi/si_shader_variant_info.c b/src/gallium/drivers/radeonsi/si_shader_variant_info.c index d2872456107..f2ab5e9f674 100644 --- a/src/gallium/drivers/radeonsi/si_shader_variant_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_variant_info.c @@ -184,7 +184,7 @@ void si_get_shader_variant_info(struct si_shader *shader, shader->info.uses_vmem_load_other = true; } else if (nir->info.stage == MESA_SHADER_FRAGMENT) { nir_io_semantics sem = nir_intrinsic_io_semantics(intr); - unsigned index = nir_intrinsic_base(intr); + unsigned index = ac_nir_get_io_driver_location(nir, sem.location, true); assert(sem.num_slots == 1); shader->info.num_ps_inputs = MAX2(shader->info.num_ps_inputs, index + 1); @@ -204,13 +204,21 @@ void si_get_shader_variant_info(struct si_shader *shader, break; } case nir_intrinsic_load_color0_amd: - assert(!shader->is_monolithic); - shader->info.ps_colors_read |= nir_def_components_read(&intr->def); - break; - case nir_intrinsic_load_color1_amd: - assert(!shader->is_monolithic); - shader->info.ps_colors_read |= nir_def_components_read(&intr->def) << 4; + case nir_intrinsic_load_color1_amd: { + assert(!shader->is_monolithic && nir->info.stage == MESA_SHADER_FRAGMENT); + unsigned col_index = intr->intrinsic == nir_intrinsic_load_color1_amd; + shader->info.ps_colors_read |= nir_def_components_read(&intr->def) << (col_index * 4); + + gl_varying_slot location = VARYING_SLOT_COL0 + col_index; + unsigned index = ac_nir_get_io_driver_location(nir, location, true); + unsigned interp = shader->selector->info.color_interpolate[col_index]; + + shader->info.num_ps_inputs = MAX2(shader->info.num_ps_inputs, index + 1); + shader->info.ps_inputs[index].semantic = location; + shader->info.ps_inputs[index].interpolate = + interp == INTERP_MODE_NONE ? INTERP_MODE_COLOR : interp; break; + } case nir_intrinsic_load_ubo: if (intr->src[1].ssa->divergent) shader->info.uses_vmem_load_other = true; @@ -333,28 +341,19 @@ void si_get_shader_variant_info(struct si_shader *shader, } if (nir->info.stage == MESA_SHADER_FRAGMENT) { - /* Add both front and back color inputs. */ + /* Add back color inputs. */ if (!shader->is_monolithic) { unsigned index = shader->info.num_ps_inputs; - for (unsigned back = 0; back < 2; back++) { - for (unsigned i = 0; i < 2; i++) { - if ((shader->info.ps_colors_read >> (i * 4)) & 0xf) { - assert(index < ARRAY_SIZE(shader->info.ps_inputs)); - shader->info.ps_inputs[index].semantic = - (back ? VARYING_SLOT_BFC0 : VARYING_SLOT_COL0) + i; + for (unsigned i = 0; i < 2; i++) { + if ((shader->info.ps_colors_read >> (i * 4)) & 0xf) { + assert(index < ARRAY_SIZE(shader->info.ps_inputs)); + shader->info.ps_inputs[index].semantic = VARYING_SLOT_BFC0 + i; - enum glsl_interp_mode mode = shader->selector->info.color_interpolate[i]; - shader->info.ps_inputs[index].interpolate = - mode == INTERP_MODE_NONE ? INTERP_MODE_COLOR : mode; - index++; - - /* Back-face colors don't increment num_ps_inputs. si_emit_spi_map will use - * back-face colors conditionally only when needed. - */ - if (!back) - shader->info.num_ps_inputs++; - } + enum glsl_interp_mode mode = shader->selector->info.color_interpolate[i]; + shader->info.ps_inputs[index].interpolate = + mode == INTERP_MODE_NONE ? INTERP_MODE_COLOR : mode; + index++; } } }