From a9525f4b44a9353c496175d0a059043487aebcf0 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 19 May 2026 14:20:42 -0400 Subject: [PATCH] jay: hack for sample position Adding this to the list of design constraints for the next RA rework. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/intel/compiler/jay/jay_nir.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/intel/compiler/jay/jay_nir.c b/src/intel/compiler/jay/jay_nir.c index 2f5f3551eb0..c490f77ee1b 100644 --- a/src/intel/compiler/jay/jay_nir.c +++ b/src/intel/compiler/jay/jay_nir.c @@ -11,6 +11,7 @@ #include "nir.h" #include "nir_builder.h" #include "nir_intrinsics.h" +#include "shader_enums.h" /* * Jay-to-NIR relies on a careful indexing of defs: every 32-bit word has @@ -260,6 +261,17 @@ jay_process_nir(const struct intel_device_info *devinfo, /* TODO: Real heuristic */ bool do_simd32 = INTEL_SIMD(FS, 32); do_simd32 &= stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_FRAGMENT; + + /* TODO: The SIMD32 fragment payload is even more fragmented than RA + * currently models when sample position is read. RA needs a rework to handle + * the real partitions in a proper way (this is planned soon). + * + * Hot fix for + * dEQP-GLES31.functional.shaders.sample_variables.sample_pos.correctness.multisample_texture_4 + */ + do_simd32 &= + !BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS); + unsigned simd_width = do_simd32 ? (nir->info.api_subgroup_size ?: 32) : 16; if (stage == MESA_SHADER_VERTEX) {