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freedreno/a5xx: fix draw packet size with index buffer

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gpuaddr of idx buffer is now two dwords (64b).

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2016-12-06 15:52:28 -05:00
parent ec24f009ca
commit a9383ae6d6
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/freedreno/a5xx/fd5_draw.h
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@ -53,7 +53,7 @@ fd5_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
*/
emit_marker5(ring, 7);
OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 6 : 3);
OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 7 : 3);
if (vismode == USE_VISIBILITY) {
/* leave vis mode blank for now, it will be patched up when
* we know if we are binning or not