From a92d1d13c5d57a26a537476b5b62fa6b27a55bcc Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 7 Nov 2022 14:21:03 +0100 Subject: [PATCH] radv: add support for dynamic color write mask Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 95 +++++++++++++++++++++++--------- src/amd/vulkan/radv_pipeline.c | 34 ++++++++---- src/amd/vulkan/radv_private.h | 24 +++++--- src/amd/vulkan/radv_shader.h | 1 + 4 files changed, 107 insertions(+), 47 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b6f4a9ae544..afe1dedb051 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -133,6 +133,7 @@ const struct radv_dynamic_state default_dynamic_state = { .depth_clip_negative_one_to_one = 0u, .provoking_vertex_mode = VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT, .depth_clamp_enable = 0u, + .color_write_mask = 0u, }; static void @@ -288,6 +289,8 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy RADV_CMP_COPY(depth_clamp_enable, RADV_DYNAMIC_DEPTH_CLAMP_ENABLE); + RADV_CMP_COPY(color_write_mask, RADV_DYNAMIC_COLOR_WRITE_MASK); + #undef RADV_CMP_COPY cmd_buffer->state.dirty |= dest_mask; @@ -1154,9 +1157,11 @@ struct radv_bin_size_entry { static VkExtent2D radv_gfx10_compute_bin_size(struct radv_graphics_pipeline *pipeline, - struct radv_rendering_state *render) + struct radv_cmd_buffer *cmd_buffer) { const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; + const struct radv_rendering_state *render = &cmd_buffer->state.render; + const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; VkExtent2D extent = {512, 512}; const unsigned db_tag_size = 64; @@ -1188,7 +1193,7 @@ radv_gfx10_compute_bin_size(struct radv_graphics_pipeline *pipeline, if (!iview) continue; - if (!((pipeline->cb_target_mask >> (i * 4)) & 0xf)) + if (!((d->color_write_mask >> (i * 4)) & 0xf)) continue; color_bytes_per_pixel += vk_format_get_blocksize(render->color_att[i].format); @@ -1241,10 +1246,12 @@ radv_gfx10_compute_bin_size(struct radv_graphics_pipeline *pipeline, static VkExtent2D radv_gfx9_compute_bin_size(struct radv_graphics_pipeline *pipeline, - struct radv_rendering_state *render) + struct radv_cmd_buffer *cmd_buffer) { const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; + const struct radv_rendering_state *render = &cmd_buffer->state.render; + const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; static const struct radv_bin_size_entry color_size_table[][3][9] = { { /* One RB / SE */ @@ -1472,7 +1479,7 @@ radv_gfx9_compute_bin_size(struct radv_graphics_pipeline *pipeline, if (!iview) continue; - if (!((pipeline->cb_target_mask >> (i * 4)) & 0xf)) + if (!((d->color_write_mask >> (i * 4)) & 0xf)) continue; color_bytes_per_pixel += vk_format_get_blocksize(render->color_att[i].format); @@ -1508,9 +1515,11 @@ radv_gfx9_compute_bin_size(struct radv_graphics_pipeline *pipeline, static unsigned radv_get_disabled_binning_state(struct radv_graphics_pipeline *pipeline, - struct radv_rendering_state *render) + struct radv_cmd_buffer *cmd_buffer) { const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; + const struct radv_rendering_state *render = &cmd_buffer->state.render; + const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; uint32_t pa_sc_binner_cntl_0; if (pdevice->rad_info.gfx_level >= GFX10) { @@ -1522,7 +1531,7 @@ radv_get_disabled_binning_state(struct radv_graphics_pipeline *pipeline, if (!iview) continue; - if (!((pipeline->cb_target_mask >> (i * 4)) & 0xf)) + if (!((d->color_write_mask >> (i * 4)) & 0xf)) continue; unsigned bytes = vk_format_get_blocksize(render->color_att[i].format); @@ -1548,17 +1557,17 @@ radv_get_disabled_binning_state(struct radv_graphics_pipeline *pipeline, } static unsigned -radv_get_binning_state(struct radv_graphics_pipeline *pipeline, struct radv_rendering_state *render) +radv_get_binning_state(struct radv_graphics_pipeline *pipeline, struct radv_cmd_buffer *cmd_buffer) { const struct radv_device *device = pipeline->base.device; unsigned pa_sc_binner_cntl_0; VkExtent2D bin_size; if (device->physical_device->rad_info.gfx_level >= GFX10) { - bin_size = radv_gfx10_compute_bin_size(pipeline, render); + bin_size = radv_gfx10_compute_bin_size(pipeline, cmd_buffer); } else { assert(device->physical_device->rad_info.gfx_level == GFX9); - bin_size = radv_gfx9_compute_bin_size(pipeline, render); + bin_size = radv_gfx9_compute_bin_size(pipeline, cmd_buffer); } if (device->pbb_allowed && bin_size.width && bin_size.height) { @@ -1578,7 +1587,7 @@ radv_get_binning_state(struct radv_graphics_pipeline *pipeline, struct radv_rend device->physical_device->rad_info.family == CHIP_VEGA20 || device->physical_device->rad_info.family >= CHIP_RAVEN2); } else { - pa_sc_binner_cntl_0 = radv_get_disabled_binning_state(pipeline, render); + pa_sc_binner_cntl_0 = radv_get_disabled_binning_state(pipeline, cmd_buffer); } return pa_sc_binner_cntl_0; @@ -1592,7 +1601,7 @@ radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer, struct radv_graphics if (pipeline->base.device->physical_device->rad_info.gfx_level < GFX9) return; - pa_sc_binner_cntl_0 = radv_get_binning_state(pipeline, &cmd_buffer->state.render); + pa_sc_binner_cntl_0 = radv_get_binning_state(pipeline, cmd_buffer); if (pa_sc_binner_cntl_0 == cmd_buffer->state.last_pa_sc_binner_cntl_0) return; @@ -1668,6 +1677,7 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer) return; struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; + const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; struct radv_rendering_state *render = &cmd_buffer->state.render; unsigned sx_ps_downconvert = 0; @@ -1695,7 +1705,7 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer) : !G_028C74_FORCE_DST_ALPHA_1_GFX6(cb->cb_color_attrib); uint32_t spi_format = (pipeline->col_format_non_compacted >> (i * 4)) & 0xf; - uint32_t colormask = (pipeline->cb_target_mask >> (i * 4)) & 0xf; + uint32_t colormask = (d->color_write_mask >> (i * 4)) & 0xf; if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 || format == V_028C70_COLOR_32) has_rgb = !has_alpha; @@ -1857,7 +1867,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) return; radv_update_multisample_state(cmd_buffer, pipeline); - radv_emit_binning_state(cmd_buffer, pipeline); cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed, pipeline->base.scratch_bytes_per_wave); @@ -1885,21 +1894,19 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) RADV_CMD_DIRTY_DYNAMIC_POLYGON_MODE | RADV_CMD_DIRTY_DYNAMIC_PROVOKING_VERTEX_MODE | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT | - RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE; + RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE; if (!cmd_buffer->state.emitted_graphics_pipeline || radv_rast_prim_is_points_or_lines(cmd_buffer->state.emitted_graphics_pipeline->rast_prim) != radv_rast_prim_is_points_or_lines(pipeline->rast_prim)) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_GUARDBAND; if (!cmd_buffer->state.emitted_graphics_pipeline || - cmd_buffer->state.emitted_graphics_pipeline->cb_color_control != pipeline->cb_color_control) + cmd_buffer->state.emitted_graphics_pipeline->cb_color_control != pipeline->cb_color_control || + cmd_buffer->state.emitted_graphics_pipeline->custom_blend_mode != pipeline->custom_blend_mode) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP | RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE; - if (!cmd_buffer->state.emitted_graphics_pipeline || - cmd_buffer->state.emitted_graphics_pipeline->cb_target_mask != pipeline->cb_target_mask) - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE; - if (!cmd_buffer->state.emitted_graphics_pipeline || cmd_buffer->state.emitted_graphics_pipeline->vgt_tf_param != pipeline->vgt_tf_param) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_TESS_DOMAIN_ORIGIN; @@ -2331,6 +2338,7 @@ radv_emit_clipping(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer) { + struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; unsigned cb_color_control = cmd_buffer->state.graphics_pipeline->cb_color_control; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; @@ -2344,17 +2352,24 @@ radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer) cb_color_control |= S_028808_DISABLE_DUAL_QUAD(d->logic_op_enable); } + if (pipeline->custom_blend_mode) { + cb_color_control |= S_028808_MODE(pipeline->custom_blend_mode); + } else if (d->color_write_mask) { + cb_color_control |= S_028808_MODE(V_028808_CB_NORMAL); + } else { + cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE); + } + radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, cb_color_control); } static void -radv_emit_color_write_enable(struct radv_cmd_buffer *cmd_buffer) +radv_emit_color_write(struct radv_cmd_buffer *cmd_buffer) { - struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, - pipeline->cb_target_mask & d->color_write_enable); + d->color_write_mask & d->color_write_enable); } static void @@ -3956,11 +3971,13 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE)) radv_emit_clipping(cmd_buffer); - if (states & (RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP | RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE)) + if (states & (RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP | RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK)) radv_emit_logic_op(cmd_buffer); - if (states & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) - radv_emit_color_write_enable(cmd_buffer); + if (states & (RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK)) + radv_emit_color_write(cmd_buffer); if (states & RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT) radv_emit_vertex_input(cmd_buffer, pipeline_is_dirty); @@ -6540,6 +6557,27 @@ radv_CmdSetDepthClampEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthClam state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE; } +VKAPI_ATTR void VKAPI_CALL +radv_CmdSetColorWriteMaskEXT(VkCommandBuffer commandBuffer, uint32_t firstAttachment, + uint32_t attachmentCount, const VkColorComponentFlags *pColorWriteMasks) +{ + RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); + struct radv_cmd_state *state = &cmd_buffer->state; + uint32_t color_write_mask = 0; + + assert(firstAttachment + attachmentCount <= MAX_RTS); + + for (unsigned i = 0; i < attachmentCount; i++) { + unsigned idx = firstAttachment + i; + + color_write_mask |= pColorWriteMasks[i] << (4 * idx); + } + + state->dynamic.color_write_mask = color_write_mask; + + state->dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK; +} + VKAPI_ATTR void VKAPI_CALL radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer *pCmdBuffers) @@ -8081,6 +8119,10 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r cmd_buffer->state.graphics_pipeline->is_ngg) radv_emit_ngg_culling_state(cmd_buffer, info); + if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK) || + cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline) + radv_emit_binning_state(cmd_buffer, cmd_buffer->state.graphics_pipeline); + if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) radv_emit_graphics_pipeline(cmd_buffer); @@ -8129,7 +8171,8 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r if (device->pbb_allowed) { struct radv_binning_settings *settings = &device->physical_device->binning_settings; - if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) && + if ((cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK)) && settings->context_states_per_bin > 1) { /* Break the batch on CB_TARGET_MASK changes. */ radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index eeff707a94b..a7dcb6e9387 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -578,7 +578,9 @@ radv_pipeline_compute_spi_color_formats(const struct radv_graphics_pipeline *pip unsigned cf; VkFormat fmt = state->rp->color_attachment_formats[i]; - if (fmt == VK_FORMAT_UNDEFINED || !(blend->cb_target_mask & (0xfu << (i * 4)))) { + if (fmt == VK_FORMAT_UNDEFINED || + (!(pipeline->dynamic_states & RADV_DYNAMIC_COLOR_WRITE_MASK) && + !(blend->cb_target_mask & (0xfu << (i * 4))))) { cf = V_028714_SPI_SHADER_ZERO; } else { bool blend_enable = blend->blend_enable_4bit & (0xfu << (i * 4)); @@ -760,7 +762,8 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline, blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); - if (!state->cb->attachments[i].write_mask) + if (!(pipeline->dynamic_states & RADV_DYNAMIC_COLOR_WRITE_MASK) && + !state->cb->attachments[i].write_mask) continue; /* Ignore other blend targets if dual-source blending @@ -876,11 +879,6 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline, cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1); } - if (blend.cb_target_mask) - cb_color_control |= S_028808_MODE(V_028808_CB_NORMAL); - else - cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE); - if (state->rp) radv_pipeline_compute_spi_color_formats(pipeline, &blend, state, has_ps_epilog); @@ -1345,6 +1343,8 @@ radv_dynamic_state_mask(VkDynamicState state) return RADV_DYNAMIC_PROVOKING_VERTEX_MODE; case VK_DYNAMIC_STATE_DEPTH_CLAMP_ENABLE_EXT: return RADV_DYNAMIC_DEPTH_CLAMP_ENABLE; + case VK_DYNAMIC_STATE_COLOR_WRITE_MASK_EXT: + return RADV_DYNAMIC_COLOR_WRITE_MASK; default: unreachable("Unhandled dynamic state"); } @@ -1356,7 +1356,8 @@ radv_pipeline_is_blend_enabled(const struct radv_graphics_pipeline *pipeline, { if (cb) { for (uint32_t i = 0; i < cb->attachment_count; i++) { - if (cb->attachments[i].write_mask && cb->attachments[i].blend_enable) + if (((pipeline->dynamic_states & RADV_DYNAMIC_COLOR_WRITE_MASK) || + cb->attachments[i].write_mask) && cb->attachments[i].blend_enable) return true; } } @@ -1925,6 +1926,12 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline, dynamic->depth_clamp_enable = state->rs->depth_clamp_enable; } + if (radv_pipeline_has_color_attachments(state->rp) && states & RADV_DYNAMIC_COLOR_WRITE_MASK) { + for (unsigned i = 0; i < state->cb->attachment_count; i++) { + dynamic->color_write_mask |= state->cb->attachments[i].write_mask << (4 * i); + } + } + pipeline->dynamic_state.mask = states; } @@ -2284,6 +2291,10 @@ radv_remove_color_exports(const struct radv_pipeline_key *pipeline_key, nir_shad { bool fixup_derefs = false; + /* Do not remove color exports when the write mask is dynamic. */ + if (pipeline_key->dynamic_color_write_mask) + return; + nir_foreach_shader_out_variable(var, nir) { int idx = var->data.location; idx -= FRAG_RESULT_DATA0; @@ -2887,6 +2898,8 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin key.dynamic_rasterization_samples = !!(pipeline->active_stages & VK_SHADER_STAGE_FRAGMENT_BIT) && !state->ms; + key.dynamic_color_write_mask = !!(pipeline->dynamic_states & RADV_DYNAMIC_COLOR_WRITE_MASK); + return key; } @@ -5614,8 +5627,7 @@ radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline, if (extra->custom_blend_mode == V_028808_CB_RESOLVE) pipeline->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1); - pipeline->cb_color_control &= C_028808_MODE; - pipeline->cb_color_control |= S_028808_MODE(extra->custom_blend_mode); + pipeline->custom_blend_mode = extra->custom_blend_mode; } if (extra->use_rectlist) { @@ -5772,8 +5784,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv blend.cb_shader_mask &= ps->info.ps.colors_written; } - pipeline->cb_target_mask = blend.cb_target_mask; - if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) { struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY]; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 7b5c6531df4..6dc5e360f77 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1111,7 +1111,8 @@ enum radv_dynamic_state_bits { RADV_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE = 1ull << 38, RADV_DYNAMIC_PROVOKING_VERTEX_MODE = 1ull << 39, RADV_DYNAMIC_DEPTH_CLAMP_ENABLE = 1ull << 40, - RADV_DYNAMIC_ALL = (1ull << 41) - 1, + RADV_DYNAMIC_COLOR_WRITE_MASK = 1ull << 41, + RADV_DYNAMIC_ALL = (1ull << 42) - 1, }; enum radv_cmd_dirty_bits { @@ -1158,13 +1159,14 @@ enum radv_cmd_dirty_bits { RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLIP_NEGATIVE_ONE_TO_ONE = 1ull << 38, RADV_CMD_DIRTY_DYNAMIC_PROVOKING_VERTEX_MODE = 1ull << 39, RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE = 1ull << 40, - RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 41) - 1, - RADV_CMD_DIRTY_PIPELINE = 1ull << 41, - RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 42, - RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 43, - RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 44, - RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 45, - RADV_CMD_DIRTY_GUARDBAND = 1ull << 46, + RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK = 1ull << 41, + RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 42) - 1, + RADV_CMD_DIRTY_PIPELINE = 1ull << 42, + RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 43, + RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 44, + RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 45, + RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 46, + RADV_CMD_DIRTY_GUARDBAND = 1ull << 47, }; enum radv_cmd_flush_bits { @@ -1384,6 +1386,8 @@ struct radv_dynamic_state { VkProvokingVertexModeEXT provoking_vertex_mode; bool depth_clamp_enable; + + uint32_t color_write_mask; }; extern const struct radv_dynamic_state default_dynamic_state; @@ -2086,7 +2090,6 @@ struct radv_graphics_pipeline { /* Used for rbplus */ uint32_t col_format_non_compacted; - uint32_t cb_target_mask; bool disable_out_of_order_rast_for_occlusion; bool uses_drawid; @@ -2112,6 +2115,9 @@ struct radv_graphics_pipeline { /* Not NULL if graphics pipeline uses a PS epilog. */ struct radv_shader_part *ps_epilog; + + /* Custom blend mode for internal operations. */ + unsigned custom_blend_mode; }; struct radv_compute_pipeline { diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index bb8bf159391..89f21ceaa1b 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -64,6 +64,7 @@ struct radv_pipeline_key { uint32_t primitives_generated_query : 1; uint32_t dynamic_patch_control_points : 1; uint32_t dynamic_rasterization_samples : 1; + uint32_t dynamic_color_write_mask : 1; struct { uint32_t instance_rate_inputs;