diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 1698775dabf..66b5d6c9fb4 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -1792,6 +1792,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
                                S_0089B0_OFFCHIP_GRANULARITY(wg_size_enum);
    }
 
+   info->hs_offchip_workgroup_dw_size = wg_size_in_dwords;
    info->tess_offchip_ring_size = num_workgroups * wg_size_in_dwords * 4;
    info->tess_factor_ring_size = 48 * 1024 * info->max_se;
    info->total_tess_ring_size = info->tess_offchip_ring_size + info->tess_factor_ring_size;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index df27220c8cd..010866a062a 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -295,6 +295,7 @@ struct radeon_info {
 
    /* Tessellation rings. */
    uint32_t hs_offchip_param;
+   uint32_t hs_offchip_workgroup_dw_size;
    uint32_t tess_factor_ring_size;
    uint32_t tess_offchip_ring_size;
    uint32_t total_tess_ring_size;
diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index ae142488c1a..c6962ec39ee 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -966,11 +966,8 @@ uint32_t ac_compute_num_tess_patches(const struct radeon_info *info, uint32_t nu
       num_patches = MIN2(num_patches, 16); /* recommended */
 
    /* Make sure the output data fits in the offchip buffer */
-   if (vram_per_patch) {
-      const uint32_t tess_offchip_block_dw_size = info->family == CHIP_HAWAII ? 4096 : 8192;
-      num_patches =
-         MIN2(num_patches, (tess_offchip_block_dw_size * 4) / vram_per_patch);
-   }
+   if (vram_per_patch)
+      num_patches = MIN2(num_patches, (info->hs_offchip_workgroup_dw_size * 4) / vram_per_patch);
 
    /* Make sure that the data fits in LDS. This assumes the shaders only
     * use LDS for the inputs and outputs.