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r600: add missing ZPASS setup bits for r7xx+

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This commit is contained in:
Alex Deucher 2009-11-09 11:34:13 -05:00
parent bc9d51bb0e
commit a9035f3dc3
2 changed files with 6 additions and 0 deletions
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2
src/mesa/drivers/dri/r600/r600_reg_r7xx.h
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@ -143,6 +143,8 @@ enum {
// SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c,
R7xx_TRUNCATE_COORD_bit = 1 << 9,
R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10,
// DB_RENDER_CONTROL = 0x00028d0c,
PERFECT_ZPASS_COUNTS_bit = 1 << 15,
} ;

4
src/mesa/drivers/dri/r600/r700_state.c
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@ -1686,6 +1686,10 @@ void r700InitState(GLcontext * ctx) //-------------------
SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
{
CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
}
r700->DB_ALPHA_TO_MASK.u32All = 0;
SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);