fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 11:08:03 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

aco: use p_as_uniform in emit_vop1_instruction

Browse source 
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5245>
This commit is contained in:
Rhys Perry 2020-06-11 14:35:13 +01:00 • committed by Marge Bot
parent b6d9e45f47
commit a8f800a836
1 changed files with 15 additions and 41 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

56
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -640,7 +640,11 @@ void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode
void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
{
Builder bld(ctx->program, ctx->block);
bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
if (dst.type() == RegType::sgpr)
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
bld.vop1(op, bld.def(RegType::vgpr, dst.size()), get_alu_src(ctx, instr->src[0])));
else
bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
}
void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
@ -2326,32 +2330,22 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
case nir_op_f2i8:
case nir_op_f2i16: {
Temp src = get_alu_src(ctx, instr->src[0]);
Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v1);
if (instr->src[0].src.ssa->bit_size == 16)
src = bld.vop1(aco_opcode::v_cvt_i16_f16, Definition(tmp), src);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_i16_f16, dst);
else if (instr->src[0].src.ssa->bit_size == 32)
src = bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(tmp), src);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_i32_f32, dst);
else
src = bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(tmp), src);
if (dst.type() != RegType::vgpr)
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_i32_f64, dst);
break;
}
case nir_op_f2u8:
case nir_op_f2u16: {
Temp src = get_alu_src(ctx, instr->src[0]);
Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v1);
if (instr->src[0].src.ssa->bit_size == 16)
bld.vop1(aco_opcode::v_cvt_u16_f16, Definition(tmp), src);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u16_f16, dst);
else if (instr->src[0].src.ssa->bit_size == 32)
bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(tmp), src);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f32, dst);
else
bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(tmp), src);
if (dst.type() != RegType::vgpr)
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f64, dst);
break;
}
case nir_op_f2i32: {
@ -2365,19 +2359,9 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), tmp));
}
} else if (instr->src[0].src.ssa->bit_size == 32) {
if (dst.type() == RegType::vgpr)
bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
else
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_i32_f32, dst);
} else if (instr->src[0].src.ssa->bit_size == 64) {
if (dst.type() == RegType::vgpr)
bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
else
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_i32_f64, dst);
} else {
fprintf(stderr, "Unimplemented NIR instr bit size: ");
nir_print_instr(&instr->instr, stderr);
@ -2396,19 +2380,9 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), tmp));
}
} else if (instr->src[0].src.ssa->bit_size == 32) {
if (dst.type() == RegType::vgpr)
bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
else
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f32, dst);
} else if (instr->src[0].src.ssa->bit_size == 64) {
if (dst.type() == RegType::vgpr)
bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
else
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f64, dst);
} else {
fprintf(stderr, "Unimplemented NIR instr bit size: ");
nir_print_instr(&instr->instr, stderr);