From a8d669b593122a91c6ba2fefbb7ab308c7477300 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Corentin=20No=C3=ABl?= Date: Tue, 27 Jun 2023 16:28:41 +0200 Subject: [PATCH] nir/split_64bit_vec3_and_vec4: Use the right number of components MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Always make sure to correctly deref and store a 64bits variable from the right number of components. This fixes the `spec@arb_enhanced_layouts@matching_fp64_types_` piglit tests for virgl. Corrects this validation issue: ``` decl_var INTERP_MODE_FLAT dvec2[] var_7@2 decl_var INTERP_MODE_FLAT dvec2[] var_7@3 ... vec1 32 ssa_302 = deref_var &var_7@2 (function_temp dvec2[]) vec1 32 ssa_303 = deref_var &var_7@3 (function_temp dvec2[]) vec1 32 ssa_304 = deref_array &(*ssa_302)[ssa_301] (function_temp dvec2) /* &var_7@2[ssa_301] */ vec1 32 ssa_305 = deref_array &(*ssa_303)[ssa_301] (function_temp dvec2) /* &var_7@3[ssa_301] */ vec1 64 ssa_306 = mov ssa_110.z intrinsic store_deref (ssa_305, ssa_306) (wrmask=x, access=0) error: instr->num_components == glsl_get_vector_elements(dst->type) (../src/compiler/nir/nir_validate.c:632) vec4 64 ssa_111 = vec4 ssa_14, ssa_13, ssa_12, ssa_109 vec1 32 ssa_307 = load_const (0x00000000 = 0.000000) vec1 32 ssa_308 = iadd ssa_307, ssa_61 vec1 32 ssa_309 = deref_var &var_7@2 (function_temp dvec2[]) vec1 32 ssa_310 = deref_var &var_7@3 (function_temp dvec2[]) vec1 32 ssa_311 = deref_array &(*ssa_309)[ssa_308] (function_temp dvec2) /* &var_7@2[ssa_308] */ vec1 32 ssa_312 = deref_array &(*ssa_310)[ssa_308] (function_temp dvec2) /* &var_7@3[ssa_308] */ vec1 64 ssa_313 = mov ssa_111.w intrinsic store_deref (ssa_312, ssa_313) (wrmask=, access=0) error: (nir_intrinsic_write_mask(instr) & ~component_mask) == 0 (../src/compiler/nir/nir_validate.c:803) ``` Fixes: 496fd59d711b9a0744878918caeeaafb961e3deb (add pass to split 64 bit vec3/4 variable access) Signed-off-by: Corentin Noël Reviewed-by: Gert Wollny Reviewed-by: Emma Anholt Part-of: --- src/compiler/nir/nir_split_64bit_vec3_and_vec4.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c b/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c index d8fb960c572..4eb2276eb23 100644 --- a/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c +++ b/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c @@ -213,7 +213,8 @@ split_store_deref(nir_builder *b, nir_intrinsic_instr *intr, int write_mask_zw = nir_intrinsic_write_mask(intr) & 0xc; if (write_mask_zw) { - nir_ssa_def *src_zw = nir_channels(b, intr->src[1].ssa, write_mask_zw); + nir_ssa_def *src_zw = nir_channels(b, intr->src[1].ssa, + nir_component_mask(intr->src[1].ssa->num_components) & 0xc); nir_build_store_deref(b, &deref_zw->dest.ssa, src_zw, write_mask_zw >> 2); }