fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-31 07:00:27 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

freedreno: Rename IBO -> UAV

Browse source 
Internally, adreno uses dx terminology, and calls these UAVs.  Rename to
match.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35803>
This commit is contained in:
Rob Clark 2025-06-20 14:25:11 -07:00 • committed by Marge Bot
parent 12530fb8df
commit a8c052ca9d
29 changed files with 260 additions and 260 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

52
src/freedreno/.gitlab-ci/reference/crash.log
View file

@ -6775,7 +6775,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_VS_PVT_MEM_ADDR: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_VS_INSTRLEN: 0
00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -6786,7 +6786,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_PVT_MEM_ADDR: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_HS_INSTRLEN: 0
00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BRANCH_COND: 0
@ -6821,7 +6821,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_DS_PVT_MEM_ADDR: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_DS_INSTRLEN: 0
00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_PRIM_SIZE: 0
@ -6857,7 +6857,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_PVT_MEM_ADDR: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_GS_INSTRLEN: 0
ed21e0c4d9c6 SP_VS_TEX_SAMP: 0xed21e0c4d9c6
1a0573a9bba1 SP_HS_TEX_SAMP: 0x1a0573a9bba1
@ -6905,7 +6905,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_VS_PVT_MEM_ADDR: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_VS_INSTRLEN: 0
00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -6916,7 +6916,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_PVT_MEM_ADDR: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_HS_INSTRLEN: 0
00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BRANCH_COND: 0
@ -6951,7 +6951,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_DS_PVT_MEM_ADDR: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_DS_INSTRLEN: 0
00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_PRIM_SIZE: 0
@ -6987,7 +6987,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_PVT_MEM_ADDR: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_GS_INSTRLEN: 0
ed21e0c4d9c6 SP_VS_TEX_SAMP: 0xed21e0c4d9c6
1a0573a9bba1 SP_HS_TEX_SAMP: 0x1a0573a9bba1
@ -7026,26 +7026,26 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- cluster-name: CLUSTER_SP_VS
- context: 0
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_FS_INSTRLEN: 0
cd302764a40a SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xcd302764a408 }
17dc493870830 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x17dc493870830 }
14b45d3064206 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x14b45d3064204 }
1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ddc9bfafe9b8 }
bd3befda4292 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xbd3befda4290 }
13c400c0e0691 SP_IBO: 0x13c400c0e0691
00000040 SP_IBO_COUNT: 64
13c400c0e0691 SP_UAV: 0x13c400c0e0691
00000040 SP_UAV_COUNT: 64
- context: 1
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_FS_INSTRLEN: 0
cd302764a40a SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xcd302764a408 }
17dc493870830 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x17dc493870830 }
14b45d3064206 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x14b45d3064204 }
1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ddc9bfafe9b8 }
bd3befda4292 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0xbd3befda4290 }
13c400c0e0691 SP_IBO: 0x13c400c0e0691
00000040 SP_IBO_COUNT: 64
13c400c0e0691 SP_UAV: 0x13c400c0e0691
00000040 SP_UAV_COUNT: 64
- cluster-name: CLUSTER_SP_VS
- context: 0
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
@ -7181,7 +7181,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_CS_TEX_COUNT: 128
00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NIBO = 0 }
00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NUAV = 0 }
00000004 SP_CS_INSTRLEN: 4
00000000 0xa9d0: 00000000
00000000 0xa9d1: 00000000
@ -7196,8 +7196,8 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
76cd6915b33d SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x76cd6915b33c }
1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f2333cfd0194 }
16204a6b745da SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x16204a6b745d8 }
1d693fdfdd365 SP_CS_IBO: 0x1d693fdfdd365
00000040 SP_CS_IBO_COUNT: 64
1d693fdfdd365 SP_CS_UAV: 0x1d693fdfdd365
00000040 SP_CS_UAV_COUNT: 64
00000000 0xaa30: 00000000
00000000 0xaa31: 00000000
- context: 1
@ -7249,7 +7249,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_CS_TEX_COUNT: 128
00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NIBO = 0 }
00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NUAV = 0 }
00000004 SP_CS_INSTRLEN: 4
00000000 0xa9d0: 00000000
00000000 0xa9d1: 00000000
@ -7264,8 +7264,8 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
76cd6915b33d SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x76cd6915b33c }
1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f2333cfd0194 }
16204a6b745da SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x16204a6b745d8 }
1d693fdfdd365 SP_CS_IBO: 0x1d693fdfdd365
00000040 SP_CS_IBO_COUNT: 64
1d693fdfdd365 SP_CS_UAV: 0x1d693fdfdd365
00000040 SP_CS_UAV_COUNT: 64
00000000 0xaa30: 00000000
00000000 0xaa31: 00000000
- cluster-name: CLUSTER_SP_PS
@ -7337,26 +7337,26 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_FS_INSTRLEN: 0
7b4cdb94116 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x7b4cdb94114 }
1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f54b6e5e07c0 }
1b4555f979543 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1b4555f979540 }
13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x13f8ca4d3a8cc }
1ff601d337e76 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ff601d337e74 }
10202e0e8bc18 SP_IBO: 0x10202e0e8bc18
00000040 SP_IBO_COUNT: 64
10202e0e8bc18 SP_UAV: 0x10202e0e8bc18
00000040 SP_UAV_COUNT: 64
- context: 1
00000000 SP_MODE_CONTROL: { ISAMMODE = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_FS_INSTRLEN: 0
7b4cdb94116 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x7b4cdb94114 }
1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1f54b6e5e07c0 }
1b4555f979543 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1b4555f979540 }
13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x13f8ca4d3a8cc }
1ff601d337e76 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x1ff601d337e74 }
10202e0e8bc18 SP_IBO: 0x10202e0e8bc18
00000040 SP_IBO_COUNT: 64
10202e0e8bc18 SP_UAV: 0x10202e0e8bc18
00000040 SP_UAV_COUNT: 64
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }

112
src/freedreno/.gitlab-ci/reference/crash_prefetch.log
View file

@ -1979,7 +1979,7 @@ got cmdszdw=38
!+ 00000001 VFD_ADD_OFFSET: { VERTEX }
+ 00000000 SP_UNKNOWN_A9A8: 0
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000000 SP_IBO_COUNT: 0
+ 00000000 SP_UAV_COUNT: 0
!+ 0000f300 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_16_16_16_16_UNORM | MASK = 0xf }
+ 00000000 SP_DBG_ECO_CNTL: 0
!+ 00000430 SP_CHICKEN_BITS: 0x430
@ -1993,7 +1993,7 @@ got cmdszdw=38
!+ 00108000 TPL1_DBG_ECO_CNTL: 0x108000
!+ 00000044 TPL1_UNKNOWN_B605: 68
!+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
+ 00000000 HLSQ_UNKNOWN_BE01: 0
@ -2289,7 +2289,7 @@ got cmdszdw=38
+ 00000001 VFD_ADD_OFFSET: { VERTEX }
+ 00000000 SP_UNKNOWN_A9A8: 0
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000000 SP_IBO_COUNT: 0
+ 00000000 SP_UAV_COUNT: 0
+ 00000000 SP_DBG_ECO_CNTL: 0
+ 00000430 SP_CHICKEN_BITS: 0x430
+ 00000000 SP_FLOAT_CNTL: { 0 }
@ -2304,7 +2304,7 @@ got cmdszdw=38
+ 00108000 TPL1_DBG_ECO_CNTL: 0x108000
+ 00000044 TPL1_UNKNOWN_B605: 68
+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
+ 00000000 HLSQ_UNKNOWN_BE01: 0
@ -2856,13 +2856,13 @@ got cmdszdw=38
+ 00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
+ 00000000 SP_VS_PVT_MEM_ADDR: 0
+ 00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_VS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 81100300 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 6 | BRANCHSTACK = 0 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 1001e7080 SP_FS_OBJ_START: 0x1001e7080 base=1001e7000, offset=128, size=131072
@ -2933,7 +2933,7 @@ got cmdszdw=38
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000003 SP_FS_INSTRLEN: 3
+ 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
@ -2948,7 +2948,7 @@ got cmdszdw=38
!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
!+ 0200fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r0.x | ZWCOORDREGID = r0.z }
!+ 0000fcfc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r63.x }
!+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 00000101 HLSQ_FS_CNTL: { CONSTLEN = 4 | ENABLED }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
0000000100208174: 0000: 70388003 00000d84 00000001 00000006
@ -3570,13 +3570,13 @@ got cmdszdw=38
+ 00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
+ 00000000 SP_VS_PVT_MEM_ADDR: 0
+ 00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_VS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 81100300 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 6 | BRANCHSTACK = 0 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 1001e8580 SP_FS_OBJ_START: 0x1001e8580 base=1001e7000, offset=5504, size=131072
@ -3647,7 +3647,7 @@ got cmdszdw=38
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000003 SP_FS_INSTRLEN: 3
+ 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
@ -3662,7 +3662,7 @@ got cmdszdw=38
+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
+ 0200fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r0.x | ZWCOORDREGID = r0.z }
+ 0000fcfc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r63.x }
+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 00000101 HLSQ_FS_CNTL: { CONSTLEN = 4 | ENABLED }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
000000010020f174: 0000: 70388003 00000d84 00000001 00000006
@ -4295,13 +4295,13 @@ got cmdszdw=38
+ 00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
+ 00000000 SP_VS_PVT_MEM_ADDR: 0
+ 00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_VS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 81100300 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 6 | BRANCHSTACK = 0 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 1001e9a80 SP_FS_OBJ_START: 0x1001e9a80 base=1001e7000, offset=10880, size=131072
@ -4372,7 +4372,7 @@ got cmdszdw=38
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000003 SP_FS_INSTRLEN: 3
+ 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
@ -4387,7 +4387,7 @@ got cmdszdw=38
+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
+ 0200fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r0.x | ZWCOORDREGID = r0.z }
+ 0000fcfc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r63.x }
+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 00000101 HLSQ_FS_CNTL: { CONSTLEN = 4 | ENABLED }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
ESTIMATED CRASH LOCATION!
@ -4945,13 +4945,13 @@ ESTIMATED CRASH LOCATION!
+ 00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
+ 00000000 SP_VS_PVT_MEM_ADDR: 0
+ 00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_VS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 81100300 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 6 | BRANCHSTACK = 0 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 1001eaf80 SP_FS_OBJ_START: 0x1001eaf80 base=1001e7000, offset=16256, size=131072
@ -5023,7 +5023,7 @@ ESTIMATED CRASH LOCATION!
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_FS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000003 SP_FS_INSTRLEN: 3
+ 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
@ -5038,7 +5038,7 @@ ESTIMATED CRASH LOCATION!
+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
+ 0200fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r0.x | ZWCOORDREGID = r0.z }
+ 0000fcfc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r63.x }
+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 00000101 HLSQ_FS_CNTL: { CONSTLEN = 4 | ENABLED }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
000000010021d174: 0000: 70388003 00000d84 00000001 00000006
@ -5169,7 +5169,7 @@ ESTIMATED CRASH LOCATION!
+ 00000001 VFD_ADD_OFFSET: { VERTEX }
+ 00000000 SP_UNKNOWN_A9A8: 0
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000000 SP_IBO_COUNT: 0
+ 00000000 SP_UAV_COUNT: 0
!+ 0000f300 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_16_16_16_16_UNORM | MASK = 0xf }
+ 00000000 SP_DBG_ECO_CNTL: 0
+ 00000430 SP_CHICKEN_BITS: 0x430
@ -5189,7 +5189,7 @@ ESTIMATED CRASH LOCATION!
+ 00108000 TPL1_DBG_ECO_CNTL: 0x108000
+ 00000044 TPL1_UNKNOWN_B605: 68
!+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
+ 00000000 HLSQ_UNKNOWN_BE01: 0
@ -18551,7 +18551,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_VS_PVT_MEM_ADDR: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000001 SP_VS_INSTRLEN: 1
00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -18562,7 +18562,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_PVT_MEM_ADDR: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_HS_INSTRLEN: 0
00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BRANCH_COND: 0
@ -18597,7 +18597,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_DS_PVT_MEM_ADDR: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_DS_INSTRLEN: 0
00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_PRIM_SIZE: 0
@ -18633,7 +18633,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_PVT_MEM_ADDR: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_GS_INSTRLEN: 0
197c98f30815f SP_VS_TEX_SAMP: 0x197c98f30815f
fca982cfc3af SP_HS_TEX_SAMP: 0xfca982cfc3af
@ -18681,7 +18681,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_VS_PVT_MEM_ADDR: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000001 SP_VS_INSTRLEN: 1
00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -18692,7 +18692,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_PVT_MEM_ADDR: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_HS_INSTRLEN: 0
00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BRANCH_COND: 0
@ -18727,7 +18727,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_DS_PVT_MEM_ADDR: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_DS_INSTRLEN: 0
00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_PRIM_SIZE: 0
@ -18763,7 +18763,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_PVT_MEM_ADDR: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_GS_INSTRLEN: 0
197c98f30815f SP_VS_TEX_SAMP: 0x197c98f30815f
fca982cfc3af SP_HS_TEX_SAMP: 0xfca982cfc3af
@ -18802,26 +18802,26 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- cluster-name: CLUSTER_SP_VS
- context: 0
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000003 SP_FS_INSTRLEN: 3
1001a8003 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1001a8000 }
100083003 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100083000 }
100082003 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100082000 }
1d69eb22e8d6b SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1d69eb22e8d68 }
10008f443 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x10008f440 }
10267d210 SP_IBO: 0x10267d210
00000000 SP_IBO_COUNT: 0
10267d210 SP_UAV: 0x10267d210
00000000 SP_UAV_COUNT: 0
- context: 1
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000003 SP_FS_INSTRLEN: 3
1001a8003 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1001a8000 }
100083003 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100083000 }
100082003 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100082000 }
1d69eb22e8d6b SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1d69eb22e8d68 }
10008f443 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x10008f440 }
10267d210 SP_IBO: 0x10267d210
00000000 SP_IBO_COUNT: 0
10267d210 SP_UAV: 0x10267d210
00000000 SP_UAV_COUNT: 0
- cluster-name: CLUSTER_SP_VS
- context: 0
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
@ -18957,7 +18957,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_CS_TEX_COUNT: 128
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_CS_INSTRLEN: 0
00000000 0xa9d0: 00000000
00000000 0xa9d1: 00000000
@ -18972,8 +18972,8 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
1e704e5bf4845 SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x1e704e5bf4844 }
1b92335b570db SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1b92335b570d8 }
138a0c45e43dc SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x138a0c45e43dc }
1146c5000 SP_CS_IBO: 0x1146c5000
00000040 SP_CS_IBO_COUNT: 64
1146c5000 SP_CS_UAV: 0x1146c5000
00000040 SP_CS_UAV_COUNT: 64
00000000 0xaa30: 00000000
00000000 0xaa31: 00000000
- context: 1
@ -19025,7 +19025,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_CS_TEX_COUNT: 128
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_CS_INSTRLEN: 0
00000000 0xa9d0: 00000000
00000000 0xa9d1: 00000000
@ -19040,8 +19040,8 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
1e704e5bf4845 SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x1e704e5bf4844 }
1b92335b570db SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1b92335b570d8 }
138a0c45e43dc SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x138a0c45e43dc }
1146c5000 SP_CS_IBO: 0x1146c5000
00000040 SP_CS_IBO_COUNT: 64
1146c5000 SP_CS_UAV: 0x1146c5000
00000040 SP_CS_UAV_COUNT: 64
00000000 0xaa30: 00000000
00000000 0xaa31: 00000000
- cluster-name: CLUSTER_SP_PS
@ -19113,26 +19113,26 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- cluster-name: CLUSTER_SP_PS
- context: 0
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000003 SP_FS_INSTRLEN: 3
1001a8003 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1001a8000 }
100083003 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100083000 }
100082003 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100082000 }
a112e6e8e914 SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0xa112e6e8e914 }
10008f443 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x10008f440 }
10267d210 SP_IBO: 0x10267d210
00000000 SP_IBO_COUNT: 0
10267d210 SP_UAV: 0x10267d210
00000000 SP_UAV_COUNT: 0
- context: 1
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000003 SP_FS_INSTRLEN: 3
1001a8003 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1001a8000 }
100083003 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100083000 }
100082003 SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x100082000 }
a112e6e8e914 SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0xa112e6e8e914 }
10008f443 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x10008f440 }
10267d210 SP_IBO: 0x10267d210
00000000 SP_IBO_COUNT: 0
10267d210 SP_UAV: 0x10267d210
00000000 SP_UAV_COUNT: 0
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }

38
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -7,7 +7,7 @@ cmdstream[0]: 265 dwords
event CACHE_INVALIDATE
0000000001058000: 0000: 70460001 00000031
write HLSQ_INVALIDATE_CMD (bb08)
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
0000000001058008: 0000: 40bb0801 000fffff
opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001058010: 0000: 70268000
@ -50,8 +50,8 @@ cmdstream[0]: 265 dwords
write SP_CHICKEN_BITS (ae03)
SP_CHICKEN_BITS: 0x410
0000000001058074: 0000: 40ae0301 00000410
write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
write SP_UAV_COUNT (ab20)
SP_UAV_COUNT: 0
000000000105807c: 0000: 48ab2001 00000000
write SP_UNKNOWN_B182 (b182)
SP_UNKNOWN_B182: 0
@ -333,7 +333,7 @@ cmdstream[0]: 265 dwords
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
+ 00000000 SP_UNKNOWN_A9A8: 0
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000000 SP_IBO_COUNT: 0
+ 00000000 SP_UAV_COUNT: 0
!+ 0000f180 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
+ 00000000 SP_DBG_ECO_CNTL: 0
!+ 00000410 SP_CHICKEN_BITS: 0x410
@ -347,7 +347,7 @@ cmdstream[0]: 265 dwords
!+ 00100000 TPL1_DBG_ECO_CNTL: 0x100000
!+ 00000044 TPL1_UNKNOWN_B605: 68
!+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
+ 00000000 HLSQ_UNKNOWN_BE01: 0
@ -758,13 +758,13 @@ cmdstream[0]: 265 dwords
00000000010543c0: 0240: 000000fc 000000fc 48a98b01 0000000f 40880b02 00000000 00000001 40880d01
00000000010543e0: 0260: 0000000f 48809401 00000000 40887001 00000000
write HLSQ_INVALIDATE_CMD (bb08)
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
0000000001054180: 0000: 40bb0801 0000009f
write SP_VS_CTRL_REG0 (a800)
SP_VS_CTRL_REG0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | 0x80000000 }
0000000001054188: 0000: 40a80001 80100180
write SP_VS_CONFIG (a823)
SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
SP_VS_INSTRLEN: 1
0000000001054190: 0000: 48a82302 00000100 00000001
write HLSQ_VS_CNTL (b800)
@ -822,19 +822,19 @@ cmdstream[0]: 265 dwords
00000000010541d0: 0000: 3f800000 00000000 d0d0d0d0 d0d0d0d0
00000000010541c0: 0000: 70320007 00604001 00000000 00000000 3f800000 00000000 d0d0d0d0 d0d0d0d0
write SP_HS_CONFIG (a83b)
SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000010541e0: 0000: 48a83b01 00000000
write HLSQ_HS_CNTL (b801)
HLSQ_HS_CNTL: { CONSTLEN = 0 }
00000000010541e8: 0000: 40b80101 00000000
write SP_DS_CONFIG (a863)
SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000010541f0: 0000: 40a86301 00000000
write HLSQ_DS_CNTL (b802)
HLSQ_DS_CNTL: { CONSTLEN = 0 }
00000000010541f8: 0000: 40b80201 00000000
write SP_GS_CONFIG (a894)
SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
0000000001054200: 0000: 48a89401 00000000
write HLSQ_GS_CNTL (b803)
HLSQ_GS_CNTL: { CONSTLEN = 0 }
@ -843,7 +843,7 @@ cmdstream[0]: 265 dwords
SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | VARYING | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 }
0000000001054210: 0000: 40a98001 81500100
write SP_FS_CONFIG (ab04)
SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
SP_FS_INSTRLEN: 1
0000000001054218: 0000: 48ab0402 00000100 00000001
write HLSQ_FS_CNTL (bb10)
@ -891,7 +891,7 @@ cmdstream[0]: 265 dwords
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
0000000001054238: 0000: 70348003 00720000 01054080 00000000
write SP_CS_CONFIG (a9bb)
SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
0000000001054248: 0000: 48a9bb01 00000000
write HLSQ_CS_CNTL (b987)
HLSQ_CS_CNTL: { CONSTLEN = 0 }
@ -1442,12 +1442,12 @@ cmdstream[0]: 265 dwords
- shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 81500100 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | VARYING | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 }
!+ 01054080 SP_FS_OBJ_START: 0x1054080 base=1054000, offset=128, size=12288
0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
@ -1484,8 +1484,8 @@ cmdstream[0]: 265 dwords
!+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
!+ 00000030 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000001 SP_FS_INSTRLEN: 1
+ 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
@ -1501,7 +1501,7 @@ cmdstream[0]: 265 dwords
!+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
+ 00000000 HLSQ_CS_CNTL: { CONSTLEN = 0 }
!+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 00000100 HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED }
000000000115e394: 0000: 702a000b 00000904 00000007 00000003 01057000 00000000 00000009 01162008
000000000115e3b4: 0020: 00000000 0116300c 00000000 00000028

78
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -7,7 +7,7 @@ cmdstream[0]: 1023 dwords
event CACHE_INVALIDATE
0000000001d91000: 0000: 70460001 00000031
write HLSQ_INVALIDATE_CMD (bb08)
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
0000000001d91008: 0000: 40bb0801 000fffff
opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d91010: 0000: 70268000
@ -47,8 +47,8 @@ cmdstream[0]: 1023 dwords
write SP_CHICKEN_BITS (ae03)
SP_CHICKEN_BITS: 0x1430
0000000001d9106c: 0000: 40ae0301 00001430
write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
write SP_UAV_COUNT (ab20)
SP_UAV_COUNT: 0
0000000001d91074: 0000: 48ab2001 00000000
write SP_UNKNOWN_B182 (b182)
SP_UNKNOWN_B182: 0
@ -543,7 +543,7 @@ cmdstream[0]: 1023 dwords
000000000111f020: 0020: 00000108 48a82301 00000100 48a83b01 00000000 40a86301 00000000 48a89401
000000000111f040: 0040: 00000000 48ab0401 00000100 48ab2001 00000000
write HLSQ_INVALIDATE_CMD (bb08)
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
000000000111f000: 0000: 40bb0801 000000ff
write HLSQ_VS_CNTL (b800)
HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
@ -555,22 +555,22 @@ cmdstream[0]: 1023 dwords
HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
000000000111f01c: 0000: 40bb1001 00000108
write SP_VS_CONFIG (a823)
SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f024: 0000: 48a82301 00000100
write SP_HS_CONFIG (a83b)
SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f02c: 0000: 48a83b01 00000000
write SP_DS_CONFIG (a863)
SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f034: 0000: 40a86301 00000000
write SP_GS_CONFIG (a894)
SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f03c: 0000: 48a89401 00000000
write SP_FS_CONFIG (ab04)
SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f044: 0000: 48ab0401 00000100
write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
write SP_UAV_COUNT (ab20)
SP_UAV_COUNT: 0
000000000111f04c: 0000: 48ab2001 00000000
group_id: 1
count: 192
@ -1076,14 +1076,14 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_PRIM_SIZE: 0
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 81100080 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
+ 00000000 SP_SRGB_CNTL: { 0 }
@ -1101,8 +1101,8 @@ cmdstream[0]: 1023 dwords
!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_UNKNOWN_A9A8: 0
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_IBO_COUNT: 0
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_UAV_COUNT: 0
+ 00000000 SP_DBG_ECO_CNTL: 0
!+ 00001430 SP_CHICKEN_BITS: 0x1430
!+ 00000008 SP_FLOAT_CNTL: { F16_NO_INF }
@ -1126,7 +1126,7 @@ cmdstream[0]: 1023 dwords
!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
!+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
!+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
!+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
@ -1822,7 +1822,7 @@ cmdstream[0]: 1023 dwords
000000000111f020: 0020: 00000108 48a82301 00000100 48a83b01 00000000 40a86301 00000000 48a89401
000000000111f040: 0040: 00000000 48ab0401 00000100 48ab2001 00000000
write HLSQ_INVALIDATE_CMD (bb08)
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
000000000111f000: 0000: 40bb0801 000000ff
write HLSQ_VS_CNTL (b800)
HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
@ -1834,22 +1834,22 @@ cmdstream[0]: 1023 dwords
HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
000000000111f01c: 0000: 40bb1001 00000108
write SP_VS_CONFIG (a823)
SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f024: 0000: 48a82301 00000100
write SP_HS_CONFIG (a83b)
SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f02c: 0000: 48a83b01 00000000
write SP_DS_CONFIG (a863)
SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f034: 0000: 40a86301 00000000
write SP_GS_CONFIG (a894)
SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f03c: 0000: 48a89401 00000000
write SP_FS_CONFIG (ab04)
SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
000000000111f044: 0000: 48ab0401 00000100
write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
write SP_UAV_COUNT (ab20)
SP_UAV_COUNT: 0
000000000111f04c: 0000: 48ab2001 00000000
group_id: 1
count: 192
@ -5018,15 +5018,15 @@ cmdstream[0]: 1023 dwords
00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000 48ab1a02 011160a0 00000000 48ab2001
*
opcode: CP_LOAD_STATE6 (36) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_IBO | NUM_UNIT = 0 }
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_UAV | NUM_UNIT = 0 }
{ EXT_SRC_ADDR = 0x11160a0 }
{ EXT_SRC_ADDR_HI = 0 }
00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000
write SP_IBO (ab1a)
SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
write SP_UAV (ab1a)
SP_UAV: 0x11160a0 base=1116000, offset=160, size=388
00000000011160b0: 0000: 48ab1a02 011160a0 00000000
write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
write SP_UAV_COUNT (ab20)
SP_UAV_COUNT: 0
00000000011160bc: 0000: 48ab2001 00000000
group_id: 21
count: 14
@ -5270,14 +5270,14 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_PRIM_SIZE: 0
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 81508980 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | VARYING | INOUTREGOVERLAP | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 01013000 SP_FS_OBJ_START: 0x1013000 base=1013000, offset=0, size=11264
@ -6718,10 +6718,10 @@ cmdstream[0]: 1023 dwords
+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | CONSTSLOTID = 511 }
+ 00000000 SP_UNKNOWN_A9A8: 0
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000058 SP_FS_INSTRLEN: 88
!+ 011160a0 SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
+ 00000000 SP_IBO_COUNT: 0
!+ 011160a0 SP_UAV: 0x11160a0 base=1116000, offset=160, size=388
+ 00000000 SP_UAV_COUNT: 0
+ 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
+ 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 }
+ 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 }
@ -6732,7 +6732,7 @@ cmdstream[0]: 1023 dwords
+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
!+ 1513fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y }
+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
+ 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED }
0000000001d8f130: 0000: 70388003 00000186 00000001 00000004
opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)

70
src/freedreno/.gitlab-ci/reference/prefetch-test.log
View file

@ -2595,7 +2595,7 @@ got cmdszdw=416
+ 00000000 VFD_FETCH[0x1e].SIZE: 0
+ 00000000 VFD_FETCH[0x1f].SIZE: 0
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000000 SP_IBO_COUNT: 0
+ 00000000 SP_UAV_COUNT: 0
!+ 0000f180 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
+ 00000000 SP_DBG_ECO_CNTL: 0
!+ 00001430 SP_CHICKEN_BITS: 0x1430
@ -2610,7 +2610,7 @@ got cmdszdw=416
!+ 00108000 TPL1_DBG_ECO_CNTL: 0x108000
!+ 00000044 TPL1_UNKNOWN_B605: 68
!+ 000000fc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r0.x }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
!+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
+ 00000000 HLSQ_UNKNOWN_BE01: 0
@ -3185,14 +3185,14 @@ got cmdszdw=416
+ 00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
+ 00000000 SP_VS_PVT_MEM_ADDR: 0
+ 00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 00000003 SP_VS_INSTRLEN: 3
+ 00000000 SP_VS_PVT_MEM_HW_STACK_OFFSET: { OFFSET = 0 }
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
+ 00000000 SP_GS_PRIM_SIZE: 0
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
!+ 85508180 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | VARYING | INOUTREGOVERLAP | PIXLODENABLE | MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 2 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 10372c000 SP_FS_OBJ_START: 0x10372c000 base=10372c000, offset=0, size=4096
@ -3268,9 +3268,9 @@ got cmdszdw=416
00000001000092c0: 00c0: 48882101 00000000 40882001 000007e0 40880e01 00000000 40a98901 00000100
00000001000092e0: 00e0: 48886501 ffff0000 00000000 00000000 00000000 00000000 00000000 00000000
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
!+ 00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NIBO = 0 }
!+ 00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NUAV = 0 }
!+ 00000002 SP_FS_INSTRLEN: 2
+ 00000000 SP_IBO_COUNT: 0
+ 00000000 SP_UAV_COUNT: 0
+ 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
!+ 00000102 HLSQ_VS_CNTL: { CONSTLEN = 8 | ENABLED }
@ -3283,7 +3283,7 @@ got cmdszdw=416
!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
!+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
!+ 0000fcfc HLSQ_CONTROL_5_REG: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r63.x }
!+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_UAV | GFX_UAV | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
!+ 00000102 HLSQ_FS_CNTL: { CONSTLEN = 8 | ENABLED }
0000000103cd2120: 0000: 70380007 00000504 00000001 00000006 00000000 03730000 00000001 00000006
opcode: CP_SET_DRAW_STATE (43) (4 dwords)
@ -152546,7 +152546,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_VS_PVT_MEM_ADDR: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000003 SP_VS_INSTRLEN: 3
00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -152557,7 +152557,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_PVT_MEM_ADDR: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_HS_INSTRLEN: 0
00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BRANCH_COND: 0
@ -152592,7 +152592,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_DS_PVT_MEM_ADDR: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_DS_INSTRLEN: 0
00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_PRIM_SIZE: 0
@ -152628,7 +152628,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_PVT_MEM_ADDR: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_GS_INSTRLEN: 0
f07f59c1423 SP_VS_TEX_SAMP: 0xf07f59c1423
155398b7c6e7b SP_HS_TEX_SAMP: 0x155398b7c6e7b
@ -152676,7 +152676,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_VS_PVT_MEM_ADDR: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000003 SP_VS_INSTRLEN: 3
00000000 SP_HS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -152687,7 +152687,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_PVT_MEM_ADDR: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_HS_INSTRLEN: 0
00000000 SP_DS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BRANCH_COND: 0
@ -152722,7 +152722,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_DS_PVT_MEM_ADDR: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_DS_INSTRLEN: 0
00000000 SP_GS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_PRIM_SIZE: 0
@ -152758,7 +152758,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_PVT_MEM_ADDR: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_GS_INSTRLEN: 0
f07f59c1423 SP_VS_TEX_SAMP: 0xf07f59c1423
155398b7c6e7b SP_HS_TEX_SAMP: 0x155398b7c6e7b
@ -152797,26 +152797,26 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- cluster-name: CLUSTER_SP_VS
- context: 0
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NIBO = 0 }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NUAV = 0 }
00000002 SP_FS_INSTRLEN: 2
f7fd9401 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0xf7fd9400 }
13f90355fa4bf SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x13f90355fa4bc }
539cf42f181d SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x539cf42f181c }
1fe1abdd85a5b SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1fe1abdd85a58 }
16579f3ebef2d SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x16579f3ebef2c }
1009b10f0 SP_IBO: 0x1009b10f0
00000000 SP_IBO_COUNT: 0
1009b10f0 SP_UAV: 0x1009b10f0
00000000 SP_UAV_COUNT: 0
- context: 1
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NIBO = 0 }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NUAV = 0 }
00000002 SP_FS_INSTRLEN: 2
f7fd9401 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0xf7fd9400 }
13f90355fa4bf SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x13f90355fa4bc }
539cf42f181d SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x539cf42f181c }
1fe1abdd85a5b SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1fe1abdd85a58 }
16579f3ebef2d SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0x16579f3ebef2c }
1009b10f0 SP_IBO: 0x1009b10f0
00000000 SP_IBO_COUNT: 0
1009b10f0 SP_UAV: 0x1009b10f0
00000000 SP_UAV_COUNT: 0
- cluster-name: CLUSTER_SP_VS
- context: 0
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
@ -152952,7 +152952,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_CS_TEX_COUNT: 128
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_CS_INSTRLEN: 0
00000000 0xa9d0: 00000000
00000000 0xa9d1: 00000000
@ -152967,8 +152967,8 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
1bbb971f39d18 SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x1bbb971f39d18 }
10a708bd04366 SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x10a708bd04364 }
724d84c0227 SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x724d84c0224 }
11c34de54789b SP_CS_IBO: 0x11c34de54789b
00000040 SP_CS_IBO_COUNT: 64
11c34de54789b SP_CS_UAV: 0x11c34de54789b
00000040 SP_CS_UAV_COUNT: 64
00000000 0xaa30: 00000000
00000000 0xaa31: 00000000
- context: 1
@ -153020,7 +153020,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_CS_TEX_COUNT: 128
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NUAV = 0 }
00000000 SP_CS_INSTRLEN: 0
00000000 0xa9d0: 00000000
00000000 0xa9d1: 00000000
@ -153035,8 +153035,8 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
1bbb971f39d18 SP_CS_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x1bbb971f39d18 }
10a708bd04366 SP_CS_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x10a708bd04364 }
724d84c0227 SP_CS_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x724d84c0224 }
11c34de54789b SP_CS_IBO: 0x11c34de54789b
00000040 SP_CS_IBO_COUNT: 64
11c34de54789b SP_CS_UAV: 0x11c34de54789b
00000040 SP_CS_UAV_COUNT: 64
00000000 0xaa30: 00000000
00000000 0xaa31: 00000000
- cluster-name: CLUSTER_SP_PS
@ -153108,26 +153108,26 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- cluster-name: CLUSTER_SP_PS
- context: 0
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NIBO = 0 }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NUAV = 0 }
00000002 SP_FS_INSTRLEN: 2
212162ab1452 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x212162ab1450 }
1aaf2a3ff6b43 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1aaf2a3ff6b40 }
398bb57c11a SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x398bb57c118 }
ab1f39f102f9 SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0xab1f39f102f8 }
15bf2be973248 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x15bf2be973248 }
1009b10f0 SP_IBO: 0x1009b10f0
00000000 SP_IBO_COUNT: 0
1009b10f0 SP_UAV: 0x1009b10f0
00000000 SP_UAV_COUNT: 0
- context: 1
00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NIBO = 0 }
00020300 SP_FS_CONFIG: { ENABLED | NTEX = 1 | NSAMP = 1 | NUAV = 0 }
00000002 SP_FS_INSTRLEN: 2
212162ab1452 SP_BINDLESS_BASE[0].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x212162ab1450 }
1aaf2a3ff6b43 SP_BINDLESS_BASE[0x1].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_64B | ADDR = 0x1aaf2a3ff6b40 }
398bb57c11a SP_BINDLESS_BASE[0x2].DESCRIPTOR: { DESC_SIZE = 0x2 | ADDR = 0x398bb57c118 }
ab1f39f102f9 SP_BINDLESS_BASE[0x3].DESCRIPTOR: { DESC_SIZE = BINDLESS_DESCRIPTOR_16B | ADDR = 0xab1f39f102f8 }
15bf2be973248 SP_BINDLESS_BASE[0x4].DESCRIPTOR: { DESC_SIZE = 0 | ADDR = 0x15bf2be973248 }
1009b10f0 SP_IBO: 0x1009b10f0
00000000 SP_IBO_COUNT: 0
1009b10f0 SP_UAV: 0x1009b10f0
00000000 SP_UAV_COUNT: 0
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }

8
src/freedreno/common/freedreno_dev_info.h
View file

@ -280,11 +280,11 @@ struct fd_dev_info {
uint32_t sysmem_vpc_attr_buf_size;
uint32_t gmem_vpc_attr_buf_size;
/* Whether UBWC is supported on all IBOs. Prior to this, only readonly
* or writeonly IBOs could use UBWC and mixing reads and writes was not
/* Whether UBWC is supported on all UAVs. Prior to this, only readonly
* or writeonly UAVs could use UBWC and mixing reads and writes was not
* permitted.
*/
bool supports_ibo_ubwc;
bool supports_uav_ubwc;
/* Whether the UBWC fast-clear values for snorn, unorm, and int formats
* are the same. This is the case from a740 onwards. These formats were
@ -329,7 +329,7 @@ struct fd_dev_info {
/* Whether r8g8 UBWC fast-clear work correctly. */
bool r8g8_faulty_fast_clear_quirk;
/* a750 has a bug where writing and then reading a UBWC-compressed IBO
/* a750 has a bug where writing and then reading a UBWC-compressed UAV
* requires flushing UCHE. This is reproducible in many CTS tests, for
* example dEQP-VK.image.load_store.with_format.2d.*.
*/

6
src/freedreno/common/freedreno_devices.py
View file

@ -924,7 +924,7 @@ a7xx_base = A6XXProps(
)
a7xx_gen1 = A7XXProps(
supports_ibo_ubwc = True,
supports_uav_ubwc = True,
fs_must_have_non_zero_constlen_quirk = True,
enable_tp_ubwc_flag_hint = True,
reading_shading_rate_requires_smask_quirk = True,
@ -934,7 +934,7 @@ a7xx_gen2 = A7XXProps(
stsc_duplication_quirk = True,
has_event_write_sample_count = True,
ubwc_unorm_snorm_int_compatible = True,
supports_ibo_ubwc = True,
supports_uav_ubwc = True,
fs_must_have_non_zero_constlen_quirk = True,
# Most devices with a740 have blob v6xx which doesn't have
# this hint set. Match them for better compatibility by default.
@ -953,7 +953,7 @@ a7xx_gen3 = A7XXProps(
sysmem_vpc_attr_buf_size = 0x20000,
gmem_vpc_attr_buf_size = 0xc000,
ubwc_unorm_snorm_int_compatible = True,
supports_ibo_ubwc = True,
supports_uav_ubwc = True,
has_generic_clear = True,
r8g8_faulty_fast_clear_quirk = True,
gs_vpc_adjacency_quirk = True,

12
src/freedreno/computerator/a6xx.cc
View file

@ -149,7 +149,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
.gs_state = true,
.fs_state = true,
.cs_state = true,
.gfx_ibo = true,
.gfx_uav = true,
));
unsigned constlen = align(v->constlen, 4);
@ -157,7 +157,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
A6XX_SP_CS_CONFIG_NIBO(kernel->num_bufs) |
A6XX_SP_CS_CONFIG_NUAV(kernel->num_bufs) |
A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_VS_CONFIG */
OUT_RING(ring, v->instrlen); /* SP_VS_INSTRLEN */
@ -395,20 +395,20 @@ cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_UAV) |
CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
CP_LOAD_STATE6_0_NUM_UNIT(kernel->num_bufs));
OUT_RB(ring, state);
if (CHIP == A6XX) {
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_UAV, 2);
} else {
OUT_PKT4(ring, REG_A7XX_SP_CS_IBO, 2);
OUT_PKT4(ring, REG_A7XX_SP_CS_UAV, 2);
}
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
OUT_PKT4(ring, REG_A6XX_SP_CS_UAV_COUNT, 1);
OUT_RING(ring, kernel->num_bufs);
fd_ringbuffer_del(state);

2
src/freedreno/ir3/ir3.c
View file

@ -1804,7 +1804,7 @@ ir3_valid_flags(struct ir3_instruction *instr, unsigned n, unsigned flags)
return false;
/* as with atomics, these cat6 instrs can only have an immediate
* for SSBO/IBO slot argument
* for SSBO/UAV slot argument
*/
switch (instr->opc) {
case OPC_LDIB:

10
src/freedreno/ir3/ir3_image.c
View file

@ -9,13 +9,13 @@
#include "ir3_image.h"
/*
* SSBO/Image to/from IBO/tex hw mapping table:
* SSBO/Image to/from UAV/tex hw mapping table:
*/
void
ir3_ibo_mapping_init(struct ir3_ibo_mapping *mapping, unsigned num_textures)
{
memset(mapping, IBO_INVALID, sizeof(*mapping));
memset(mapping, UAV_INVALID, sizeof(*mapping));
mapping->num_tex = 0;
mapping->tex_base = num_textures;
}
@ -31,10 +31,10 @@ ir3_ssbo_to_ibo(struct ir3_context *ctx, nir_src src)
unsigned
ir3_ssbo_to_tex(struct ir3_ibo_mapping *mapping, unsigned ssbo)
{
if (mapping->ssbo_to_tex[ssbo] == IBO_INVALID) {
if (mapping->ssbo_to_tex[ssbo] == UAV_INVALID) {
unsigned tex = mapping->num_tex++;
mapping->ssbo_to_tex[ssbo] = tex;
mapping->tex_to_image[tex] = IBO_SSBO | ssbo;
mapping->tex_to_image[tex] = UAV_SSBO | ssbo;
}
return mapping->ssbo_to_tex[ssbo] + mapping->tex_base;
}
@ -64,7 +64,7 @@ ir3_image_to_ibo(struct ir3_context *ctx, nir_src src)
unsigned
ir3_image_to_tex(struct ir3_ibo_mapping *mapping, unsigned image)
{
if (mapping->image_to_tex[image] == IBO_INVALID) {
if (mapping->image_to_tex[image] == UAV_INVALID) {
unsigned tex = mapping->num_tex++;
mapping->image_to_tex[image] = tex;
mapping->tex_to_image[tex] = image;

2
src/freedreno/ir3/ir3_nir.c
View file

@ -951,7 +951,7 @@ ir3_nir_post_finalize(struct ir3_shader *shader)
OPT(s, ir3_nir_lower_ssbo_size, 2);
/* The resinfo opcode we have for getting the SSBO size on a6xx returns a
* byte length divided by IBO_0_FMT, while the NIR intrinsic coming in is a
* byte length divided by UAV_0_FMT, while the NIR intrinsic coming in is a
* number of bytes. Switch things so the NIR intrinsic in our backend means
* dwords.
*/

2
src/freedreno/ir3/ir3_shader.c
View file

@ -549,7 +549,7 @@ alloc_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
}
v->num_ssbos = info->num_ssbos;
v->num_ibos = info->num_ssbos + info->num_images;
v->num_uavs = info->num_ssbos + info->num_images;
v->shader_options = shader->options;
if (!v->binning_pass) {

18
src/freedreno/ir3/ir3_shader.h
View file

@ -543,10 +543,10 @@ ir3_shader_key_changes_vs(struct ir3_shader_key *key,
* mapping table to remap things from image/SSBO idx to hw idx.
*
* To make things less (more?) confusing, for the hw "SSBO" state
* (since it is really both SSBO and Image) I'll use the name "IBO"
* (since it is really both SSBO and Image) I'll use the name "UAV"
*/
struct ir3_ibo_mapping {
#define IBO_INVALID 0xff
#define UAV_INVALID 0xff
/* Maps logical SSBO state to hw tex state: */
uint8_t ssbo_to_tex[IR3_MAX_SHADER_BUFFERS];
@ -555,10 +555,10 @@ struct ir3_ibo_mapping {
/* Maps hw state back to logical SSBO or Image state:
*
* note IBO_SSBO ORd into values to indicate that the
* note UAV_SSBO ORd into values to indicate that the
* hw slot is used for SSBO state vs Image state.
*/
#define IBO_SSBO 0x80
#define UAV_SSBO 0x80
uint8_t tex_to_image[32];
/* including real textures */
@ -893,11 +893,11 @@ struct ir3_shader_variant {
/* Important for compute shader to determine max reg footprint */
bool has_barrier;
/* The offset where images start in the IBO array. */
/* The offset where images start in the UAV array. */
unsigned num_ssbos;
/* The total number of SSBOs and images, i.e. the number of hardware IBOs. */
unsigned num_ibos;
/* The total number of SSBOs and images, i.e. the number of hardware UAVs. */
unsigned num_uavs;
union {
struct {
@ -1428,9 +1428,9 @@ ir3_shader_halfregs(const struct ir3_shader_variant *v)
}
static inline uint32_t
ir3_shader_nibo(const struct ir3_shader_variant *v)
ir3_shader_num_uavs(const struct ir3_shader_variant *v)
{
return v->num_ibos;
return v->num_uavs;
}
static inline uint32_t

2
src/freedreno/isa/ir3-cat6.xml
View file

@ -1293,7 +1293,7 @@ SOFTWARE.
<bitset name="#instruction-cat6-a6xx-ibo-base" extends="#instruction-cat6-a6xx-base">
<doc>
IBO (ie. Image/SSBO) instructions
UAV (ie. Image/SSBO) instructions
</doc>
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.{MODE}{BASE} {TYPE_HALF}{SRC1}, {SRC2}{OFFSET}, {SSBO}

32
src/freedreno/registers/adreno/a6xx.xml
View file

@ -4664,7 +4664,7 @@ to upconvert to 32b float internally?
-->
<bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
<bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
<bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
<bitfield name="BINDLESS_UAV" pos="2" type="boolean"/>
<bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
<bitfield name="ENABLED" pos="8" type="boolean"/>
@ -4674,7 +4674,7 @@ to upconvert to 32b float internally?
-->
<bitfield name="NTEX" low="9" high="16" type="uint"/>
<bitfield name="NSAMP" low="17" high="21" type="uint"/>
<bitfield name="NIBO" low="22" high="28" type="uint"/>
<bitfield name="NUAV" low="22" high="28" type="uint"/>
</bitset>
<bitset name="a6xx_sp_xs_prim_cntl" inline="yes">
@ -5210,11 +5210,11 @@ to upconvert to 32b float internally?
</array>
<!--
IBO state for compute shader:
UAV state for compute shader:
-->
<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16" variants="A6XX"/>
<reg64 offset="0xa9f8" name="SP_CS_IBO" type="address" align="16" variants="A7XX"/>
<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
<reg64 offset="0xa9f2" name="SP_CS_UAV" type="address" align="16" variants="A6XX"/>
<reg64 offset="0xa9f8" name="SP_CS_UAV" type="address" align="16" variants="A7XX"/>
<reg32 offset="0xaa00" name="SP_CS_UAV_COUNT" low="0" high="6" type="uint"/>
<!-- Correlated with avgs/uvgs usage in FS -->
<reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
@ -5292,11 +5292,11 @@ to upconvert to 32b float internally?
</array>
<!--
Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
Combined UAV state for 3d pipe, used for Image and SSBO write/atomic
instructions VS/HS/DS/GS/FS. See SP_CS_UAV_* for compute shaders.
-->
<reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/>
<reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/>
<reg64 offset="0xab1a" name="SP_UAV" type="address" align="16" usage="cmd"/>
<reg32 offset="0xab20" name="SP_UAV_COUNT" low="0" high="6" type="uint" usage="cmd"/>
<reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
@ -5781,8 +5781,8 @@ to upconvert to 32b float internally?
<bitfield name="FS_STATE" pos="4" type="boolean"/>
<bitfield name="CS_STATE" pos="5" type="boolean"/>
<bitfield name="CS_IBO" pos="6" type="boolean"/>
<bitfield name="GFX_IBO" pos="7" type="boolean"/>
<bitfield name="CS_UAV" pos="6" type="boolean"/>
<bitfield name="GFX_UAV" pos="7" type="boolean"/>
<!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
<bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
@ -5821,8 +5821,8 @@ to upconvert to 32b float internally?
<bitfield name="FS_STATE" pos="4" type="boolean"/>
<bitfield name="CS_STATE" pos="5" type="boolean"/>
<bitfield name="CS_IBO" pos="6" type="boolean"/>
<bitfield name="GFX_IBO" pos="7" type="boolean"/>
<bitfield name="CS_UAV" pos="6" type="boolean"/>
<bitfield name="GFX_UAV" pos="7" type="boolean"/>
<!-- SS6_BINDLESS: one bit per bindless base -->
<bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/>
@ -5841,7 +5841,7 @@ to upconvert to 32b float internally?
const pool and 16 in the geometry const pool although
only 8 are actually used (why?) and they are mapped to
c504-c511 in each stage. Both VS and FS shared consts
are written using ST6_CONSTANTS/SB6_IBO, so that both
are written using ST6_CONSTANTS/SB6_UAV, so that both
the geometry and FS shared consts can be written at once
by using CP_LOAD_STATE6 rather than
CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition
@ -5850,7 +5850,7 @@ to upconvert to 32b float internally?
There is also a separate shared constant pool for CS,
which is loaded through CP_LOAD_STATE6_FRAG with
ST6_UBO/ST6_IBO. However the only real difference for CS
ST6_UBO/ST6_UAV. However the only real difference for CS
is the dword units.
</doc>
<bitfield name="ENABLE" pos="0" type="boolean"/>

8
src/freedreno/registers/adreno/adreno_pm4.xml
View file

@ -546,7 +546,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
<value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
<!--
Note: For IBO state (Image/SSBOs) which have shared state across
Note: For UAV state (Image/SSBOs) which have shared state across
shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
interchangable.
@ -805,14 +805,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<value name="SB6_GS_SHADER" value="0xb"/>
<value name="SB6_FS_SHADER" value="0xc"/>
<value name="SB6_CS_SHADER" value="0xd"/>
<value name="SB6_IBO" value="0xe"/>
<value name="SB6_CS_IBO" value="0xf"/>
<value name="SB6_UAV" value="0xe"/>
<value name="SB6_CS_UAV" value="0xf"/>
</enum>
<enum name="a6xx_state_type">
<value name="ST6_SHADER" value="0"/>
<value name="ST6_CONSTANTS" value="1"/>
<value name="ST6_UBO" value="2"/>
<value name="ST6_IBO" value="3"/>
<value name="ST6_UAV" value="3"/>
</enum>
<enum name="a6xx_state_src">
<value name="SS6_DIRECT" value="0"/>

2
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -902,7 +902,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
.ds_state = true,
.gs_state = true,
.fs_state = true,
.gfx_ibo = true,
.gfx_uav = true,
.gfx_shared_const = true,
.cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
.gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,));

8
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -1622,7 +1622,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
}
tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS,
phys_dev->info->a6xx.magic.SP_CHICKEN_BITS);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0); // 2 on a740 ???
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UAV_COUNT, 0); // 2 on a740 ???
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
if (CHIP == A6XX)
tu_cs_emit_regs(cs, A6XX_HLSQ_SHARED_CONSTS(.enable = false));
@ -1839,8 +1839,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
.gs_state = true,
.fs_state = true,
.cs_state = true,
.cs_ibo = true,
.gfx_ibo = true,
.cs_uav = true,
.gfx_uav = true,
.cs_shared_const = true,
.gfx_shared_const = true,
.cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
@ -6089,7 +6089,7 @@ tu6_emit_shared_consts(struct tu_cs *cs,
tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
CP_LOAD_STATE6_0_STATE_TYPE(st) |
CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
CP_LOAD_STATE6_0_STATE_BLOCK(SB6_UAV) |
CP_LOAD_STATE6_0_NUM_UNIT(num_units));
tu_cs_emit(cs, 0);
tu_cs_emit(cs, 0);

4
src/freedreno/vulkan/tu_device.cc
View file

@ -2422,7 +2422,7 @@ tu_init_cmdbuf_start_a725_quirk(struct tu_device *device)
tu_cs_emit_regs(&sub_cs, HLSQ_INVALIDATE_CMD(A7XX,
.vs_state = true, .hs_state = true, .ds_state = true,
.gs_state = true, .fs_state = true, .gfx_ibo = true,
.gs_state = true, .fs_state = true, .gfx_uav = true,
.cs_bindless = 0xff, .gfx_bindless = 0xff));
tu_cs_emit_regs(&sub_cs, HLSQ_CS_CNTL(A7XX,
.constlen = 4,
@ -2438,7 +2438,7 @@ tu_init_cmdbuf_start_a725_quirk(struct tu_device *device)
HLSQ_CS_KERNEL_GROUP_Z(A7XX, 1));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_INSTRLEN(.sp_cs_instrlen = 1));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_TEX_COUNT(0));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_IBO_COUNT(0));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_UAV_COUNT(0));
tu_cs_emit_regs(&sub_cs, HLSQ_CS_CNTL_1(A7XX,
.linearlocalidregid = regid(63, 0),
.threadsize = THREAD128,

2
src/freedreno/vulkan/tu_image.cc
View file

@ -385,7 +385,7 @@ ubwc_possible(struct tu_device *device,
* and we can't change the descriptor so we can't do this.
*/
if (((usage | stencil_usage) & VK_IMAGE_USAGE_STORAGE_BIT) &&
!info->a7xx.supports_ibo_ubwc) {
!info->a7xx.supports_uav_ubwc) {
return false;
}

12
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -81,7 +81,7 @@ tu6_load_state_size(struct tu_pipeline *pipeline,
case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
case VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_KHR:
/* IBO-backed resources only need one packet for all graphics stages */
/* UAV-backed resources only need one packet for all graphics stages */
if (stage_count)
count += 1;
break;
@ -179,13 +179,13 @@ tu6_emit_load_state(struct tu_device *device,
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
case VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_KHR: {
unsigned mul = binding->size / (A6XX_TEX_CONST_DWORDS * 4);
/* IBO-backed resources only need one packet for all graphics stages */
/* UAV-backed resources only need one packet for all graphics stages */
if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_UAV,
base, offset, count * mul);
}
if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_UAV, SB6_CS_SHADER,
base, offset, count * mul);
}
break;
@ -392,7 +392,7 @@ tu6_emit_xs_config(struct tu_cs *cs,
tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_UAV) |
COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
@ -1287,7 +1287,7 @@ tu6_emit_program_config(struct tu_cs *cs,
.ds_state = true,
.gs_state = true,
.fs_state = true,
.gfx_ibo = true,
.gfx_uav = true,
.gfx_shared_const = shared_consts_enable));
for (size_t stage_idx = MESA_SHADER_VERTEX;
stage_idx <= MESA_SHADER_FRAGMENT; stage_idx++) {

2
src/freedreno/vulkan/tu_shader.cc
View file

@ -1526,7 +1526,7 @@ tu6_emit_cs_config(struct tu_cs *cs,
tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
.cs_state = true,
.cs_ibo = true,
.cs_uav = true,
.cs_shared_const = shared_consts_enable));
tu6_emit_xs_config<CHIP>(cs, MESA_SHADER_COMPUTE, v);

2
src/gallium/drivers/freedreno/a4xx/fd4_image.c
View file

@ -227,7 +227,7 @@ fd4_emit_images(struct fd_context *ctx, struct fd_ringbuffer *ring,
translate_image(&img, &so->si[index]);
if (m->image_to_tex[index] != IBO_INVALID)
if (m->image_to_tex[index] != UAV_INVALID)
emit_image_tex(ring, m->image_to_tex[index] + m->tex_base, &img, shader);
emit_image_ssbo(ring, v->num_ssbos + index, &img, shader);
}

2
src/gallium/drivers/freedreno/a5xx/fd5_image.c
View file

@ -207,7 +207,7 @@ fd5_emit_images(struct fd_context *ctx, struct fd_ringbuffer *ring,
translate_image(&img, &so->si[index]);
if (m->image_to_tex[index] != IBO_INVALID)
if (m->image_to_tex[index] != UAV_INVALID)
emit_image_tex(ring, m->image_to_tex[index] + m->tex_base, &img, shader);
emit_image_ssbo(ring, v->num_ssbos + index, &img,
shader);

6
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
View file

@ -73,7 +73,7 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
.ds_state = true, .gs_state = true,
.fs_state = true, .cs_state = true,
.cs_ibo = true, .gfx_ibo = true, ));
.cs_uav = true, .gfx_uav = true, ));
OUT_REG(ring, HLSQ_CS_CNTL(
CHIP,
@ -85,9 +85,9 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
COND(v->bindless_tex, A6XX_SP_CS_CONFIG_BINDLESS_TEX) |
COND(v->bindless_samp, A6XX_SP_CS_CONFIG_BINDLESS_SAMP) |
COND(v->bindless_ibo, A6XX_SP_CS_CONFIG_BINDLESS_IBO) |
COND(v->bindless_ibo, A6XX_SP_CS_CONFIG_BINDLESS_UAV) |
COND(v->bindless_ubo, A6XX_SP_CS_CONFIG_BINDLESS_UBO) |
A6XX_SP_CS_CONFIG_NIBO(ir3_shader_nibo(v)) |
A6XX_SP_CS_CONFIG_NUAV(ir3_shader_num_uavs(v)) |
A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_CS_CONFIG */

4
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -913,7 +913,7 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
if (CHIP == A6XX)
WRITE(REG_A6XX_HLSQ_DBG_ECO_CNTL, screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL);
WRITE(REG_A6XX_SP_CHICKEN_BITS, screen->info->a6xx.magic.SP_CHICKEN_BITS);
WRITE(REG_A6XX_SP_IBO_COUNT, 0);
WRITE(REG_A6XX_SP_UAV_COUNT, 0);
WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
if (CHIP == A6XX)
WRITE(REG_A6XX_HLSQ_SHARED_CONSTS, 0);
@ -1130,7 +1130,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
.vs_state = true, .hs_state = true,
.ds_state = true, .gs_state = true,
.fs_state = true, .cs_state = true,
.cs_ibo = true, .gfx_ibo = true,
.cs_uav = true, .gfx_uav = true,
.cs_shared_const = true,
.gfx_shared_const = true,
.cs_bindless = CHIP == A6XX ? 0x1f : 0xff,

12
src/gallium/drivers/freedreno/a6xx/fd6_image.cc
View file

@ -140,7 +140,7 @@ clear_descriptor(struct fd6_descriptor_set *set, unsigned slot)
/* The 2nd dword of the descriptor contains the width and height.
* so a non-zero value means the slot was previously valid and
* must be cleared. We can't leave dangling descriptors as the
* shader could use variable indexing into the set of IBOs to
* shader could use variable indexing into the set of UAVs to
* get at them. See piglit arb_shader_image_load_store-invalid.
*/
if (!set->descriptor[slot][1])
@ -261,7 +261,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
* set and CP_LOAD_STATE packets to preload the state.
*
* Note that unless the app is using the max # of SSBOs there will
* be a gap between the IBO descriptors used for SSBOs and for images,
* be a gap between the UAV descriptors used for SSBOs and for images,
* so emit this as two CP_LOAD_STATE packets:
*/
@ -290,7 +290,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
OUT_PKT(ring, CP_LOAD_STATE6_FRAG,
CP_LOAD_STATE6_0(
.dst_off = IR3_BINDLESS_SSBO_OFFSET,
.state_type = ST6_IBO,
.state_type = ST6_UAV,
.state_src = SS6_BINDLESS,
.state_block = SB6_CS_SHADER,
.num_unit = util_last_bit(bufso->enabled_mask),
@ -307,7 +307,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
OUT_PKT(ring, CP_LOAD_STATE6_FRAG,
CP_LOAD_STATE6_0(
.dst_off = IR3_BINDLESS_IMAGE_OFFSET,
.state_type = ST6_IBO,
.state_type = ST6_UAV,
.state_src = SS6_BINDLESS,
.state_block = SB6_CS_SHADER,
.num_unit = util_last_bit(imgso->enabled_mask),
@ -341,7 +341,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
.dst_off = IR3_BINDLESS_SSBO_OFFSET,
.state_type = ST6_SHADER,
.state_src = SS6_BINDLESS,
.state_block = SB6_IBO,
.state_block = SB6_UAV,
.num_unit = util_last_bit(bufso->enabled_mask),
),
CP_LOAD_STATE6_EXT_SRC_ADDR(
@ -358,7 +358,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
.dst_off = IR3_BINDLESS_IMAGE_OFFSET,
.state_type = ST6_SHADER,
.state_src = SS6_BINDLESS,
.state_block = SB6_IBO,
.state_block = SB6_UAV,
.num_unit = util_last_bit(imgso->enabled_mask),
),
CP_LOAD_STATE6_EXT_SRC_ADDR(

10
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -389,9 +389,9 @@ sp_xs_config(const struct ir3_shader_variant *v)
return A6XX_SP_VS_CONFIG_ENABLED |
COND(v->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
COND(v->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
COND(v->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
COND(v->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_UAV) |
COND(v->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(v)) |
A6XX_SP_VS_CONFIG_NUAV(ir3_shader_num_uavs(v)) |
A6XX_SP_VS_CONFIG_NTEX(v->num_samp) |
A6XX_SP_VS_CONFIG_NSAMP(v->num_samp);
}
@ -405,7 +405,7 @@ setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
.ds_state = true, .gs_state = true,
.fs_state = true, .cs_state = true,
.cs_ibo = true, .gfx_ibo = true, ));
.cs_uav = true, .gfx_uav = true, ));
assert(state->vs->constlen >= state->bs->constlen);
@ -450,8 +450,8 @@ setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
OUT_RING(ring, sp_xs_config(state->fs));
OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
OUT_RING(ring, ir3_shader_nibo(state->fs));
OUT_PKT4(ring, REG_A6XX_SP_UAV_COUNT, 1);
OUT_RING(ring, ir3_shader_num_uavs(state->fs));
state->config_stateobj = ring;
}

2
src/gallium/drivers/freedreno/ir3/ir3_descriptor.h
View file

@ -27,7 +27,7 @@
#define IR3_BINDLESS_DESC_COUNT (IR3_BINDLESS_IMAGE_OFFSET + IR3_BINDLESS_IMAGE_COUNT)
/**
* When using bindless descriptor sets for IBO/etc, each shader stage gets
* When using bindless descriptor sets for UAV/etc, each shader stage gets
* it's own descriptor set, avoiding the need to merge image/ssbo state
* across shader stages.
*/