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radeon/llvm: Remove AMDIL EXP* instructions

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This commit is contained in:
Tom Stellard 2012-05-23 15:37:11 -04:00
parent dd9927eb36
commit a8ba697c1e
5 changed files with 7 additions and 15 deletions
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11
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
View file

@ -31,10 +31,6 @@
use warnings;
use strict;
my @F32_MULTICLASSES = qw {
UnaryIntrinsicFloatScalar
};
my @I32_MULTICLASSES = qw {
BinaryOpMCi32Const
};
@ -52,14 +48,11 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'SMULHI_i32', 'SMUL_i32');
my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'SMULHI_i32', 'SMUL_i32', 'LOG_f32', 'RSQ_f32', 'SIN_f32', 'COS_f32');
while (<AMDIL>) {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
if (grep {$_ eq $2} @F32_MULTICLASSES) {
push @INST_ENUMS, "$1\_f32";
} elsif (grep {$_ eq $2} @I32_MULTICLASSES) {
if (grep {$_ eq $2} @I32_MULTICLASSES) {
push @INST_ENUMS, "$1\_i32";
}
} elsif ($_ =~ /def\s+([A-Z_]+)(_[fi]32)/) {

3
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
View file

@ -30,6 +30,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
// Library functions. These default to Expand, but we have instructions
// for them.
setOperationAction(ISD::FCEIL, MVT::f32, Legal);
setOperationAction(ISD::FEXP2, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal);
}
@ -55,6 +56,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
default: return Op;
case AMDGPUIntrinsic::AMDIL_abs:
return LowerIntrinsicIABS(Op, DAG);
case AMDGPUIntrinsic::AMDIL_exp:
return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
case AMDGPUIntrinsic::AMDGPU_lrp:
return LowerIntrinsicLRP(Op, DAG);
case AMDGPUIntrinsic::AMDIL_fraction:

1
src/gallium/drivers/radeon/AMDGPUUtil.cpp
View file

@ -55,7 +55,6 @@ bool AMDGPU::isTransOp(unsigned opcode)
case AMDIL::MUL_LIT_eg:
case AMDIL::SHR_i32:
case AMDIL::SIN_f32:
case AMDIL::EXP_f32:
case AMDIL::EXP_IEEE_r600:
case AMDIL::EXP_IEEE_eg:
case AMDIL::LOG_CLAMPED_r600:

2
src/gallium/drivers/radeon/AMDILInstructions.td
View file

@ -218,8 +218,6 @@ defm TAN : UnaryIntrinsicFloatScalar<IL_OP_TAN, int_AMDIL_tan>;
defm SIN : UnaryIntrinsicFloatScalar<IL_OP_SIN, int_AMDIL_sin>;
defm COS : UnaryIntrinsicFloatScalar<IL_OP_COS, int_AMDIL_cos>;
defm SQRT : UnaryIntrinsicFloatScalar<IL_OP_SQRT, int_AMDIL_sqrt>;
defm EXP : UnaryIntrinsicFloatScalar<IL_OP_EXP, int_AMDIL_exp>;
defm EXPVEC : UnaryIntrinsicFloat<IL_OP_EXP_VEC, int_AMDIL_exp_vec>;
defm SQRTVEC : UnaryIntrinsicFloat<IL_OP_SQRT_VEC, int_AMDIL_sqrt_vec>;
defm COSVEC : UnaryIntrinsicFloat<IL_OP_COS_VEC, int_AMDIL_cos_vec>;
defm SINVEC : UnaryIntrinsicFloat<IL_OP_SIN_VEC, int_AMDIL_sin_vec>;

5
src/gallium/drivers/radeon/R600Instructions.td
View file

@ -622,9 +622,8 @@ class CUBE_Common <bits<32> inst> : InstR600 <
class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
inst, "EXP_IEEE",
[]> {
let AMDILOp = AMDILInst.EXP_f32;
}
[(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
>;
class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
inst, "FLT_TO_INT", []> {