From a8b72082cfb2dcf92a46e6e6e66ae5d4aa0bcac4 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Wed, 14 Feb 2024 15:30:44 +0000 Subject: [PATCH] aco/ra: constify various RegisterFile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes it more obvious that these functions don't change it. Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_register_allocation.cpp | 52 +++++++++++--------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 18753ae2fc0..c6e9f2c4f33 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -262,7 +262,7 @@ public: uint32_t& operator[](PhysReg index) { return regs[index]; } - unsigned count_zero(PhysRegInterval reg_interval) + unsigned count_zero(PhysRegInterval reg_interval) const { unsigned res = 0; for (PhysReg reg : reg_interval) @@ -271,16 +271,17 @@ public: } /* Returns true if any of the bytes in the given range are allocated or blocked */ - bool test(PhysReg start, unsigned num_bytes) + bool test(PhysReg start, unsigned num_bytes) const { for (PhysReg i = start; i.reg_b < start.reg_b + num_bytes; i = PhysReg(i + 1)) { assert(i <= 511); if (regs[i] & 0x0FFFFFFF) return true; if (regs[i] == 0xF0000000) { - assert(subdword_regs.find(i) != subdword_regs.end()); + auto it = subdword_regs.find(i); + assert(it != subdword_regs.end()); for (unsigned j = i.byte(); i * 4 + j < start.reg_b + num_bytes && j < 4; j++) { - if (subdword_regs[i][j]) + if (it->second[j]) return true; } } @@ -296,24 +297,28 @@ public: fill(start, rc.size(), 0xFFFFFFFF); } - bool is_blocked(PhysReg start) + bool is_blocked(PhysReg start) const { if (regs[start] == 0xFFFFFFFF) return true; if (regs[start] == 0xF0000000) { + auto it = subdword_regs.find(start); + assert(it != subdword_regs.end()); for (unsigned i = start.byte(); i < 4; i++) - if (subdword_regs[start][i] == 0xFFFFFFFF) + if (it->second[i] == 0xFFFFFFFF) return true; } return false; } - bool is_empty_or_blocked(PhysReg start) + bool is_empty_or_blocked(PhysReg start) const { /* Empty is 0, blocked is 0xFFFFFFFF, so to check both we compare the * incremented value to 1 */ if (regs[start] == 0xF0000000) { - return subdword_regs[start][start.byte()] + 1 <= 1; + auto it = subdword_regs.find(start); + assert(it != subdword_regs.end()); + return it->second[start.byte()] + 1 <= 1; } return regs[start] + 1 <= 1; } @@ -346,9 +351,9 @@ public: void clear(Definition def) { clear(def.physReg(), def.regClass()); } - unsigned get_id(PhysReg reg) + unsigned get_id(PhysReg reg) const { - return regs[reg] == 0xF0000000 ? subdword_regs[reg][reg.byte()] : regs[reg]; + return regs[reg] == 0xF0000000 ? subdword_regs.at(reg)[reg.byte()] : regs[reg]; } private: @@ -376,7 +381,7 @@ private: } }; -std::vector find_vars(ra_ctx& ctx, RegisterFile& reg_file, +std::vector find_vars(ra_ctx& ctx, const RegisterFile& reg_file, const PhysRegInterval reg_interval); /* helper function for debugging */ @@ -419,7 +424,7 @@ print_reg(const RegisterFile& reg_file, PhysReg reg, bool has_adjacent_variable) /* helper function for debugging */ UNUSED void -print_regs(ra_ctx& ctx, bool vgprs, RegisterFile& reg_file) +print_regs(ra_ctx& ctx, bool vgprs, const RegisterFile& reg_file) { PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr); char reg_char = vgprs ? 'v' : 's'; @@ -880,7 +885,7 @@ update_renames(ra_ctx& ctx, RegisterFile& reg_file, } std::optional -get_reg_simple(ra_ctx& ctx, RegisterFile& reg_file, DefInfo info) +get_reg_simple(ra_ctx& ctx, const RegisterFile& reg_file, DefInfo info) { const PhysRegInterval& bounds = info.bounds; uint32_t size = info.size; @@ -973,7 +978,8 @@ get_reg_simple(ra_ctx& ctx, RegisterFile& reg_file, DefInfo info) * larger instruction encodings or copies * TODO: don't do this in situations where it doesn't benefit */ if (rc.is_subdword()) { - for (std::pair>& entry : reg_file.subdword_regs) { + for (const std::pair>& entry : + reg_file.subdword_regs) { assert(reg_file[PhysReg{entry.first}] == 0xF0000000); if (!bounds.contains({PhysReg{entry.first}, rc.size()})) continue; @@ -1003,7 +1009,7 @@ get_reg_simple(ra_ctx& ctx, RegisterFile& reg_file, DefInfo info) /* collect variables from a register area */ std::vector -find_vars(ra_ctx& ctx, RegisterFile& reg_file, const PhysRegInterval reg_interval) +find_vars(ra_ctx& ctx, const RegisterFile& reg_file, const PhysRegInterval reg_interval) { std::vector vars; for (PhysReg j : reg_interval) { @@ -1011,7 +1017,7 @@ find_vars(ra_ctx& ctx, RegisterFile& reg_file, const PhysRegInterval reg_interva continue; if (reg_file[j] == 0xF0000000) { for (unsigned k = 0; k < 4; k++) { - unsigned id = reg_file.subdword_regs[j][k]; + unsigned id = reg_file.subdword_regs.at(j)[k]; if (id && (vars.empty() || id != vars.back())) vars.emplace_back(id); } @@ -1254,7 +1260,7 @@ get_regs_for_copies(ra_ctx& ctx, RegisterFile& reg_file, } std::optional -get_reg_impl(ra_ctx& ctx, RegisterFile& reg_file, +get_reg_impl(ra_ctx& ctx, const RegisterFile& reg_file, std::vector>& parallelcopies, const DefInfo& info, aco_ptr& instr) { @@ -1402,8 +1408,8 @@ get_reg_impl(ra_ctx& ctx, RegisterFile& reg_file, } bool -get_reg_specified(ra_ctx& ctx, RegisterFile& reg_file, RegClass rc, aco_ptr& instr, - PhysReg reg) +get_reg_specified(ra_ctx& ctx, const RegisterFile& reg_file, RegClass rc, + aco_ptr& instr, PhysReg reg) { /* catch out-of-range registers */ if (reg >= PhysReg{512}) @@ -1538,7 +1544,7 @@ compact_relocate_vars(ra_ctx& ctx, const std::vector& vars, } bool -is_mimg_vaddr_intact(ra_ctx& ctx, RegisterFile& reg_file, Instruction* instr) +is_mimg_vaddr_intact(ra_ctx& ctx, const RegisterFile& reg_file, Instruction* instr) { PhysReg first{512}; for (unsigned i = 0; i < instr->operands.size() - 3u; i++) { @@ -1570,7 +1576,7 @@ is_mimg_vaddr_intact(ra_ctx& ctx, RegisterFile& reg_file, Instruction* instr) } std::optional -get_reg_vector(ra_ctx& ctx, RegisterFile& reg_file, Temp temp, aco_ptr& instr) +get_reg_vector(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp, aco_ptr& instr) { Instruction* vec = ctx.vectors[temp.id()]; unsigned first_operand = vec->format == Format::MIMG ? 3 : 0; @@ -1622,7 +1628,7 @@ get_reg_vector(ra_ctx& ctx, RegisterFile& reg_file, Temp temp, aco_ptr>& parallelcopies, aco_ptr& instr, int operand_index = -1) { @@ -1735,7 +1741,7 @@ get_reg(ra_ctx& ctx, RegisterFile& reg_file, Temp temp, } PhysReg -get_reg_create_vector(ra_ctx& ctx, RegisterFile& reg_file, Temp temp, +get_reg_create_vector(ra_ctx& ctx, const RegisterFile& reg_file, Temp temp, std::vector>& parallelcopies, aco_ptr& instr) {