From a854a9fa623d3269eeebdc34c06ae442a65e2e41 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 21 Apr 2021 14:11:44 +0200 Subject: [PATCH] radv: fix various CMASK regressions on GFX9 This fixes a bunch of MSAA related CTS regressions. This restores previous behaviour on GFX9 but it should be fixed properly. Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 26 +++++++++++++++++++++----- src/amd/vulkan/radv_meta_clear.c | 12 +++++++++--- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 4e6d33dc6ac..1b5b1a1c1cc 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5991,11 +5991,8 @@ radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra static uint32_t radv_init_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, - const VkImageSubresourceRange *range) + const VkImageSubresourceRange *range, uint32_t value) { - static const uint32_t cmask_clear_values[4] = {0xffffffff, 0xdddddddd, 0xeeeeeeee, 0xffffffff}; - uint32_t log2_samples = util_logbase2(image->info.samples); - uint32_t value = cmask_clear_values[log2_samples]; struct radv_barrier_data barrier = {0}; barrier.layout_transitions.init_mask_ram = 1; @@ -6079,7 +6076,26 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image); if (radv_image_has_cmask(image)) { - flush_bits |= radv_init_cmask(cmd_buffer, image, range); + uint32_t value; + + if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + /* TODO: Fix clearing CMASK layers on GFX9. */ + if (radv_image_is_tc_compat_cmask(image) || + (radv_image_has_fmask(image) && + radv_layout_can_fast_clear(cmd_buffer->device, image, dst_layout, + dst_render_loop, dst_queue_mask))) { + value = 0xccccccccu; + } else { + value = 0xffffffffu; + } + } else { + static const uint32_t cmask_clear_values[4] = {0xffffffff, 0xdddddddd, 0xeeeeeeee, 0xffffffff}; + uint32_t log2_samples = util_logbase2(image->info.samples); + + value = cmask_clear_values[log2_samples]; + } + + flush_bits |= radv_init_cmask(cmd_buffer, image, range, value); } if (radv_image_has_fmask(image)) { diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 0966c5b4a95..d9c09e01682 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1242,11 +1242,17 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value) { uint64_t offset = image->offset + image->planes[0].surface.cmask_offset; - unsigned slice_size = image->planes[0].surface.cmask_slice_size; uint64_t size; - offset += slice_size * range->baseArrayLayer; - size = slice_size * radv_get_layerCount(image, range); + if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + /* TODO: clear layers. */ + size = image->planes[0].surface.cmask_size; + } else { + unsigned slice_size = image->planes[0].surface.cmask_slice_size; + + offset += slice_size * range->baseArrayLayer; + size = slice_size * radv_get_layerCount(image, range); + } return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); }