diff --git a/.pick_status.json b/.pick_status.json
index 521349c67dd..aefb6c9f338 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -5179,7 +5179,7 @@
         "description": "radv: Fix mipmap extent adjustment on GFX9+.",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": null
     },
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 4ef58baa4c8..5eb79f1b4e5 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1493,6 +1493,9 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib,
       }
    }
 
+   surf->u.gfx9.base_mip_width = mip_info[0].pitch;
+   surf->u.gfx9.base_mip_height = mip_info[0].height;
+
    if (in->flags.depth) {
       assert(in->swizzleMode != ADDR_SW_LINEAR);
 
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 766be2bb770..c825ad14ff7 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -163,7 +163,10 @@ struct gfx9_surf_layout {
    /* Mipmap level pitch in elements. Only valid for LINEAR. */
    uint16_t               pitch[RADEON_SURF_MAX_LEVELS];
 
-   uint64_t               stencil_offset; /* separate stencil */
+   uint16_t base_mip_width;
+   uint16_t base_mip_height;
+
+   uint64_t stencil_offset; /* separate stencil */
 
    uint8_t                dcc_block_width;
    uint8_t                dcc_block_height;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index e2204c4add0..6c3836242c7 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1652,26 +1652,15 @@ radv_image_view_init(struct radv_image_view *iview,
 		 *
 		 * This means that mip2 will be missing texels.
 		 *
-		 * Fix this by calculating the base mip's width and height, then convert that, and round it
-		 * back up to get the level 0 size.
-		 * Clamp the converted size between the original values, and next power of two, which
-		 * means we don't oversize the image.
+		 * Fix it by taking the actual extent addrlib assigned to the base mip level.
 		 */
-		 if (device->physical_device->rad_info.chip_class >= GFX9 &&
+		if (device->physical_device->rad_info.chip_class >= GFX9 &&
 		     vk_format_is_compressed(image->vk_format) &&
-		     !vk_format_is_compressed(iview->vk_format)) {
-			 unsigned lvl_width  = radv_minify(image->info.width , range->baseMipLevel);
-			 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
-
-			 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
-			 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
-
-			 lvl_width <<= range->baseMipLevel;
-			 lvl_height <<= range->baseMipLevel;
-
-			 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
-			 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
-		 }
+		     !vk_format_is_compressed(iview->vk_format) &&
+		     iview->image->info.levels > 1) {
+			iview->extent.width = iview->image->planes[0].surface.u.gfx9.base_mip_width;
+			iview->extent.height = iview->image->planes[0].surface.u.gfx9.base_mip_height;
+		}
 	}
 
 	iview->base_layer = range->baseArrayLayer;