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spirv2dxil: Lower some wave op properties
DXIL has no concept of subgroup mask ops, relative shuffle ops, and everything is scalar. Most wave broadcast ops support i1 overloads, except for quad swap operations. Go figure. Use lower_bit_size to promote those to i32 instead. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20801>
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1 changed files with 26 additions and 0 deletions
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@ -873,6 +873,22 @@ dxil_spirv_nir_link(nir_shader *nir, nir_shader *prev_stage_nir,
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glsl_type_singleton_decref();
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}
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static unsigned
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lower_bit_size_callback(const nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return 0;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_quad_swap_horizontal:
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case nir_intrinsic_quad_swap_vertical:
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case nir_intrinsic_quad_swap_diagonal:
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return intr->dest.ssa.bit_size == 1 ? 32 : 0;
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default:
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return 0;
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}
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}
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void
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dxil_spirv_nir_passes(nir_shader *nir,
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const struct dxil_spirv_runtime_conf *conf,
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@ -902,6 +918,16 @@ dxil_spirv_nir_passes(nir_shader *nir,
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NIR_PASS_V(nir, dxil_nir_lower_subgroup_id);
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NIR_PASS_V(nir, dxil_nir_lower_num_subgroups);
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nir_lower_subgroups_options subgroup_options = {
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.ballot_bit_size = 32,
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.ballot_components = 4,
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.lower_subgroup_masks = true,
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.lower_to_scalar = true,
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.lower_relative_shuffle = true,
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};
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NIR_PASS_V(nir, nir_lower_subgroups, &subgroup_options);
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NIR_PASS_V(nir, nir_lower_bit_size, lower_bit_size_callback, NULL);
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// Force sample-rate shading if we're asked to.
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if (conf->force_sample_rate_shading) {
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assert(nir->info.stage == MESA_SHADER_FRAGMENT);
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