From a7ff177a88efca7aa3ec8b4a4d0cc724d43d516b Mon Sep 17 00:00:00 2001
From: Caio Oliveira <caio.oliveira@intel.com>
Date: Fri, 11 Apr 2025 11:54:30 -0700
Subject: [PATCH] brw: Consider bfloat16 in lower simd width pass

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34105>
---
 src/intel/compiler/brw_lower_simd_width.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/compiler/brw_lower_simd_width.cpp b/src/intel/compiler/brw_lower_simd_width.cpp
index 2404ad09453..28e57ec43fa 100644
--- a/src/intel/compiler/brw_lower_simd_width.cpp
+++ b/src/intel/compiler/brw_lower_simd_width.cpp
@@ -110,6 +110,9 @@ get_fpu_lowered_simd_width(const brw_shader *shader,
    if (inst->is_3src(compiler) && !devinfo->supports_simd16_3src)
       max_width = MIN2(max_width, inst->exec_size / reg_count);
 
+   if (has_bfloat_operands(inst))
+      max_width = MIN2(max_width, devinfo->ver < 20 ? 8 : 16);
+
    if (inst->opcode != BRW_OPCODE_MOV) {
       /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
        * Float Operations: