fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-06 04:30:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: pass a pointer to a pipeline for the create/insert cache functions

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13690>
This commit is contained in:
Samuel Pitoiset 2021-11-05 13:57:35 +01:00 • committed by Marge Bot
parent 13143b3c11
commit a7f0463612
3 changed files with 15 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/vulkan/radv_pipeline.c
View file

@ -3408,7 +3408,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
bool found_in_application_cache = true;
if (!keep_executable_info &&
radv_create_shaders_from_pipeline_cache(device, cache, hash, pipeline->shaders,
radv_create_shaders_from_pipeline_cache(device, cache, hash, pipeline,
stack_sizes, num_stack_sizes,
&found_in_application_cache)) {
if (modules[MESA_SHADER_GEOMETRY] && !pipeline->shaders[MESA_SHADER_GEOMETRY]->info.is_ngg) {
@ -3713,7 +3713,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
pipeline->shaders[MESA_SHADER_COMPUTE] = pipeline->gs_copy_shader;
}
radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders, binaries,
radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline, binaries,
stack_sizes ? *stack_sizes : NULL,
num_stack_sizes ? *num_stack_sizes : 0);

22
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -294,7 +294,7 @@ radv_is_cache_disabled(struct radv_device *device)
bool
radv_create_shaders_from_pipeline_cache(
struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
struct radv_shader **shaders, struct radv_pipeline_shader_stack_size **stack_sizes,
struct radv_pipeline *pipeline, struct radv_pipeline_shader_stack_size **stack_sizes,
uint32_t *num_stack_sizes, bool *found_in_application_cache)
{
struct cache_entry *entry;
@ -368,7 +368,7 @@ radv_create_shaders_from_pipeline_cache(
}
}
memcpy(shaders, entry->shaders, sizeof(entry->shaders));
memcpy(pipeline->shaders, entry->shaders, sizeof(entry->shaders));
if (num_stack_sizes) {
*num_stack_sizes = entry->num_stack_sizes;
@ -397,7 +397,7 @@ radv_create_shaders_from_pipeline_cache(
void
radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipeline_cache *cache,
const unsigned char *sha1, struct radv_shader **shaders,
const unsigned char *sha1, struct radv_pipeline *pipeline,
struct radv_shader_binary *const *binaries,
const struct radv_pipeline_shader_stack_size *stack_sizes,
uint32_t num_stack_sizes)
@ -412,10 +412,10 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
if (!entry->shaders[i])
continue;
radv_shader_destroy(cache->device, shaders[i]);
radv_shader_destroy(cache->device, pipeline->shaders[i]);
shaders[i] = entry->shaders[i];
p_atomic_inc(&shaders[i]->ref_count);
pipeline->shaders[i] = entry->shaders[i];
p_atomic_inc(&pipeline->shaders[i]->ref_count);
}
radv_pipeline_cache_unlock(cache);
return;
@ -431,7 +431,7 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
size_t size = sizeof(*entry) + sizeof(*stack_sizes) * num_stack_sizes;
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; ++i)
if (shaders[i])
if (pipeline->shaders[i])
size += binaries[i]->total_size;
const size_t size_without_align = size;
size = align(size_without_align, alignof(struct cache_entry));
@ -448,7 +448,7 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
char *p = entry->code;
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; ++i) {
if (!shaders[i])
if (!pipeline->shaders[i])
continue;
entry->binary_sizes[i] = binaries[i]->total_size;
@ -492,11 +492,11 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device, struct radv_pipel
* items.
*/
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; ++i) {
if (!shaders[i])
if (!pipeline->shaders[i])
continue;
entry->shaders[i] = shaders[i];
p_atomic_inc(&shaders[i]->ref_count);
entry->shaders[i] = pipeline->shaders[i];
p_atomic_inc(&pipeline->shaders[i]->ref_count);
}
radv_pipeline_cache_add_entry(cache, entry);

4
src/amd/vulkan/radv_private.h
View file

@ -365,12 +365,12 @@ bool radv_pipeline_cache_load(struct radv_pipeline_cache *cache, const void *dat
bool radv_create_shaders_from_pipeline_cache(
struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
struct radv_shader **shaders, struct radv_pipeline_shader_stack_size **stack_sizes,
struct radv_pipeline *pipeline, struct radv_pipeline_shader_stack_size **stack_sizes,
uint32_t *num_stack_sizes, bool *found_in_application_cache);
void radv_pipeline_cache_insert_shaders(
struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
struct radv_shader **shaders, struct radv_shader_binary *const *binaries,
struct radv_pipeline *pipeline, struct radv_shader_binary *const *binaries,
const struct radv_pipeline_shader_stack_size *stack_sizes, uint32_t num_stack_sizes);
enum radv_blit_ds_layout {