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Simple TCL stage and ability to disable vps.
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parent
80a939cafb
commit
a78bbd0816
4 changed files with 54 additions and 6 deletions
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@ -102,12 +102,13 @@ static const char *const card_extensions[] = {
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};
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extern struct tnl_pipeline_stage _r300_render_stage;
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extern struct tnl_pipeline_stage _r300_tcl_stage;
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static const struct tnl_pipeline_stage *r300_pipeline[] = {
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/* Try and go straight to t&l
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*/
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// &_r300_tcl_stage,
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&_r300_tcl_stage,
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/* Catch any t&l fallbacks
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*/
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@ -272,7 +272,7 @@ void r300EmitArrays(GLcontext * ctx, GLboolean immd)
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} \
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}
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if (rmesa->current_vp != NULL) {
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if (rmesa->current_vp != NULL && ctx->VertexProgram._Enabled) {
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if (rmesa->current_vp->inputs[VERT_ATTRIB_POS] != -1) {
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inputs |= _TNL_BIT_POS;
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rmesa->state.aos[nr++].aos_reg = rmesa->current_vp->inputs[VERT_ATTRIB_POS];
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@ -497,7 +497,7 @@ drm_radeon_cmd_header_t *cmd = NULL;
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#endif
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/* Stage 3: VAP output */
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if (rmesa->current_vp != NULL)
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if (rmesa->current_vp != NULL && ctx->VertexProgram._Enabled)
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outputs = rmesa->current_vp->outputs;
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else
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outputs = inputs;
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@ -672,7 +672,7 @@ static void r300_check_render(GLcontext *ctx, struct tnl_pipeline_stage *stage)
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stage->active = GL_FALSE;
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return;
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}
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/* I'm almost certain I forgot something here */
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#if 0 /* These should work now.. */
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@ -731,3 +731,50 @@ const struct tnl_pipeline_stage _r300_render_stage = {
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r300_check_render, /* check */
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r300_run_render /* run */
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};
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static GLboolean r300_run_tcl_render(GLcontext *ctx,
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struct tnl_pipeline_stage *stage)
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{
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r300ContextPtr rmesa = R300_CONTEXT(ctx);
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TNLcontext *tnl = TNL_CONTEXT(ctx);
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struct vertex_buffer *VB = &tnl->vb;
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GLuint i;
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if (RADEON_DEBUG & DEBUG_PRIMS)
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fprintf(stderr, "%s\n", __FUNCTION__);
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return r300_run_vb_render(ctx, stage);
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}
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static void r300_check_tcl_render(GLcontext *ctx, struct tnl_pipeline_stage *stage)
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{
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r300ContextPtr r300 = R300_CONTEXT(ctx);
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int i;
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if (RADEON_DEBUG & DEBUG_STATE)
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fprintf(stderr, "%s\n", __FUNCTION__);
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/* We only support rendering in hardware for now */
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if (ctx->RenderMode != GL_RENDER) {
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stage->active = GL_FALSE;
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return;
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}
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if((r300->current_vp != NULL) && ctx->VertexProgram._Enabled) {
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stage->active = GL_TRUE;
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stage->inputs = ctx->VertexProgram.Current->InputsRead;
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} else {
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stage->active = GL_FALSE;
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}
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}
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const struct tnl_pipeline_stage _r300_tcl_stage = {
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"r300 tcl",
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_NEW_ALL, /* re-check (always re-check for now) */
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0, /* re-run (always runs) */
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GL_TRUE, /* active */
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0, 0, /* inputs (set in check_render), outputs */
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0, 0, /* changed_inputs, private */
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dtr, /* destructor */
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r300_check_tcl_render, /* check */
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r300_run_tcl_render /* run */
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};
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@ -1435,7 +1435,7 @@ void r300_setup_rs_unit(GLcontext *ctx)
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cur_reg = 0;
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r300->hw.rr.cmd[R300_RR_ROUTE_0] = 0;
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if (r300->current_vp != NULL)
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if (r300->current_vp != NULL && ctx->VertexProgram._Enabled)
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vap_outputs = r300->current_vp->outputs;
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else
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vap_outputs = r300->state.render_inputs;
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@ -1693,7 +1693,7 @@ void r300SetupVertexShader(r300ContextPtr rmesa)
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0x400 area might have something to do with pixel shaders as it appears right after pfs programming.
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0x406 is set to { 0.0, 0.0, 1.0, 0.0 } most of the time but should change with smooth points and in other rare cases. */
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//setup_vertex_shader_fragment(rmesa, 0x406, &unk4);
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if(rmesa->current_vp != NULL){
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if(rmesa->current_vp != NULL && ctx->VertexProgram._Enabled){
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r300SetupVertexProgram(rmesa);
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return ;
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}
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