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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-09 04:38:03 +02:00
radv: clean up the sample locations codebase
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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135dff8dcf
commit
a7763ddcf2
4 changed files with 75 additions and 97 deletions
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@ -669,7 +669,7 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
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radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
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radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
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radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
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/* GFX9: Flush DFSM when the AA mode changes. */
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if (cmd_buffer->device->dfsm_allowed) {
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@ -1128,7 +1128,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
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S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
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S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
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ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
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S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
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S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
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S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
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ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
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if (ps_iter_samples > 1)
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@ -1212,8 +1212,8 @@ void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
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void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
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void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
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void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
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void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
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unsigned radv_cayman_get_maxdist(int log_samples);
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void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
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unsigned radv_get_default_max_sample_dist(int log_samples);
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void radv_device_init_msaa(struct radv_device *device);
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void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
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@ -1300,144 +1300,122 @@ void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
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/* For MSAA sample positions. */
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#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
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(((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
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(((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
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(((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
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((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
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(((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
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(((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
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(((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
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/* For obtaining location coordinates from registers */
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#define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
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#define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
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#define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
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#define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
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/* 2xMSAA
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* There are two locations (4, 4), (-4, -4). */
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const uint32_t eg_sample_locs_2x[4] = {
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
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};
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const unsigned eg_max_dist_2x = 4;
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/* 4xMSAA
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* There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
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const uint32_t eg_sample_locs_4x[4] = {
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
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};
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const unsigned eg_max_dist_4x = 6;
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/* 1x MSAA */
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static const uint32_t sample_locs_1x =
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FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
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static const unsigned max_dist_1x = 0;
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/* Cayman 8xMSAA */
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static const uint32_t cm_sample_locs_8x[] = {
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
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};
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static const unsigned cm_max_dist_8x = 8;
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/* 2xMSAA */
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static const uint32_t sample_locs_2x =
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FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
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static const unsigned max_dist_2x = 4;
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unsigned radv_cayman_get_maxdist(int log_samples)
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/* 4xMSAA */
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static const uint32_t sample_locs_4x =
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FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
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static const unsigned max_dist_4x = 6;
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/* 8xMSAA */
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static const uint32_t sample_locs_8x[] = {
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FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
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FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
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/* The following are unused by hardware, but we emit them to IBs
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* instead of multiple SET_CONTEXT_REG packets. */
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0,
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0,
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};
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static const unsigned max_dist_8x = 8;
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unsigned radv_get_default_max_sample_dist(int log_samples)
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{
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unsigned max_dist[] = {
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0,
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eg_max_dist_2x,
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eg_max_dist_4x,
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cm_max_dist_8x,
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max_dist_1x,
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max_dist_2x,
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max_dist_4x,
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max_dist_8x,
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};
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return max_dist[log_samples];
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}
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void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
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void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
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{
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switch (nr_samples) {
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default:
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case 1:
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radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
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radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
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radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
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radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
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radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
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radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
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radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
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radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
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break;
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case 2:
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radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
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radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
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radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
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radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
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radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
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radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
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radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
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radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
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break;
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case 4:
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radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
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radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
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radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
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radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
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radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
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radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
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radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
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radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
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break;
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case 8:
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radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
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radeon_emit(cs, cm_sample_locs_8x[0]);
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radeon_emit(cs, cm_sample_locs_8x[4]);
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, cm_sample_locs_8x[1]);
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radeon_emit(cs, cm_sample_locs_8x[5]);
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, cm_sample_locs_8x[2]);
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radeon_emit(cs, cm_sample_locs_8x[6]);
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, cm_sample_locs_8x[3]);
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radeon_emit(cs, cm_sample_locs_8x[7]);
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radeon_emit_array(cs, sample_locs_8x, 4);
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radeon_emit_array(cs, sample_locs_8x, 4);
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radeon_emit_array(cs, sample_locs_8x, 4);
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radeon_emit_array(cs, sample_locs_8x, 2);
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break;
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}
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}
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static void radv_cayman_get_sample_position(struct radv_device *device,
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unsigned sample_count,
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unsigned sample_index, float *out_value)
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static void radv_get_sample_position(struct radv_device *device,
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unsigned sample_count,
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unsigned sample_index, float *out_value)
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{
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int offset, index;
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struct {
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int idx:4;
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} val;
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const uint32_t *sample_locs;
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switch (sample_count) {
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case 1:
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default:
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out_value[0] = out_value[1] = 0.5;
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sample_locs = &sample_locs_1x;
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break;
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case 2:
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offset = 4 * (sample_index * 2);
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val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
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out_value[0] = (float)(val.idx + 8) / 16.0f;
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val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
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out_value[1] = (float)(val.idx + 8) / 16.0f;
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sample_locs = &sample_locs_2x;
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break;
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case 4:
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offset = 4 * (sample_index * 2);
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val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
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out_value[0] = (float)(val.idx + 8) / 16.0f;
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val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
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out_value[1] = (float)(val.idx + 8) / 16.0f;
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sample_locs = &sample_locs_4x;
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break;
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case 8:
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offset = 4 * (sample_index % 4 * 2);
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index = (sample_index / 4) * 4;
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val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
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out_value[0] = (float)(val.idx + 8) / 16.0f;
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val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
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out_value[1] = (float)(val.idx + 8) / 16.0f;
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sample_locs = sample_locs_8x;
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break;
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}
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out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
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out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
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}
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void radv_device_init_msaa(struct radv_device *device)
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{
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int i;
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radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
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radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
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for (i = 0; i < 2; i++)
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radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
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radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
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for (i = 0; i < 4; i++)
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radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
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radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
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for (i = 0; i < 8; i++)
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radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
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radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
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}
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