fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 07:28:11 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

anv: add support for handling wa_18019110168 with gfx-libs

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35103>
This commit is contained in:
Lionel Landwerlin 2025-05-21 14:37:49 +03:00 • committed by Marge Bot
parent fcf4401824
commit a742b859bd
8 changed files with 97 additions and 23 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/intel/compiler/brw_nir_wa_18019110168.c
View file

@ -553,7 +553,7 @@ brw_nir_frag_convert_attrs_prim_to_vert_indirect(struct nir_shader *nir,
&per_primitive_stride,
&first_read_offset,
0, nir, nir_var_shader_in,
nir->info.per_primitive_inputs,
per_primitive_inputs,
true /* separate_shader */);
per_primitive_stride = align(per_primitive_stride, devinfo->grf_size);

59
src/intel/vulkan/anv_nir_compute_push_layout.c
View file

@ -90,6 +90,11 @@ anv_nir_compute_push_layout(nir_shader *nir,
has_const_ubo && nir->info.stage != MESA_SHADER_COMPUTE &&
!brw_shader_stage_requires_bindless_resources(nir->info.stage);
const bool needs_wa_18019110168 =
nir->info.stage == MESA_SHADER_FRAGMENT &&
brw_nir_fragment_shader_needs_wa_18019110168(
devinfo, mesh_dynamic ? INTEL_SOMETIMES : INTEL_NEVER, nir);
if (push_ubo_ranges && (robust_flags & BRW_ROBUSTNESS_UBO)) {
/* We can't on-the-fly adjust our push ranges because doing so would
* mess up the layout in the shader. When robustBufferAccess is
@ -106,13 +111,26 @@ anv_nir_compute_push_layout(nir_shader *nir,
push_end = MAX2(push_end, push_reg_mask_end);
}
if (nir->info.stage == MESA_SHADER_FRAGMENT && fragment_dynamic) {
const uint32_t fs_msaa_flags_start =
anv_drv_const_offset(gfx.fs_msaa_flags);
const uint32_t fs_msaa_flags_end = fs_msaa_flags_start +
anv_drv_const_size(gfx.fs_msaa_flags);
push_start = MIN2(push_start, fs_msaa_flags_start);
push_end = MAX2(push_end, fs_msaa_flags_end);
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
if (fragment_dynamic) {
const uint32_t fs_msaa_flags_start =
anv_drv_const_offset(gfx.fs_msaa_flags);
const uint32_t fs_msaa_flags_end =
fs_msaa_flags_start +
anv_drv_const_size(gfx.fs_msaa_flags);
push_start = MIN2(push_start, fs_msaa_flags_start);
push_end = MAX2(push_end, fs_msaa_flags_end);
}
if (needs_wa_18019110168) {
const uint32_t fs_per_prim_remap_start =
anv_drv_const_offset(gfx.fs_per_prim_remap_offset);
const uint32_t fs_per_prim_remap_end =
fs_per_prim_remap_start +
anv_drv_const_size(gfx.fs_per_prim_remap_offset);
push_start = MIN2(push_start, fs_per_prim_remap_start);
push_end = MAX2(push_end, fs_per_prim_remap_end);
}
}
if (nir->info.stage == MESA_SHADER_COMPUTE && devinfo->verx10 < 125) {
@ -226,8 +244,9 @@ anv_nir_compute_push_layout(nir_shader *nir,
* dynamic bit in fs_msaa_intel.
*/
const bool needs_padding_per_primitive =
mesh_dynamic &&
(nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID);
needs_wa_18019110168 ||
(mesh_dynamic &&
(nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID));
unsigned n_push_ranges = 0;
if (push_ubo_ranges) {
@ -330,15 +349,25 @@ anv_nir_compute_push_layout(nir_shader *nir,
assert(n_push_ranges <= 4);
if (nir->info.stage == MESA_SHADER_FRAGMENT && fragment_dynamic) {
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
struct brw_wm_prog_data *wm_prog_data =
container_of(prog_data, struct brw_wm_prog_data, base);
const uint32_t fs_msaa_flags_offset =
anv_drv_const_offset(gfx.fs_msaa_flags);
assert(fs_msaa_flags_offset >= push_start);
wm_prog_data->msaa_flags_param =
(fs_msaa_flags_offset - push_start) / 4;
if (fragment_dynamic) {
const uint32_t fs_msaa_flags_offset =
anv_drv_const_offset(gfx.fs_msaa_flags);
assert(fs_msaa_flags_offset >= push_start);
wm_prog_data->msaa_flags_param =
(fs_msaa_flags_offset - push_start) / 4;
}
if (needs_wa_18019110168) {
const uint32_t fs_per_prim_remap_offset =
anv_drv_const_offset(gfx.fs_per_prim_remap_offset);
assert(fs_per_prim_remap_offset >= push_start);
wm_prog_data->per_primitive_remap_param =
(fs_per_prim_remap_offset - push_start) / 4;
}
}
#if 0

9
src/intel/vulkan/anv_pipeline.c
View file

@ -1619,6 +1619,15 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler,
(uint32_t)fs_stage->prog_data.wm.dispatch_16 +
(uint32_t)fs_stage->prog_data.wm.dispatch_32;
assert(fs_stage->num_stats <= ARRAY_SIZE(fs_stage->stats));
for (unsigned i = 0; i < ARRAY_SIZE(fs_stage->bind_map.push_ranges); i++) {
if (fs_stage->bind_map.push_ranges[i].set == ANV_DESCRIPTOR_SET_PER_PRIM_PADDING) {
fs_stage->bind_map.push_ranges[i].length = MAX2(
fs_stage->prog_data.wm.num_per_primitive_inputs / 2,
fs_stage->bind_map.push_ranges[i].length);
break;
}
}
}
static void

7
src/intel/vulkan/anv_pipeline_cache.c
View file

@ -272,7 +272,12 @@ anv_shader_bin_create(struct anv_device *device,
prog_data_in->const_data_offset;
int rv_count = 0;
struct brw_shader_reloc_value reloc_values[10];
struct brw_shader_reloc_value reloc_values[11];
assert((device->physical->va.instruction_state_pool.addr & 0xffffffff) == 0);
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_INSTRUCTION_BASE_ADDR_HIGH,
.value = device->physical->va.instruction_state_pool.addr >> 32,
};
assert((device->physical->va.dynamic_visible_pool.addr & 0xffffffff) == 0);
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_DESCRIPTORS_BUFFER_ADDR_HIGH,

4
src/intel/vulkan/anv_private.h
View file

@ -3836,6 +3836,8 @@ struct anv_push_constants {
/** Robust access pushed registers. */
uint64_t push_reg_mask[MESA_SHADER_STAGES];
uint32_t fs_per_prim_remap_offset;
} gfx;
struct {
@ -5002,6 +5004,8 @@ struct anv_graphics_pipeline {
uint32_t view_mask;
uint32_t instance_multiplier;
/* First VUE slot read by SBE */
uint32_t first_vue_slot;
/* Attribute index of the PrimitiveID in the delivered attributes */
uint32_t primitive_id_index;

13
src/intel/vulkan/genX_cmd_draw.c
View file

@ -497,6 +497,11 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
if (gfx_state->base.push_constants_data_dirty || GFX_VER < 12)
gfx_state->base.push_constants_state = ANV_STATE_NULL;
#if GFX_VERx10 >= 125
const struct brw_mesh_prog_data *mesh_prog_data =
get_mesh_prog_data(pipeline);
#endif
anv_foreach_stage(stage, dirty_stages) {
unsigned buffer_count = 0;
flushed |= mesa_to_vk_shader_stage(stage);
@ -519,9 +524,15 @@ cmd_buffer_flush_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer,
if (range->length == 0)
break;
#if GFX_VERx10 >= 125
/* Padding for Mesh only matters where the platform supports Mesh
* shaders.
*/
if (range->set == ANV_DESCRIPTOR_SET_PER_PRIM_PADDING &&
anv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
mesh_prog_data && !mesh_prog_data->map.wa_18019110168_active) {
break;
}
#endif
buffers[i] = get_push_range_address(cmd_buffer, shader, range);
max_push_range = MAX2(max_push_range, range->length);

13
src/intel/vulkan/genX_gfx_state.c
View file

@ -786,6 +786,8 @@ update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state,
if (!brw_wm_prog_data_is_dynamic(wm_prog_data))
return;
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
enum intel_msaa_flags fs_msaa_flags =
intel_fs_msaa_flags((struct intel_fs_params) {
.shader_sample_shading = wm_prog_data->sample_shading,
@ -795,7 +797,10 @@ update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state,
.coarse_pixel = !vk_fragment_shading_rate_is_disabled(&dyn->fsr),
.alpha_to_coverage = dyn->ms.alpha_to_coverage_enable,
.provoking_vertex_last = dyn->rs.provoking_vertex == VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT,
.first_vue_slot = pipeline->first_vue_slot,
.primitive_id_index = pipeline->primitive_id_index,
.per_primitive_remapping = mesh_prog_data &&
mesh_prog_data->map.wa_18019110168_active,
});
SET(FS_MSAA_FLAGS, fs_msaa_flags, fs_msaa_flags);
@ -2307,6 +2312,14 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_FS_MSAA_FLAGS)) {
push_consts->gfx.fs_msaa_flags = hw_state->fs_msaa_flags;
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
if (mesh_prog_data) {
push_consts->gfx.fs_per_prim_remap_offset =
pipeline->base.shaders[MESA_SHADER_MESH]->kernel.offset +
mesh_prog_data->wa_18019110168_mapping_offset;
}
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
gfx->base.push_constants_data_dirty = true;
}

13
src/intel/vulkan/genX_pipeline.c
View file

@ -655,6 +655,8 @@ static void
emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct brw_mesh_prog_data *mesh_prog_data =
get_mesh_prog_data(pipeline);
UNUSED const struct anv_device *device = pipeline->base.base.device;
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
@ -677,11 +679,15 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
int max_source_attr = 0;
uint32_t vertex_read_offset, vertex_read_length, vertex_varyings, flat_inputs;
brw_compute_sbe_per_vertex_urb_read(
vue_map, anv_pipeline_is_mesh(pipeline), false, wm_prog_data,
vue_map, mesh_prog_data != NULL,
mesh_prog_data ? mesh_prog_data->map.wa_18019110168_active : false,
wm_prog_data,
&vertex_read_offset, &vertex_read_length, &vertex_varyings,
&pipeline->primitive_id_index,
&flat_inputs);
pipeline->first_vue_slot = vertex_read_offset * 2;
sbe.AttributeSwizzleEnable = anv_pipeline_is_primitive(pipeline);
sbe.PointSpriteTextureCoordinateOrigin = UPPERLEFT;
sbe.ConstantInterpolationEnable = flat_inputs;
@ -766,12 +772,9 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
if (device->vk.enabled_extensions.EXT_mesh_shader) {
anv_pipeline_emit(pipeline, final.sbe_mesh,
GENX(3DSTATE_SBE_MESH), sbe_mesh) {
if (!anv_pipeline_is_mesh(pipeline))
if (mesh_prog_data == NULL)
continue;
const struct brw_mesh_prog_data *mesh_prog_data =
get_mesh_prog_data(pipeline);
sbe_mesh.PerVertexURBEntryOutputReadOffset = vertex_read_offset;
sbe_mesh.PerVertexURBEntryOutputReadLength = vertex_read_length;