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asahi: clang-format

Browse source 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38245>
This commit is contained in:
Alyssa Rosenzweig 2025-11-04 13:37:12 -05:00 • committed by Marge Bot
parent 9c2a2deee6
commit a72ebeac6d
7 changed files with 19 additions and 17 deletions
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4
src/asahi/lib/agx_device.c
View file

@ -375,8 +375,8 @@ agx_bo_make_shared(struct agx_device *dev, struct agx_bo *bo)
bo->flags |= AGX_BO_SHARED;
assert(bo->prime_fd == -1);
int ret =
drmPrimeHandleToFD(dev->fd, bo->handle, DRM_CLOEXEC | DRM_RDWR, &bo->prime_fd);
int ret = drmPrimeHandleToFD(dev->fd, bo->handle, DRM_CLOEXEC | DRM_RDWR,
&bo->prime_fd);
assert(ret == 0);
assert(bo->prime_fd >= 0);

4
src/asahi/lib/agx_nir_prolog_epilog.c
View file

@ -473,8 +473,8 @@ agx_nir_fs_epilog(nir_builder *b, const void *key_)
/* Alpha-to-coverage must be lowered before alpha-to-one */
if (key->blend.alpha_to_coverage)
NIR_PASS(_, b->shader, nir_lower_alpha_to_coverage, tib.nr_samples,
false, NULL);
NIR_PASS(_, b->shader, nir_lower_alpha_to_coverage, tib.nr_samples, false,
NULL);
/* Depth/stencil writes must be deferred until after all discards,
* particularly alpha-to-coverage.

5
src/asahi/vulkan/hk_cmd_draw.c
View file

@ -986,8 +986,9 @@ hk_CmdEndRendering(VkCommandBuffer commandBuffer)
}
static void
hk_init_heap(const void *data) {
struct hk_cmd_buffer *cmd = (struct hk_cmd_buffer *) data;
hk_init_heap(const void *data)
{
struct hk_cmd_buffer *cmd = (struct hk_cmd_buffer *)data;
struct hk_device *dev = hk_cmd_buffer_device(cmd);
perf_debug(cmd, "Allocating heap");

3
src/asahi/vulkan/hk_device_memory.c
View file

@ -411,7 +411,8 @@ hk_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR *pGetFdInfo,
VKAPI_ATTR uint64_t VKAPI_CALL
hk_GetDeviceMemoryOpaqueCaptureAddress(
UNUSED VkDevice device, UNUSED const VkDeviceMemoryOpaqueCaptureAddressInfo *pInfo)
UNUSED VkDevice device,
UNUSED const VkDeviceMemoryOpaqueCaptureAddressInfo *pInfo)
{
/* Addresses are replayed at buffer and image creation, not memory. */
return 0;

3
src/asahi/vulkan/hk_physical_device.c
View file

@ -936,7 +936,8 @@ hk_get_device_properties(const struct agx_device *dev,
/* VK_KHR_maintenance9 */
.image2DViewOf3DSparse = false,
.defaultVertexAttributeValue = VK_DEFAULT_VERTEX_ATTRIBUTE_VALUE_ZERO_ZERO_ZERO_ONE_KHR,
.defaultVertexAttributeValue =
VK_DEFAULT_VERTEX_ATTRIBUTE_VALUE_ZERO_ZERO_ZERO_ONE_KHR,
/* VK_EXT_map_memory_placed */
.minPlacedMemoryMapAlignment = os_page_size,

3
src/gallium/drivers/asahi/agx_blit.c
View file

@ -284,8 +284,7 @@ asahi_compute_restore(struct agx_context *ctx)
}
/* take_ownership=true so do not unreference */
pctx->set_constant_buffer(pctx, MESA_SHADER_COMPUTE, 0,
&blitter->saved_cb);
pctx->set_constant_buffer(pctx, MESA_SHADER_COMPUTE, 0, &blitter->saved_cb);
blitter->saved_cb.buffer = NULL;
if (blitter->saved_sampler_view) {

14
src/gallium/drivers/asahi/agx_state.c
View file

@ -1300,8 +1300,7 @@ agx_batch_upload_pbe(struct agx_batch *batch, struct agx_pbe_packed *out,
static void
agx_set_constant_buffer(struct pipe_context *pctx, mesa_shader_stage shader,
uint index,
const struct pipe_constant_buffer *cb)
uint index, const struct pipe_constant_buffer *cb)
{
struct agx_context *ctx = agx_context(pctx);
struct agx_stage *s = &ctx->stage[shader];
@ -1312,8 +1311,8 @@ agx_set_constant_buffer(struct pipe_context *pctx, mesa_shader_stage shader,
/* Upload user buffer immediately */
if (constants->user_buffer && !constants->buffer) {
u_upload_data_ref(ctx->base.const_uploader, 0, constants->buffer_size, 64,
constants->user_buffer, &constants->buffer_offset,
&constants->buffer);
constants->user_buffer, &constants->buffer_offset,
&constants->buffer);
}
unsigned mask = (1 << index);
@ -4217,7 +4216,8 @@ agx_draw_without_restart(struct agx_batch *batch,
draw->index_bias, info->start_instance};
u_upload_data_ref(ctx->base.const_uploader, 0, sizeof(desc), 4, &desc,
&indirect_synthesized.offset, &indirect_synthesized.buffer);
&indirect_synthesized.offset,
&indirect_synthesized.buffer);
indirect = &indirect_synthesized;
} else {
@ -4434,8 +4434,8 @@ util_draw_multi_upload_indirect(struct pipe_context *pctx,
{
struct pipe_draw_indirect_info indirect_ = *indirect;
u_upload_data_ref(pctx->const_uploader, 0, 4, 4, &indirect->draw_count,
&indirect_.indirect_draw_count_offset,
&indirect_.indirect_draw_count);
&indirect_.indirect_draw_count_offset,
&indirect_.indirect_draw_count);
pctx->draw_vbo(pctx, info, 0, &indirect_, draws, 1);
}