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genxml: Rename two MCS fields to Auxiliary Surface on gen7

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This makes gen7 more consistent with gen8+

Reviewed-by: Chad Versace <chadversary@chromium.org>
This commit is contained in:
Jason Ekstrand 2017-03-24 13:50:34 -07:00
parent c03f6f12bb
commit a6df637d26
3 changed files with 7 additions and 8 deletions
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4
src/intel/genxml/gen7.xml
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@ -672,8 +672,8 @@
<field name="MIP Count / LOD" start="160" end="163" type="uint"/>
<field name="Append Counter Address" start="198" end="223" type="address"/>
<field name="Append Counter Enable" start="193" end="193" type="bool"/>
<field name="MCS Base Address" start="204" end="223" type="address"/>
<field name="MCS Surface Pitch" start="195" end="203" type="uint"/>
<field name="Auxiliary Surface Base Address" start="204" end="223" type="address"/>
<field name="Auxiliary Surface Pitch" start="195" end="203" type="uint"/>
<field name="MCS Enable" start="192" end="192" type="bool"/>
<field name="Reserved: MBZ" start="222" end="223" type="uint"/>
<field name="X Offset for UV Plane" start="208" end="221" type="uint"/>

4
src/intel/genxml/gen75.xml
View file

@ -683,8 +683,8 @@
<field name="MIP Count / LOD" start="160" end="163" type="uint"/>
<field name="Append Counter Address" start="198" end="223" type="address"/>
<field name="Append Counter Enable" start="193" end="193" type="bool"/>
<field name="MCS Base Address" start="204" end="223" type="address"/>
<field name="MCS Surface Pitch" start="195" end="203" type="uint"/>
<field name="Auxiliary Surface Base Address" start="204" end="223" type="address"/>
<field name="Auxiliary Surface Pitch" start="195" end="203" type="uint"/>
<field name="MCS Enable" start="192" end="192" type="bool"/>
<field name="Reserved: MBZ" start="222" end="223" type="uint"/>
<field name="X Offset for UV Plane" start="208" end="221" type="uint"/>

7
src/intel/isl/isl_surface_state.c
View file

@ -548,16 +548,17 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
uint32_t pitch_in_tiles =
info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
s.AuxiliarySurfaceBaseAddress = info->aux_address;
s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
#if GEN_GEN >= 8
assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
/* Auxiliary surfaces in ISL have compressed formats but the hardware
* doesn't expect our definition of the compression, it expects qpitch
* in units of samples on the main surface.
*/
s.AuxiliarySurfaceQPitch =
isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
s.AuxiliarySurfaceBaseAddress = info->aux_address;
if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
/* The number of samples must be 1 */
@ -582,8 +583,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#else
assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
info->aux_usage == ISL_AUX_USAGE_CCS_D);
s.MCSBaseAddress = info->aux_address,
s.MCSSurfacePitch = pitch_in_tiles - 1;
s.MCSEnable = true;
#endif
}