mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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r600: add core pieces of image support.
This adds the atoms and gallium api implementations, along with support for compress/decompress paths for shader images. Tested-By: Gert Wollny <gw.fossdev@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
5689bb0022
commit
a6b3792843
6 changed files with 428 additions and 3 deletions
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@ -1678,6 +1678,104 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples,
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}
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}
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static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
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int immed_id_base, int res_id_base)
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{
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struct r600_image_state *state = (struct r600_image_state *)atom;
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struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
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struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
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struct r600_texture *rtex;
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struct r600_resource *resource;
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uint32_t pkt_flags = 0;
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int i;
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for (i = 0; i < R600_MAX_IMAGES; i++) {
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struct r600_image_view *image = &state->views[i];
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unsigned reloc, immed_reloc;
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int idx = i;
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idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
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if (!image->base.resource)
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continue;
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resource = (struct r600_resource *)image->base.resource;
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if (resource->b.b.target != PIPE_BUFFER)
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rtex = (struct r600_texture *)image->base.resource;
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else
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rtex = NULL;
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reloc = radeon_add_to_buffer_list(&rctx->b,
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&rctx->b.gfx,
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resource,
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RADEON_USAGE_READWRITE,
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RADEON_PRIO_SHADER_RW_BUFFER);
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immed_reloc = radeon_add_to_buffer_list(&rctx->b,
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&rctx->b.gfx,
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resource->immed_buffer,
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RADEON_USAGE_READWRITE,
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RADEON_PRIO_SHADER_RW_BUFFER);
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radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
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radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
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radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
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radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
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radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
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radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
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radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
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radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
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radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
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radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
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radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
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radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
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radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
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radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
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radeon_emit(cs, reloc);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
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radeon_emit(cs, reloc);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
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radeon_emit(cs, reloc);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
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radeon_emit(cs, reloc);
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radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
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radeon_emit(cs, immed_reloc);
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radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
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radeon_emit(cs, (immed_id_base + i) * 8);
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radeon_emit_array(cs, image->immed_resource_words, 8);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
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radeon_emit(cs, immed_reloc);
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radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
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radeon_emit(cs, (res_id_base + i) * 8);
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radeon_emit_array(cs, image->resource_words, 8);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
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radeon_emit(cs, reloc);
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if (!image->skip_mip_address_reloc) {
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
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radeon_emit(cs, reloc);
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}
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}
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}
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static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
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{
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evergreen_emit_image_state(rctx, atom,
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R600_IMAGE_IMMED_RESOURCE_OFFSET,
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R600_IMAGE_REAL_RESOURCE_OFFSET);
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}
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static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
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{
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struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
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@ -1753,6 +1851,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
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cb->cb_color_info | tex->cb_color_info);
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i++;
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}
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i += util_bitcount(rctx->fragment_images.enabled_mask);
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for (; i < 8 ; i++)
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radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
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for (; i < 12; i++)
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@ -1867,9 +1966,9 @@ static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_
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struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
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unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
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unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
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unsigned rat_colormask = ((1ULL << ((unsigned)a->nr_image_rats * 4)) - 1) << (a->nr_cbufs * 4);
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radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
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radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
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radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
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/* This must match the used export instructions exactly.
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* Other values may lead to undefined behavior and hangs.
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*/
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@ -3772,6 +3871,195 @@ static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
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}
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}
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static void evergreen_set_shader_images(struct pipe_context *ctx,
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enum pipe_shader_type shader, unsigned start_slot,
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unsigned count,
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const struct pipe_image_view *images)
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{
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struct r600_context *rctx = (struct r600_context *)ctx;
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struct r600_screen *rscreen = (struct r600_screen *)ctx->screen;
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int i;
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struct r600_image_view *rview;
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struct pipe_resource *image;
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struct r600_resource *resource;
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struct r600_tex_color_info color;
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struct eg_buf_res_params buf_params;
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struct eg_tex_res_params tex_params;
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unsigned old_mask;
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bool skip_reloc = false;
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struct r600_image_state *istate = NULL;
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int idx;
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if (shader != PIPE_SHADER_FRAGMENT && count == 0)
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return;
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istate = &rctx->fragment_images;
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assert (shader == PIPE_SHADER_FRAGMENT);
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old_mask = istate->enabled_mask;
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for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
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unsigned res_type;
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const struct pipe_image_view *iview;
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rview = &istate->views[i];
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if (!images || !images[idx].resource) {
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pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
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istate->enabled_mask &= ~(1 << i);
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continue;
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}
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iview = &images[idx];
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image = iview->resource;
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resource = (struct r600_resource *)image;
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r600_context_add_resource_size(ctx, image);
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rview->base = *iview;
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rview->base.resource = NULL;
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pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
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if (!resource->immed_buffer) {
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int immed_size = (rscreen->b.info.max_se * 256 * 64) * util_format_get_blocksize(iview->format);
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eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
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}
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bool is_buffer = image->target == PIPE_BUFFER;
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struct r600_texture *rtex = (struct r600_texture *)image;
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if (!is_buffer & rtex->db_compatible)
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istate->compressed_depthtex_mask |= 1 << i;
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else
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istate->compressed_depthtex_mask &= ~(1 << i);
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if (!is_buffer && rtex->cmask.size)
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istate->compressed_colortex_mask |= 1 << i;
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else
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istate->compressed_colortex_mask &= ~(1 << i);
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if (!is_buffer) {
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evergreen_set_color_surface_common(rctx, rtex,
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iview->u.tex.level,
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iview->u.tex.first_layer,
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iview->u.tex.last_layer,
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iview->format,
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&color);
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color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
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S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
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} else {
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color.offset = 0;
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color.view = 0;
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evergreen_set_color_surface_buffer(rctx, resource,
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iview->format,
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iview->u.buf.offset,
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iview->u.buf.size,
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&color);
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}
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switch (image->target) {
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case PIPE_BUFFER:
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res_type = V_028C70_BUFFER;
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break;
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case PIPE_TEXTURE_1D:
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res_type = V_028C70_TEXTURE1D;
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break;
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case PIPE_TEXTURE_1D_ARRAY:
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res_type = V_028C70_TEXTURE1DARRAY;
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break;
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case PIPE_TEXTURE_2D:
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case PIPE_TEXTURE_RECT:
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res_type = V_028C70_TEXTURE2D;
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break;
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case PIPE_TEXTURE_3D:
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res_type = V_028C70_TEXTURE3D;
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break;
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case PIPE_TEXTURE_2D_ARRAY:
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case PIPE_TEXTURE_CUBE:
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case PIPE_TEXTURE_CUBE_ARRAY:
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res_type = V_028C70_TEXTURE2DARRAY;
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break;
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default:
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assert(0);
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res_type = 0;
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break;
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}
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rview->cb_color_base = color.offset;
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rview->cb_color_dim = color.dim;
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rview->cb_color_info = color.info |
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S_028C70_RAT(1) |
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S_028C70_RESOURCE_TYPE(res_type);
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rview->cb_color_pitch = color.pitch;
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rview->cb_color_slice = color.slice;
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rview->cb_color_view = color.view;
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rview->cb_color_attrib = color.attrib;
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rview->cb_color_fmask = color.fmask;
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rview->cb_color_fmask_slice = color.fmask_slice;
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memset(&buf_params, 0, sizeof(buf_params));
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buf_params.pipe_format = iview->format;
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buf_params.size = resource->immed_buffer->b.b.width0;
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buf_params.swizzle[0] = PIPE_SWIZZLE_X;
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buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
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buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
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buf_params.swizzle[3] = PIPE_SWIZZLE_W;
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buf_params.uncached = 1;
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evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
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&buf_params, &skip_reloc,
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rview->immed_resource_words);
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if (image->target != PIPE_BUFFER) {
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memset(&tex_params, 0, sizeof(tex_params));
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tex_params.pipe_format = iview->format;
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tex_params.force_level = 0;
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tex_params.width0 = image->width0;
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tex_params.height0 = image->height0;
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tex_params.first_level = iview->u.tex.level;
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tex_params.last_level = iview->u.tex.level;
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tex_params.first_layer = iview->u.tex.first_layer;
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tex_params.last_layer = iview->u.tex.last_layer;
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tex_params.target = image->target;
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tex_params.swizzle[0] = PIPE_SWIZZLE_X;
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tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
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tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
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tex_params.swizzle[3] = PIPE_SWIZZLE_W;
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evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
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&rview->skip_mip_address_reloc,
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rview->resource_words);
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} else {
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memset(&buf_params, 0, sizeof(buf_params));
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buf_params.pipe_format = iview->format;
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buf_params.size = iview->u.buf.size;
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buf_params.offset = iview->u.buf.offset;
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buf_params.swizzle[0] = PIPE_SWIZZLE_X;
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buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
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buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
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buf_params.swizzle[3] = PIPE_SWIZZLE_W;
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evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
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&buf_params,
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&rview->skip_mip_address_reloc,
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rview->resource_words);
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}
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istate->enabled_mask |= (1 << i);
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}
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istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
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istate->dirty_buffer_constants = TRUE;
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rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
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R600_CONTEXT_FLUSH_AND_INV_CB_META;
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if (old_mask != istate->enabled_mask)
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r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
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if (rctx->cb_misc_state.nr_image_rats != util_bitcount(istate->enabled_mask)) {
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rctx->cb_misc_state.nr_image_rats = util_bitcount(istate->enabled_mask);
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r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
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}
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r600_mark_atom_dirty(rctx, &istate->atom);
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}
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void evergreen_init_state_functions(struct r600_context *rctx)
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{
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unsigned id = 1;
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@ -3790,6 +4078,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
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rctx->config_state.dyn_gpr_enabled = true;
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}
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r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
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r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
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/* shader const */
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r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
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r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
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@ -3858,6 +4147,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
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rctx->b.b.set_min_samples = evergreen_set_min_samples;
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rctx->b.b.set_tess_state = evergreen_set_tess_state;
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rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
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rctx->b.b.set_shader_images = evergreen_set_shader_images;
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if (rctx->b.chip_class == EVERGREEN)
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rctx->b.b.get_sample_position = evergreen_get_sample_position;
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else
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@ -291,6 +291,40 @@ void r600_decompress_depth_textures(struct r600_context *rctx,
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}
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}
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void r600_decompress_depth_images(struct r600_context *rctx,
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struct r600_image_state *images)
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{
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unsigned i;
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unsigned depth_texture_mask = images->compressed_depthtex_mask;
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while (depth_texture_mask) {
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struct r600_image_view *view;
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struct r600_texture *tex;
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i = u_bit_scan(&depth_texture_mask);
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view = &images->views[i];
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assert(view);
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tex = (struct r600_texture *)view->base.resource;
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assert(tex->db_compatible);
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if (r600_can_sample_zs(tex, false)) {
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r600_blit_decompress_depth_in_place(rctx, tex,
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false,
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view->base.u.tex.level,
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view->base.u.tex.level,
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0, util_max_layer(&tex->resource.b.b, view->base.u.tex.level));
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} else {
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||||
r600_blit_decompress_depth(&rctx->b.b, tex, NULL,
|
||||
view->base.u.tex.level,
|
||||
view->base.u.tex.level,
|
||||
0, util_max_layer(&tex->resource.b.b, view->base.u.tex.level),
|
||||
0, u_max_sample(&tex->resource.b.b));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void r600_blit_decompress_color(struct pipe_context *ctx,
|
||||
struct r600_texture *rtex,
|
||||
unsigned first_level, unsigned last_level,
|
||||
|
|
@ -360,6 +394,31 @@ void r600_decompress_color_textures(struct r600_context *rctx,
|
|||
}
|
||||
}
|
||||
|
||||
void r600_decompress_color_images(struct r600_context *rctx,
|
||||
struct r600_image_state *images)
|
||||
{
|
||||
unsigned i;
|
||||
unsigned mask = images->compressed_colortex_mask;
|
||||
|
||||
while (mask) {
|
||||
struct r600_image_view *view;
|
||||
struct r600_texture *tex;
|
||||
|
||||
i = u_bit_scan(&mask);
|
||||
|
||||
view = &images->views[i];
|
||||
assert(view);
|
||||
|
||||
tex = (struct r600_texture *)view->base.resource;
|
||||
assert(tex->cmask.size);
|
||||
|
||||
r600_blit_decompress_color(&rctx->b.b, tex,
|
||||
view->base.u.tex.level, view->base.u.tex.level,
|
||||
view->base.u.tex.first_layer,
|
||||
view->base.u.tex.last_layer);
|
||||
}
|
||||
}
|
||||
|
||||
/* Helper for decompressing a portion of a color or depth resource before
|
||||
* blitting if any decompression is needed.
|
||||
* The driver doesn't decompress resources automatically while u_blitter is
|
||||
|
|
|
|||
|
|
@ -348,6 +348,8 @@ void r600_begin_new_cs(struct r600_context *ctx)
|
|||
r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
|
||||
r600_mark_atom_dirty(ctx, &ctx->db_state.atom);
|
||||
r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
|
||||
if (ctx->b.chip_class >= EVERGREEN)
|
||||
r600_mark_atom_dirty(ctx, &ctx->fragment_images.atom);
|
||||
r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_PS].atom);
|
||||
r600_mark_atom_dirty(ctx, &ctx->poly_offset_state.atom);
|
||||
r600_mark_atom_dirty(ctx, &ctx->vgt_state.atom);
|
||||
|
|
|
|||
|
|
@ -38,7 +38,16 @@
|
|||
|
||||
#include "tgsi/tgsi_scan.h"
|
||||
|
||||
#define R600_NUM_ATOMS 52
|
||||
#define R600_NUM_ATOMS 53
|
||||
|
||||
#define R600_MAX_IMAGES 8
|
||||
/*
|
||||
* ranges reserved for images on evergreen
|
||||
* first set for the immediate buffers,
|
||||
* second for the actual resources for RESQ.
|
||||
*/
|
||||
#define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
|
||||
#define R600_IMAGE_REAL_RESOURCE_OFFSET 168
|
||||
|
||||
/* read caches */
|
||||
#define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
|
||||
|
|
@ -135,6 +144,7 @@ struct r600_cb_misc_state {
|
|||
unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
|
||||
unsigned nr_cbufs;
|
||||
unsigned nr_ps_color_outputs;
|
||||
unsigned nr_image_rats;
|
||||
bool multiwrite;
|
||||
bool dual_src_blend;
|
||||
};
|
||||
|
|
@ -425,6 +435,33 @@ struct r600_atomic_buffer_state {
|
|||
struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
|
||||
};
|
||||
|
||||
struct r600_image_view {
|
||||
struct pipe_image_view base;
|
||||
uint32_t cb_color_base;
|
||||
uint32_t cb_color_pitch;
|
||||
uint32_t cb_color_slice;
|
||||
uint32_t cb_color_view;
|
||||
uint32_t cb_color_info;
|
||||
uint32_t cb_color_attrib;
|
||||
uint32_t cb_color_dim;
|
||||
uint32_t cb_color_fmask;
|
||||
uint32_t cb_color_fmask_slice;
|
||||
uint32_t immed_resource_words[8];
|
||||
uint32_t resource_words[8];
|
||||
bool skip_mip_address_reloc;
|
||||
uint32_t buf_size;
|
||||
};
|
||||
|
||||
struct r600_image_state {
|
||||
struct r600_atom atom;
|
||||
uint32_t enabled_mask;
|
||||
uint32_t dirty_mask;
|
||||
uint32_t compressed_depthtex_mask;
|
||||
uint32_t compressed_colortex_mask;
|
||||
boolean dirty_buffer_constants;
|
||||
struct r600_image_view views[R600_MAX_IMAGES];
|
||||
};
|
||||
|
||||
struct r600_context {
|
||||
struct r600_common_context b;
|
||||
struct r600_screen *screen;
|
||||
|
|
@ -480,6 +517,8 @@ struct r600_context {
|
|||
struct r600_stencil_ref_state stencil_ref;
|
||||
struct r600_vgt_state vgt_state;
|
||||
struct r600_atomic_buffer_state atomic_buffer_state;
|
||||
/* only have images on fragment shader */
|
||||
struct r600_image_state fragment_images;
|
||||
/* Shaders and shader resources. */
|
||||
struct r600_cso_state vertex_fetch_shader;
|
||||
struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
|
||||
|
|
@ -648,8 +687,12 @@ bool evergreen_adjust_gprs(struct r600_context *rctx);
|
|||
void r600_init_blit_functions(struct r600_context *rctx);
|
||||
void r600_decompress_depth_textures(struct r600_context *rctx,
|
||||
struct r600_samplerview_state *textures);
|
||||
void r600_decompress_depth_images(struct r600_context *rctx,
|
||||
struct r600_image_state *images);
|
||||
void r600_decompress_color_textures(struct r600_context *rctx,
|
||||
struct r600_samplerview_state *textures);
|
||||
void r600_decompress_color_images(struct r600_context *rctx,
|
||||
struct r600_image_state *images);
|
||||
void r600_resource_copy_region(struct pipe_context *ctx,
|
||||
struct pipe_resource *dst,
|
||||
unsigned dst_level,
|
||||
|
|
|
|||
|
|
@ -118,6 +118,7 @@ struct r600_shader {
|
|||
boolean uses_atomics;
|
||||
boolean uses_images;
|
||||
uint8_t atomic_base;
|
||||
uint8_t rat_base;
|
||||
};
|
||||
|
||||
union r600_shader_key {
|
||||
|
|
|
|||
|
|
@ -753,6 +753,26 @@ static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
|
|||
return value;
|
||||
}
|
||||
|
||||
static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
|
||||
{
|
||||
uint32_t mask = images->enabled_mask;
|
||||
|
||||
while (mask) {
|
||||
unsigned i = u_bit_scan(&mask);
|
||||
struct pipe_resource *res = images->views[i].base.resource;
|
||||
|
||||
if (res && res->target != PIPE_BUFFER) {
|
||||
struct r600_texture *rtex = (struct r600_texture *)res;
|
||||
|
||||
if (rtex->cmask.size) {
|
||||
images->compressed_colortex_mask |= 1 << i;
|
||||
} else {
|
||||
images->compressed_colortex_mask &= ~(1 << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Compute the key for the hw shader variant */
|
||||
static inline void r600_shader_selector_key(const struct pipe_context *ctx,
|
||||
const struct r600_pipe_shader_selector *sel,
|
||||
|
|
@ -1473,6 +1493,7 @@ static void r600_update_compressed_resource_state(struct r600_context *rctx)
|
|||
for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
|
||||
r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
|
||||
}
|
||||
r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
|
||||
}
|
||||
|
||||
/* Decompress textures if needed. */
|
||||
|
|
@ -1485,6 +1506,15 @@ static void r600_update_compressed_resource_state(struct r600_context *rctx)
|
|||
r600_decompress_color_textures(rctx, views);
|
||||
}
|
||||
}
|
||||
|
||||
{
|
||||
struct r600_image_state *istate;
|
||||
istate = &rctx->fragment_images;
|
||||
if (istate->compressed_depthtex_mask)
|
||||
r600_decompress_depth_images(rctx, istate);
|
||||
if (istate->compressed_colortex_mask)
|
||||
r600_decompress_color_images(rctx, istate);
|
||||
}
|
||||
}
|
||||
|
||||
#define SELECT_SHADER_OR_FAIL(x) do { \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue