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brw: improve eot_reg computation in register allocate

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c4c7ff3f8f ("brw: enable register allocation to deal with multiple EOTs")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37326>
This commit is contained in:
Lionel Landwerlin 2025-09-12 12:25:54 +03:00 • committed by Marge Bot
parent 1f86a4ee37
commit a69853ce5e
1 changed files with 12 additions and 2 deletions
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14
src/intel/compiler/brw_reg_allocate.cpp
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@ -675,9 +675,19 @@ brw_reg_alloc::setup_inst_interference(const brw_inst *inst)
/* All the EOT messages should have the same amount of payload as we
* only use this for last render target write on Gfx11.
*
* Unfortunately opt_register_coalesce can merge 2 registers of
* different sizes (effectively increasing the allocated size of one of
* the EOT SEND sources). If that register gets spilled, the spiller
* might reduce the size of the register since it sees some of it is
* unused. This leads to the computed sizes[] values to change as we
* register allocate the program.
*
* Here we stick to the largest EOT size found during register
* allocation.
*/
assert(eot_reg == -1 || eot_reg == MIN2(regs[0], regs[1]));
eot_reg = MIN2(regs[0], regs[1]);
assert(eot_reg == -1 || eot_reg <= MIN2(regs[0], regs[1]));
eot_reg = MIN3(eot_reg == -1 ? BRW_MAX_GRF : eot_reg, regs[0], regs[1]);
}
}