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radv: introduce new radv_pipeline_stage structure

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This is used to store everything for a pipeline stage like the module,
the NIR, the shader arguments etc. This is inspired from ANV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15794>
This commit is contained in:
Samuel Pitoiset 2022-04-05 13:09:35 +02:00 • committed by Marge Bot
parent 86b1a1d5f2
commit a652c1653a
5 changed files with 462 additions and 437 deletions
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786
src/amd/vulkan/radv_pipeline.c
View file

File diff suppressed because it is too large Load diff

16
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -810,14 +810,22 @@ convert_rt_stage(VkShaderStageFlagBits vk_stage)
}
static nir_shader *
parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreateInfo *stage)
parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreateInfo *sinfo)
{
struct radv_pipeline_key key;
memset(&key, 0, sizeof(key));
nir_shader *shader = radv_shader_compile_to_nir(
device, vk_shader_module_from_handle(stage->module), stage->pName,
convert_rt_stage(stage->stage), stage->pSpecializationInfo, &key);
struct radv_pipeline_stage rt_stage = {
.stage = convert_rt_stage(sinfo->stage),
.module = vk_shader_module_from_handle(sinfo->module),
.entrypoint = sinfo->pName,
.spec_info = sinfo->pSpecializationInfo,
.feedback = {
.flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT,
},
};
nir_shader *shader = radv_shader_compile_to_nir(device, &rt_stage, &key);
if (shader->info.stage == MESA_SHADER_RAYGEN || shader->info.stage == MESA_SHADER_CLOSEST_HIT ||
shader->info.stage == MESA_SHADER_CALLABLE || shader->info.stage == MESA_SHADER_MISS) {

16
src/amd/vulkan/radv_private.h
View file

@ -79,6 +79,7 @@
#include "radv_descriptor_set.h"
#include "radv_radeon_winsys.h"
#include "radv_shader.h"
#include "radv_shader_args.h"
#include "sid.h"
/* Pre-declarations needed for WSI entrypoints */
@ -1924,6 +1925,21 @@ struct radv_pipeline {
uint32_t dynamic_offset_count;
};
struct radv_pipeline_stage {
gl_shader_stage stage;
struct vk_shader_module *module;
const char *entrypoint;
const VkSpecializationInfo *spec_info;
nir_shader *nir;
struct radv_shader_info info;
struct radv_shader_args args;
VkPipelineCreationFeedbackEXT feedback;
};
static inline bool
radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
{

57
src/amd/vulkan/radv_shader.c
View file

@ -468,9 +468,11 @@ radv_force_primitive_shading_rate(nir_shader *nir, struct radv_device *device)
}
bool
radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_info *info,
const struct radv_shader_args *args, const struct radv_pipeline_key *key)
radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_stage,
const struct radv_pipeline_key *key)
{
const struct radv_shader_info *info = &fs_stage->info;
const struct radv_shader_args *args = &fs_stage->args;
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
bool progress = false;
@ -551,17 +553,17 @@ radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_info *info,
}
nir_shader *
radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *module,
const char *entrypoint_name, gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipeline_stage *stage,
const struct radv_pipeline_key *key)
{
struct vk_shader_module *module = stage->module;
unsigned subgroup_size = 64, ballot_bit_size = 64;
if (key->cs.compute_subgroup_size) {
/* Only compute shaders currently support requiring a
* specific subgroup size.
*/
assert(stage == MESA_SHADER_COMPUTE);
assert(stage->stage == MESA_SHADER_COMPUTE);
subgroup_size = key->cs.compute_subgroup_size;
ballot_bit_size = key->cs.compute_subgroup_size;
}
@ -574,7 +576,7 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
* and just use the NIR shader. We don't want to alter meta and RT
* shaders IR directly, so clone it first. */
nir = nir_shader_clone(NULL, module->nir);
nir->options = &device->physical_device->nir_options[stage];
nir->options = &device->physical_device->nir_options[stage->stage];
nir_validate_shader(nir, "in internal shader");
assert(exec_list_length(&nir->functions) == 1);
@ -587,7 +589,7 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
uint32_t num_spec_entries = 0;
struct nir_spirv_specialization *spec_entries =
vk_spec_info_to_nir_spirv(spec_info, &num_spec_entries);
vk_spec_info_to_nir_spirv(stage->spec_info, &num_spec_entries);
struct radv_shader_debug_data spirv_debug_data = {
.device = device,
.module = module,
@ -668,10 +670,10 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
.private_data = &spirv_debug_data,
},
};
nir = spirv_to_nir(spirv, module->size / 4, spec_entries, num_spec_entries, stage,
entrypoint_name, &spirv_options,
&device->physical_device->nir_options[stage]);
assert(nir->info.stage == stage);
nir = spirv_to_nir(spirv, module->size / 4, spec_entries, num_spec_entries, stage->stage,
stage->entrypoint, &spirv_options,
&device->physical_device->nir_options[stage->stage]);
assert(nir->info.stage == stage->stage);
nir_validate_shader(nir, "after spirv_to_nir");
free(spec_entries);
@ -781,7 +783,7 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
if (nir->info.stage == MESA_SHADER_GEOMETRY) {
unsigned nir_gs_flags = nir_lower_gs_intrinsics_per_stream;
if (key->use_ngg && !radv_use_llvm_for_stage(device, stage)) {
if (key->use_ngg && !radv_use_llvm_for_stage(device, stage->stage)) {
/* ACO needs NIR to do some of the hard lifting */
nir_gs_flags |= nir_lower_gs_intrinsics_count_primitives |
nir_lower_gs_intrinsics_count_vertices_per_primitive |
@ -1002,9 +1004,12 @@ radv_lower_io(struct radv_device *device, nir_shader *nir)
}
bool
radv_lower_io_to_mem(struct radv_device *device, struct nir_shader *nir,
const struct radv_shader_info *info, const struct radv_pipeline_key *pl_key)
radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *stage,
const struct radv_pipeline_key *pl_key)
{
const struct radv_shader_info *info = &stage->info;
nir_shader *nir = stage->nir;
if (nir->info.stage == MESA_SHADER_VERTEX) {
if (info->vs.as_ls) {
ac_nir_lower_ls_outputs_to_mem(nir, info->vs.tcs_in_out_eq,
@ -1104,10 +1109,12 @@ radv_consider_culling(struct radv_device *device, struct nir_shader *nir, uint64
return true;
}
void radv_lower_ngg(struct radv_device *device, struct nir_shader *nir,
const struct radv_shader_info *info,
void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_stage,
const struct radv_pipeline_key *pl_key)
{
const struct radv_shader_info *info = &ngg_stage->info;
nir_shader *nir = ngg_stage->nir;
/* TODO: support the LLVM backend with the NIR lowering */
assert(!radv_use_llvm_for_stage(device, nir->info.stage));
@ -2008,11 +2015,10 @@ shader_compile(struct radv_device *device, struct nir_shader *const *shaders, in
}
struct radv_shader *
radv_shader_compile(struct radv_device *device, struct nir_shader *const *shaders, int shader_count,
const struct radv_pipeline_key *key,
struct radv_shader_info *info, const struct radv_shader_args *args,
bool keep_shader_info, bool keep_statistic_info,
struct radv_shader_binary **binary_out)
radv_shader_compile(struct radv_device *device, struct radv_pipeline_stage *pl_stage,
struct nir_shader *const *shaders, int shader_count,
const struct radv_pipeline_key *key, bool keep_shader_info,
bool keep_statistic_info, struct radv_shader_binary **binary_out)
{
gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
struct radv_nir_compiler_options options = {0};
@ -2021,10 +2027,11 @@ radv_shader_compile(struct radv_device *device, struct nir_shader *const *shader
options.key = *key;
options.robust_buffer_access = device->robust_buffer_access;
options.wgp_mode = radv_should_use_wgp_mode(device, stage, info);
options.wgp_mode = radv_should_use_wgp_mode(device, stage, &pl_stage->info);
return shader_compile(device, shaders, shader_count, stage, info, args, &options, false,
false, keep_shader_info, keep_statistic_info, binary_out);
return shader_compile(device, shaders, shader_count, stage, &pl_stage->info,
&pl_stage->args, &options, false, false, keep_shader_info,
keep_statistic_info, binary_out);
}
struct radv_shader *

24
src/amd/vulkan/radv_shader.h
View file

@ -513,9 +513,10 @@ void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *devi
const struct radv_shader_info *info,
const struct radv_shader_args *args);
nir_shader *radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *module,
const char *entrypoint_name, gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
struct radv_pipeline_stage;
nir_shader *radv_shader_compile_to_nir(struct radv_device *device,
const struct radv_pipeline_stage *stage,
const struct radv_pipeline_key *key);
void radv_init_shader_arenas(struct radv_device *device);
@ -537,10 +538,9 @@ struct radv_shader *radv_shader_create(struct radv_device *device,
bool keep_shader_info, bool from_cache,
const struct radv_shader_args *args);
struct radv_shader *radv_shader_compile(
struct radv_device *device, struct nir_shader *const *shaders, int shader_count,
const struct radv_pipeline_key *key,
struct radv_shader_info *info, const struct radv_shader_args *args, bool keep_shader_info,
bool keep_statistic_info, struct radv_shader_binary **binary_out);
struct radv_device *device, struct radv_pipeline_stage *stage, struct nir_shader *const *shaders,
int shader_count, const struct radv_pipeline_key *key, bool keep_shader_info, bool keep_statistic_info,
struct radv_shader_binary **binary_out);
bool radv_shader_binary_upload(struct radv_device *device, const struct radv_shader_binary *binary,
struct radv_shader *shader, void *dest_ptr);
@ -665,11 +665,10 @@ get_tcs_num_patches(unsigned tcs_num_input_vertices, unsigned tcs_num_output_ver
void radv_lower_io(struct radv_device *device, nir_shader *nir);
bool radv_lower_io_to_mem(struct radv_device *device, struct nir_shader *nir,
const struct radv_shader_info *info, const struct radv_pipeline_key *pl_key);
bool radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *stage,
const struct radv_pipeline_key *pl_key);
void radv_lower_ngg(struct radv_device *device, struct nir_shader *nir,
const struct radv_shader_info *info,
void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_stage,
const struct radv_pipeline_key *pl_key);
bool radv_consider_culling(struct radv_device *device, struct nir_shader *nir,
@ -680,8 +679,7 @@ void radv_get_nir_options(struct radv_physical_device *device);
bool radv_force_primitive_shading_rate(nir_shader *nir, struct radv_device *device);
bool radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_info *info,
const struct radv_shader_args *args,
bool radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_stage,
const struct radv_pipeline_key *key);
#endif