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intel/compiler: Remove virtual calls from scheduler
Pull run() and schedule_instructions() for fs, and pull a very simplified version of those into a run() for vec4. Because of the previous patches the duplication is small. Since we are touching these, change run() implementations to use the cfg from the existing reference to the visitor/shader instead of taking one as argument. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25841>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
d76d58cf50
commit
a6297d05ca
1 changed files with 44 additions and 53 deletions
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@ -705,23 +705,12 @@ public:
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void add_dep(schedule_node *before, schedule_node *after, int latency);
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void add_dep(schedule_node *before, schedule_node *after);
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void run(cfg_t *cfg);
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void set_current_block(bblock_t *block);
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void compute_delays();
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void compute_exits();
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virtual void calculate_deps() = 0;
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virtual schedule_node *choose_instruction_to_schedule() = 0;
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virtual int issue_time(backend_instruction *inst) = 0;
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virtual void count_reads_remaining(backend_instruction *inst) = 0;
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virtual void setup_liveness(cfg_t *cfg) = 0;
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virtual void update_register_pressure(backend_instruction *inst) = 0;
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virtual int get_register_pressure_benefit(backend_instruction *inst) = 0;
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void schedule(schedule_node *chosen);
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void update_children(schedule_node *chosen);
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void schedule_instructions();
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void *mem_ctx;
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linear_ctx *lin_ctx;
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@ -813,7 +802,7 @@ public:
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void calculate_deps();
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bool is_compressed(const fs_inst *inst);
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schedule_node *choose_instruction_to_schedule();
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int issue_time(backend_instruction *inst);
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int calculate_issue_time(backend_instruction *inst);
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const fs_visitor *v;
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void count_reads_remaining(backend_instruction *inst);
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@ -821,6 +810,9 @@ public:
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void update_register_pressure(backend_instruction *inst);
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int get_register_pressure_benefit(backend_instruction *inst);
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void clear_last_grf_write();
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void schedule_instructions();
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void run();
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};
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fs_instruction_scheduler::fs_instruction_scheduler(const fs_visitor *v,
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@ -993,13 +985,9 @@ public:
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vec4_instruction_scheduler(const vec4_visitor *v, int grf_count);
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void calculate_deps();
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schedule_node *choose_instruction_to_schedule();
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int issue_time(backend_instruction *inst);
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const vec4_visitor *v;
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void count_reads_remaining(backend_instruction *inst);
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void setup_liveness(cfg_t *cfg);
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void update_register_pressure(backend_instruction *inst);
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int get_register_pressure_benefit(backend_instruction *inst);
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void run();
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};
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vec4_instruction_scheduler::vec4_instruction_scheduler(const vec4_visitor *v,
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@ -1009,27 +997,6 @@ vec4_instruction_scheduler::vec4_instruction_scheduler(const vec4_visitor *v,
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{
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}
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void
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vec4_instruction_scheduler::count_reads_remaining(backend_instruction *)
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{
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}
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void
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vec4_instruction_scheduler::setup_liveness(cfg_t *)
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{
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}
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void
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vec4_instruction_scheduler::update_register_pressure(backend_instruction *)
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{
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}
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int
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vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *)
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{
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return 0;
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}
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void
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instruction_scheduler::set_current_block(bblock_t *block)
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{
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@ -1839,7 +1806,7 @@ vec4_instruction_scheduler::choose_instruction_to_schedule()
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}
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int
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fs_instruction_scheduler::issue_time(backend_instruction *inst0)
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fs_instruction_scheduler::calculate_issue_time(backend_instruction *inst0)
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{
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const struct brw_isa_info *isa = &v->compiler->isa;
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const fs_inst *inst = static_cast<fs_inst *>(inst0);
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@ -1851,13 +1818,6 @@ fs_instruction_scheduler::issue_time(backend_instruction *inst0)
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return 2 + overhead;
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}
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int
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vec4_instruction_scheduler::issue_time(backend_instruction *)
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{
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/* We always execute as two vec4s in parallel. */
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return 2;
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}
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void
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instruction_scheduler::schedule(schedule_node *chosen)
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{
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@ -1933,7 +1893,7 @@ instruction_scheduler::update_children(schedule_node *chosen)
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}
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void
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instruction_scheduler::schedule_instructions()
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fs_instruction_scheduler::schedule_instructions()
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{
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if (!post_reg_alloc)
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reg_pressure = reg_pressure_in[current.block->num];
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@ -1961,7 +1921,7 @@ instruction_scheduler::schedule_instructions()
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}
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void
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instruction_scheduler::run(cfg_t *cfg)
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fs_instruction_scheduler::run()
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{
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if (debug && !post_reg_alloc) {
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fprintf(stderr, "\nInstructions before scheduling (reg_alloc %d)\n",
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@ -1970,7 +1930,7 @@ instruction_scheduler::run(cfg_t *cfg)
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}
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if (!post_reg_alloc)
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setup_liveness(cfg);
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setup_liveness(v->cfg);
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if (reads_remaining) {
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memset(reads_remaining, 0,
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@ -1980,7 +1940,7 @@ instruction_scheduler::run(cfg_t *cfg)
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memset(written, 0, grf_count * sizeof(*written));
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}
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foreach_block(block, cfg) {
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foreach_block(block, v->cfg) {
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if (reads_remaining) {
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foreach_inst_in_block(fs_inst, inst, block)
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count_reads_remaining(inst);
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@ -1989,7 +1949,7 @@ instruction_scheduler::run(cfg_t *cfg)
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set_current_block(block);
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for (schedule_node *n = current.start; n < current.end; n++)
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n->issue_time = issue_time(n->inst);
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n->issue_time = calculate_issue_time(n->inst);
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calculate_deps();
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@ -2006,6 +1966,37 @@ instruction_scheduler::run(cfg_t *cfg)
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}
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}
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void
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vec4_instruction_scheduler::run()
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{
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foreach_block(block, v->cfg) {
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set_current_block(block);
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for (schedule_node *n = current.start; n < current.end; n++) {
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/* We always execute as two vec4s in parallel. */
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n->issue_time = 2;
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}
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calculate_deps();
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compute_delays();
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compute_exits();
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/* Add DAG heads to the list of available instructions. */
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assert(current.available.is_empty());
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for (schedule_node *n = current.start; n < current.end; n++) {
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if (n->parent_count == 0)
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current.available.push_tail(n);
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}
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while (!current.available.is_empty()) {
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schedule_node *chosen = choose_instruction_to_schedule();
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schedule(chosen);
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update_children(chosen);
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}
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}
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}
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void
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fs_visitor::schedule_instructions(instruction_scheduler_mode mode)
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{
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@ -2020,7 +2011,7 @@ fs_visitor::schedule_instructions(instruction_scheduler_mode mode)
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fs_instruction_scheduler sched(this, grf_count, first_non_payload_grf,
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cfg->num_blocks, mode);
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sched.run(cfg);
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sched.run();
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invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
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}
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@ -2029,7 +2020,7 @@ void
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vec4_visitor::opt_schedule_instructions()
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{
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vec4_instruction_scheduler sched(this, prog_data->total_grf);
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sched.run(cfg);
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sched.run();
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invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
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}
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