From a6292889be750882585ed8223ac7e668d739d8ec Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 17 Jan 2023 16:18:24 +0100 Subject: [PATCH] radv: fix creating BC image views when the base layer is > 0 When the base array layer of the image view is > 0, addrlib computes the offset (in HwlComputeSubResourceOffsetForSwizzlePattern) which is then added to the base VA in RADV. But if the driver doesn't reset the base array layer, the hw will compute incorrect addressing (ie. base array will be added twice). This also matches AMDVLK. This fixes a VM fault followed by a GPU hang on RDNA2 when trying to join a multiplayer game with medium settings in Halo Infinite. Fixes: 98ba1e0d817 ("radv: Fix mipmap views on GFX10+") Signed-off-by: Samuel Pitoiset Part-of: (cherry picked from commit 8d191b2cfb5fbc66321369857c7189c1dbd431fa) --- .pick_status.json | 2 +- src/amd/vulkan/radv_device.c | 4 ++-- src/amd/vulkan/radv_image.c | 6 +++++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 016dd722598..92ae1982497 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -2893,7 +2893,7 @@ "description": "radv: fix creating BC image views when the base layer is > 0", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "98ba1e0d817e0354aad5d82eb9a2dc4cce33540f" }, diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 829a5df00b8..17a65969b92 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -6641,8 +6641,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff /* GFX10 field has the same base shift as the GFX6 field. */ uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; - cb->cb_color_view = - S_028C6C_SLICE_START(iview->vk.base_array_layer) | S_028C6C_SLICE_MAX_GFX10(max_slice); + uint32_t slice_start = iview->nbc_view.valid ? 0 : iview->vk.base_array_layer; + cb->cb_color_view = S_028C6C_SLICE_START(slice_start) | S_028C6C_SLICE_MAX_GFX10(max_slice); if (iview->image->info.samples > 1) { unsigned log_samples = util_logbase2(iview->image->info.samples); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 42d01ec890e..6959a90d580 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1967,6 +1967,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic struct radv_image *image = iview->image; struct radv_image_plane *plane = &image->planes[plane_id]; bool is_stencil = iview->vk.aspects == VK_IMAGE_ASPECT_STENCIL_BIT; + unsigned first_layer = iview->vk.base_array_layer; uint32_t blk_w; union radv_descriptor *descriptor; uint32_t hw_level = 0; @@ -1988,12 +1989,15 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic hw_level = nbc_view->level; iview->extent.width = nbc_view->width; iview->extent.height = nbc_view->height; + + /* Clear the base array layer because addrlib adds it as part of the base addr offset. */ + first_layer = 0; } } radv_make_texture_descriptor( device, image, is_storage_image, iview->vk.view_type, vk_format, components, hw_level, - hw_level + iview->vk.level_count - 1, iview->vk.base_array_layer, + hw_level + iview->vk.level_count - 1, first_layer, iview->vk.base_array_layer + iview->vk.layer_count - 1, vk_format_get_plane_width(image->vk.format, plane_id, iview->extent.width), vk_format_get_plane_height(image->vk.format, plane_id, iview->extent.height),