mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-29 11:40:31 +01:00
freedreno/a3xx/compiler: const file relative addressing
Teach new compiler scheduling and register assignment how to deal with relative addressing. This gets us what we need to avoid falling back to old compiler for CONST[ADDR[0].x+n]. It is also a prerequisite for temp file relative addressing, although that is going to also need some cleverness in register assignment to keep arrays grouped together. NOTE: doing address calculation in full precision and then narrowing to s16 in the mov to addr reg seems to sometimes cause lockups (and sometimes work?!). It seems more reliable to do the address calculation in s16, like the blob does. Which means teaching RA how to deal with mixed half and full precision allocation. Fortunately that didn't turn out to be too hard, so that is a nice bonus which we could probably take better advantage of elsewhere. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
c18ae9c293
commit
a5ac36a75f
8 changed files with 203 additions and 68 deletions
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@ -192,8 +192,7 @@ compile_init(struct fd3_compile_context *ctx, struct fd3_shader_variant *so,
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#define FM(x) (1 << TGSI_FILE_##x)
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/* optimize can't deal with relative addressing: */
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if (info->indirect_files & (FM(TEMPORARY) | FM(INPUT) |
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FM(OUTPUT) | FM(IMMEDIATE) | FM(CONSTANT)))
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if (info->indirect_files & (FM(TEMPORARY) | FM(INPUT) | FM(OUTPUT)))
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return TGSI_PARSE_ERROR;
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/* Immediates go after constants: */
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@ -414,14 +413,7 @@ block_temporary(struct ir3_block *block, unsigned n)
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static struct ir3_instruction *
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create_immed(struct fd3_compile_context *ctx, float val)
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{
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/* this can happen when registers (or components of a TGSI
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* register) are used as src before they have been assigned
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* (undefined contents). To avoid confusing the rest of the
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* compiler, and to generally keep things peachy, substitute
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* an instruction that sets the src to 0.0. Or to keep
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* things undefined, I could plug in a random number? :-P
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*
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* NOTE: *don't* use instr_create() here!
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/* NOTE: *don't* use instr_create() here!
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*/
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struct ir3_instruction *instr;
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instr = ir3_instr_create(ctx->block, 1, 0);
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@ -464,6 +456,12 @@ ssa_dst(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
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ctx->output_updates[idx].instr = instr;
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ctx->num_output_updates++;
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break;
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case TGSI_FILE_ADDRESS:
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compile_assert(ctx, n < 1);
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ctx->output_updates[idx].instrp = &ctx->block->address;
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ctx->output_updates[idx].instr = instr;
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ctx->num_output_updates++;
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break;
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}
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}
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@ -526,7 +524,8 @@ add_dst_reg_wrmask(struct fd3_compile_context *ctx,
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/* uses SSA */
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break;
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case TGSI_FILE_ADDRESS:
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num = REG_A0;
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flags |= IR3_REG_ADDR;
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/* uses SSA */
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break;
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default:
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compile_error(ctx, "unsupported dst register file: %s\n",
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@ -553,7 +552,8 @@ add_dst_reg_wrmask(struct fd3_compile_context *ctx,
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if (!ctx->atomic)
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ssa_dst(ctx, instr, dst, chan);
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} else if ((dst->File == TGSI_FILE_TEMPORARY) ||
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(dst->File == TGSI_FILE_OUTPUT)) {
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(dst->File == TGSI_FILE_OUTPUT) ||
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(dst->File == TGSI_FILE_ADDRESS)) {
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unsigned i;
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/* if instruction writes multiple, we need to create
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@ -591,6 +591,7 @@ add_src_reg_wrmask(struct fd3_compile_context *ctx,
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{
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unsigned flags = 0, num = 0;
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struct ir3_register *reg;
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struct ir3_instruction *orig = NULL;
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/* TODO we need to use a mov to temp for const >= 64.. or maybe
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* we could use relative addressing..
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@ -628,9 +629,21 @@ add_src_reg_wrmask(struct fd3_compile_context *ctx,
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flags |= IR3_REG_ABS;
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if (src->Negate)
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flags |= IR3_REG_NEGATE;
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if (src->Indirect)
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if (src->Indirect) {
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flags |= IR3_REG_RELATIV;
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/* shouldn't happen, and we can't cope with it below: */
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compile_assert(ctx, wrmask == 0x1);
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/* wrap in a meta-deref to track both the src and address: */
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orig = instr;
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instr = ir3_instr_create(ctx->block, -1, OPC_META_DEREF);
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ir3_reg_create(instr, 0, 0);
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ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = ctx->block->address;
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}
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reg = ir3_reg_create(instr, regid(num, chan), flags);
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reg->wrmask = wrmask;
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@ -643,6 +656,8 @@ add_src_reg_wrmask(struct fd3_compile_context *ctx,
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struct ir3_instruction *collect;
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unsigned i;
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compile_assert(ctx, !src->Indirect);
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/* if instruction reads multiple, we need to create
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* some place-holder collect the registers:
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*/
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@ -666,6 +681,10 @@ add_src_reg_wrmask(struct fd3_compile_context *ctx,
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reg->instr = collect;
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}
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if (src->Indirect) {
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reg = ir3_reg_create(orig, 0, flags | IR3_REG_SSA);
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reg->instr = instr;
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}
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return reg;
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}
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@ -718,36 +737,6 @@ get_internal_temp(struct fd3_compile_context *ctx,
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return tmp_src;
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}
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/* Get internal half-precision temp src/dst to use for a sequence of
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* instructions generated by a single TGSI op.
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*/
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static struct tgsi_src_register *
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get_internal_temp_hr(struct fd3_compile_context *ctx,
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struct tgsi_dst_register *tmp_dst)
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{
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struct tgsi_src_register *tmp_src;
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int n;
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tmp_dst->File = TGSI_FILE_TEMPORARY;
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tmp_dst->WriteMask = TGSI_WRITEMASK_XYZW;
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tmp_dst->Indirect = 0;
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tmp_dst->Dimension = 0;
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/* assign next temporary: */
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n = ctx->num_internal_temps++;
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compile_assert(ctx, n < ARRAY_SIZE(ctx->internal_temps));
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tmp_src = &ctx->internal_temps[n];
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/* just use hr0 because no one else should be using half-
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* precision regs:
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*/
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tmp_dst->Index = 0;
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src_from_dst(tmp_src, tmp_dst);
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return tmp_src;
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}
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static inline bool
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is_const(struct tgsi_src_register *src)
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{
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@ -1049,11 +1038,18 @@ trans_arl(const struct instr_translater *t,
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struct tgsi_dst_register *dst = &inst->Dst[0].Register;
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struct tgsi_src_register *src = &inst->Src[0].Register;
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unsigned chan = src->SwizzleX;
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compile_assert(ctx, dst->File == TGSI_FILE_ADDRESS);
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tmp_src = get_internal_temp_hr(ctx, &tmp_dst);
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/* NOTE: we allocate a temporary from a flat register
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* namespace (ignoring half vs full). It turns out
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* not to really matter since registers get reassigned
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* later in ir3_ra which (hopefully!) can deal a bit
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* better with mixed half and full precision.
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*/
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tmp_src = get_internal_temp(ctx, &tmp_dst);
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/* cov.{f32,f16}s16 Rtmp, Rsrc */
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/* cov.f{32,16}s16 Rtmp, Rsrc */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = get_ftype(ctx);
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instr->cat1.dst_type = TYPE_S16;
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@ -204,6 +204,8 @@ typedef enum {
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/* branches/flow control */
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OPC_META_FLOW = 4,
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OPC_META_PHI = 5,
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/* relative addressing */
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OPC_META_DEREF = 6,
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} opc_t;
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@ -244,6 +246,16 @@ static inline int type_float(type_t type)
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return (type == TYPE_F32) || (type == TYPE_F16);
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}
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static inline int type_uint(type_t type)
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{
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return (type == TYPE_U32) || (type == TYPE_U16) || (type == TYPE_U8);
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}
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static inline int type_sint(type_t type)
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{
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return (type == TYPE_S32) || (type == TYPE_S16) || (type == TYPE_S8);
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}
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typedef union PACKED {
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/* normal gpr or const src register: */
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struct PACKED {
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@ -70,6 +70,7 @@ struct ir3_register {
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*/
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IR3_REG_SSA = 0x1000, /* 'instr' is ptr to assigning instr */
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IR3_REG_IA = 0x2000, /* meta-input dst is "assigned" */
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IR3_REG_ADDR = 0x4000, /* register is a0.x */
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} flags;
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union {
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/* normal registers:
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@ -232,6 +233,8 @@ struct ir3_block {
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struct ir3_instruction **temporaries;
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struct ir3_instruction **inputs;
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struct ir3_instruction **outputs;
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/* only a single address register: */
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struct ir3_instruction *address;
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struct ir3_block *parent;
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struct ir3_instruction *head;
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};
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@ -351,10 +354,24 @@ static inline bool is_meta(struct ir3_instruction *instr)
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return (instr->category == -1);
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}
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static inline bool is_deref(struct ir3_instruction *instr)
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{
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return is_meta(instr) && (instr->opc == OPC_META_DEREF);
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}
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static inline bool writes_addr(struct ir3_instruction *instr)
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{
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if (instr->regs_count > 0) {
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struct ir3_register *dst = instr->regs[0];
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return !!(dst->flags & IR3_REG_ADDR);
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}
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return false;
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}
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/* TODO combine is_gpr()/reg_gpr().. */
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static inline bool reg_gpr(struct ir3_register *r)
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{
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if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_SSA))
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if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV | IR3_REG_SSA | IR3_REG_ADDR))
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return false;
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if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
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return false;
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@ -43,10 +43,13 @@ static bool is_eligible_mov(struct ir3_instruction *instr)
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{
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if ((instr->category == 1) &&
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(instr->cat1.src_type == instr->cat1.dst_type)) {
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struct ir3_register *dst = instr->regs[0];
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struct ir3_register *src = instr->regs[1];
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if (dst->flags & IR3_REG_ADDR)
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return false;
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if ((src->flags & IR3_REG_SSA) &&
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/* TODO: propagate abs/neg modifiers if possible */
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!(src->flags & (IR3_REG_ABS | IR3_REG_NEGATE)))
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!(src->flags & (IR3_REG_ABS | IR3_REG_NEGATE | IR3_REG_RELATIV)))
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return true;
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}
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return false;
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@ -63,6 +63,9 @@ int ir3_delayslots(struct ir3_instruction *assigner,
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if (is_meta(assigner))
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return 0;
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if (writes_addr(assigner))
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return 6;
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/* handled via sync flags: */
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if (is_sfu(assigner) || is_tex(assigner))
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return 0;
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@ -58,6 +58,9 @@ static void dump_instr_name(struct ir3_dump_ctx *ctx,
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case OPC_META_PHI:
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fprintf(ctx->f, "Φ");
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break;
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case OPC_META_DEREF:
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fprintf(ctx->f, "(*)");
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break;
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default:
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/* shouldn't hit here.. just for debugging: */
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switch (instr->opc) {
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@ -66,7 +69,6 @@ static void dump_instr_name(struct ir3_dump_ctx *ctx,
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case OPC_META_FO: fprintf(ctx->f, "_meta:fo"); break;
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case OPC_META_FI: fprintf(ctx->f, "_meta:fi"); break;
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case OPC_META_FLOW: fprintf(ctx->f, "_meta:flow"); break;
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case OPC_META_PHI: fprintf(ctx->f, "_meta:phi"); break;
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default: fprintf(ctx->f, "_meta:%d", instr->opc); break;
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}
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@ -162,7 +164,8 @@ static void dump_instr(struct ir3_dump_ctx *ctx,
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ir3_block_dump(ctx, instr->flow.else_block, "else");
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if (reg->flags & IR3_REG_SSA)
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dump_instr(ctx, reg->instr);
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} else if (instr->opc == OPC_META_PHI) {
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} else if ((instr->opc == OPC_META_PHI) ||
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(instr->opc == OPC_META_DEREF)) {
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/* treat like a normal instruction: */
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ir3_instr_dump(ctx, instr);
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}
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@ -228,7 +231,8 @@ static void dump_link2(struct ir3_dump_ctx *ctx,
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printdef(ctx, defer, "output%lx:<out%u>:w -> %s",
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PTRID(instr->inout.block),
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instr->regs[0]->num, target);
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} else if (instr->opc == OPC_META_PHI) {
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} else if ((instr->opc == OPC_META_PHI) ||
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(instr->opc == OPC_META_DEREF)) {
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/* treat like a normal instruction: */
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printdef(ctx, defer, "instr%lx:<dst0> -> %s", PTRID(instr), target);
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}
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@ -82,8 +82,8 @@ static struct ir3_ra_assignment ra_calc(struct ir3_instruction *instr);
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* Register Allocation:
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*/
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#define REG(n, wm) (struct ir3_register){ \
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/*.flags = ((so)->half_precision) ? IR3_REG_HALF : 0,*/ \
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#define REG(n, wm, f) (struct ir3_register){ \
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.flags = (f), \
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.num = (n), \
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.wrmask = TGSI_WRITEMASK_ ## wm, \
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}
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@ -145,7 +145,7 @@ static void compute_liveregs(struct ir3_ra_ctx *ctx,
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/* be sure to account for output registers too: */
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for (i = 0; i < block->noutputs; i++) {
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struct ir3_register reg = REG(output_base(ctx) + i, X);
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struct ir3_register reg = REG(output_base(ctx) + i, X, 0);
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regmask_set_if_not(liveregs, ®, &written);
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}
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}
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@ -212,14 +212,15 @@ static bool compute_clobbers(struct ir3_ra_ctx *ctx,
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return live || was_live;
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}
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static int find_available(regmask_t *liveregs, int size)
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static int find_available(regmask_t *liveregs, int size, bool half)
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{
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unsigned i;
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unsigned f = half ? IR3_REG_HALF : 0;
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for (i = 0; i < MAX_REG - size; i++) {
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if (!regmask_get(liveregs, ®(i, X))) {
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if (!regmask_get(liveregs, ®(i, X, f))) {
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unsigned start = i++;
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for (; (i < MAX_REG) && ((i - start) < size); i++)
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if (regmask_get(liveregs, ®(i, X)))
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if (regmask_get(liveregs, ®(i, X, f)))
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break;
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if ((i - start) >= size)
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return start;
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@ -240,7 +241,9 @@ static int alloc_block(struct ir3_ra_ctx *ctx,
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*/
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return 0;
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} else {
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struct ir3_register *dst = instr->regs[0];
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regmask_t liveregs;
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compute_liveregs(ctx, instr, &liveregs);
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// XXX XXX XXX XXX XXX XXX XXX XXX XXX
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@ -257,7 +260,9 @@ static int alloc_block(struct ir3_ra_ctx *ctx,
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} else
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// XXX XXX XXX XXX XXX XXX XXX XXX XXX
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compute_clobbers(ctx, instr->next, instr, &liveregs);
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return find_available(&liveregs, size);
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return find_available(&liveregs, size,
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!!(dst->flags & IR3_REG_HALF));
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}
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}
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@ -547,24 +552,32 @@ static void ra_assign(struct ir3_ra_ctx *ctx,
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static void ir3_instr_ra(struct ir3_ra_ctx *ctx,
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struct ir3_instruction *instr)
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{
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struct ir3_ra_assignment a;
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struct ir3_register *dst;
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unsigned num;
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/* skip over nop's */
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if (instr->regs_count == 0)
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return;
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/* skip writes to a0, p0, etc */
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if (!reg_gpr(instr->regs[0]))
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return;
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dst = instr->regs[0];
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/* if we've already visited this instruction, bail now: */
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if (instr->flags & IR3_INSTR_MARK)
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return;
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/* allocate register(s): */
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a = ra_calc(instr);
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num = alloc_block(ctx, instr, a.num) + a.off;
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if (is_deref(instr)) {
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num = instr->regs[2]->num;
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} else if (reg_gpr(dst)) {
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struct ir3_ra_assignment a;
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a = ra_calc(instr);
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num = alloc_block(ctx, instr, a.num) + a.off;
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} else if (dst->flags & IR3_REG_ADDR) {
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dst->flags &= ~IR3_REG_ADDR;
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num = regid(REG_A0, 0) | REG_HALF;
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} else {
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assert(0);
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}
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ra_assign(ctx, instr, num);
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}
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@ -578,6 +591,7 @@ static void legalize(struct ir3_ra_ctx *ctx, struct ir3_block *block)
|
|||
struct ir3_instruction *end =
|
||||
ir3_instr_create(block, 0, OPC_END);
|
||||
struct ir3_instruction *last_input = NULL;
|
||||
struct ir3_instruction *last_rel = NULL;
|
||||
regmask_t needs_ss_war; /* write after read */
|
||||
regmask_t needs_ss;
|
||||
regmask_t needs_sy;
|
||||
|
|
@ -614,6 +628,13 @@ static void legalize(struct ir3_ra_ctx *ctx, struct ir3_block *block)
|
|||
regmask_init(&needs_sy);
|
||||
}
|
||||
}
|
||||
|
||||
/* TODO: is it valid to have address reg loaded from a
|
||||
* relative src (ie. mova a0, c<a0.x+4>)? If so, the
|
||||
* last_rel check below should be moved ahead of this:
|
||||
*/
|
||||
if (reg->flags & IR3_REG_RELATIV)
|
||||
last_rel = n;
|
||||
}
|
||||
|
||||
if (n->regs_count > 0) {
|
||||
|
|
@ -622,6 +643,11 @@ static void legalize(struct ir3_ra_ctx *ctx, struct ir3_block *block)
|
|||
n->flags |= IR3_INSTR_SS;
|
||||
regmask_init(&needs_ss_war); // ??? I assume?
|
||||
}
|
||||
|
||||
if (last_rel && (reg->num == regid(REG_A0, 0))) {
|
||||
last_rel->flags |= IR3_INSTR_UL;
|
||||
last_rel = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* cat5+ does not have an (ss) bit, if needed we need to
|
||||
|
|
@ -685,6 +711,9 @@ static void legalize(struct ir3_ra_ctx *ctx, struct ir3_block *block)
|
|||
if (last_input)
|
||||
last_input->regs[0]->flags |= IR3_REG_EI;
|
||||
|
||||
if (last_rel)
|
||||
last_rel->flags |= IR3_INSTR_UL;
|
||||
|
||||
shader->instrs[shader->instrs_count++] = end;
|
||||
|
||||
shader->instrs[0]->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
|
||||
|
|
|
|||
|
|
@ -31,6 +31,11 @@
|
|||
|
||||
#include "ir3.h"
|
||||
|
||||
enum {
|
||||
SCHEDULED = -1,
|
||||
DELAYED = -2,
|
||||
};
|
||||
|
||||
/*
|
||||
* Instruction Scheduling:
|
||||
*
|
||||
|
|
@ -46,7 +51,8 @@
|
|||
*/
|
||||
|
||||
struct ir3_sched_ctx {
|
||||
struct ir3_instruction *scheduled;
|
||||
struct ir3_instruction *scheduled; /* last scheduled instr */
|
||||
struct ir3_instruction *deref; /* current deref, if any */
|
||||
unsigned cnt;
|
||||
};
|
||||
|
||||
|
|
@ -123,6 +129,11 @@ static void schedule(struct ir3_sched_ctx *ctx,
|
|||
block->head = instr->next;
|
||||
}
|
||||
|
||||
if (writes_addr(instr)) {
|
||||
assert(ctx->deref == NULL);
|
||||
ctx->deref = instr;
|
||||
}
|
||||
|
||||
instr->flags |= IR3_INSTR_MARK;
|
||||
|
||||
instr->next = ctx->scheduled;
|
||||
|
|
@ -210,13 +221,19 @@ static int trysched(struct ir3_sched_ctx *ctx,
|
|||
* we have enough delay slots to schedule ourself:
|
||||
*/
|
||||
delay = delay_calc(ctx, instr);
|
||||
if (delay)
|
||||
return delay;
|
||||
|
||||
if (!delay) {
|
||||
schedule(ctx, instr, true);
|
||||
return -1;
|
||||
/* if this is a write to address register, and addr register
|
||||
* is currently in use, we need to defer until it is free:
|
||||
*/
|
||||
if (writes_addr(instr) && ctx->deref) {
|
||||
assert(ctx->deref != instr);
|
||||
return DELAYED;
|
||||
}
|
||||
|
||||
return delay;
|
||||
schedule(ctx, instr, true);
|
||||
return SCHEDULED;
|
||||
}
|
||||
|
||||
static struct ir3_instruction * reverse(struct ir3_instruction *instr)
|
||||
|
|
@ -231,6 +248,56 @@ static struct ir3_instruction * reverse(struct ir3_instruction *instr)
|
|||
return reversed;
|
||||
}
|
||||
|
||||
static bool uses_current_deref(struct ir3_sched_ctx *ctx,
|
||||
struct ir3_instruction *instr)
|
||||
{
|
||||
unsigned i;
|
||||
for (i = 1; i < instr->regs_count; i++) {
|
||||
struct ir3_register *reg = instr->regs[i];
|
||||
if (reg->flags & IR3_REG_SSA) {
|
||||
if (is_deref(reg->instr)) {
|
||||
struct ir3_instruction *deref;
|
||||
deref = reg->instr->regs[1]->instr; /* the mova */
|
||||
if (ctx->deref == deref)
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/* when we encounter an instruction that writes to the address register
|
||||
* when it is in use, we delay that instruction and try to schedule all
|
||||
* other instructions using the current address register:
|
||||
*/
|
||||
static int block_sched_undelayed(struct ir3_sched_ctx *ctx,
|
||||
struct ir3_block *block)
|
||||
{
|
||||
struct ir3_instruction *instr = block->head;
|
||||
bool in_use = false;
|
||||
unsigned cnt = ~0;
|
||||
|
||||
while (instr) {
|
||||
struct ir3_instruction *next = instr->next;
|
||||
|
||||
if (uses_current_deref(ctx, instr)) {
|
||||
int ret = trysched(ctx, instr);
|
||||
if (ret == SCHEDULED)
|
||||
cnt = 0;
|
||||
else if (ret > 0)
|
||||
cnt = MIN2(cnt, ret);
|
||||
in_use = true;
|
||||
}
|
||||
|
||||
instr = next;
|
||||
}
|
||||
|
||||
if (!in_use)
|
||||
ctx->deref = NULL;
|
||||
|
||||
return cnt;
|
||||
}
|
||||
|
||||
static void block_sched(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
||||
{
|
||||
struct ir3_instruction *instr;
|
||||
|
|
@ -255,6 +322,10 @@ static void block_sched(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
|||
*/
|
||||
struct ir3_instruction *next = instr->next;
|
||||
int cnt = trysched(ctx, instr);
|
||||
|
||||
if (cnt == DELAYED)
|
||||
cnt = block_sched_undelayed(ctx, block);
|
||||
|
||||
/* -1 is signal to return up stack, but to us means same as 0: */
|
||||
cnt = MAX2(0, cnt);
|
||||
cnt += ctx->cnt;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue