From a520c976a5d2c533260c6ac083608f8d0aeaacf6 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 27 Mar 2024 15:59:49 -0700 Subject: [PATCH] intel/brw: Drop dead CHV checks. This compiler no longer supports Cherryview. Reviewed-by: Ian Romanick Part-of: --- src/intel/compiler/brw_eu_emit.c | 3 +-- src/intel/compiler/brw_fs_generator.cpp | 3 +-- src/intel/compiler/brw_fs_lower_regioning.cpp | 1 - src/intel/compiler/brw_ir_fs.h | 4 +--- 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 0499be04260..4e8c7d0c001 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2048,8 +2048,7 @@ brw_broadcast(struct brw_codegen *p, /* Use indirect addressing to fetch the specified component. */ if (type_sz(src.type) > 4 && - (devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) || - !devinfo->has_64bit_int)) { + (intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_int)) { /* From the Cherryview PRM Vol 7. "Register Region Restrictions": * * "When source or destination datatype is 64b or operation is diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index e5ccc18463f..1c41e8cc505 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -1383,8 +1383,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, break; case SHADER_OPCODE_CLUSTER_BROADCAST: { - assert((devinfo->platform != INTEL_PLATFORM_CHV && - !intel_device_info_is_9lp(devinfo) && + assert((!intel_device_info_is_9lp(devinfo) && devinfo->has_64bit_float) || type_sz(src[0].type) <= 4); assert(!src[0].negate && !src[0].abs); assert(src[1].file == BRW_IMMEDIATE_VALUE); diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp b/src/intel/compiler/brw_fs_lower_regioning.cpp index 0632c328dbd..0f7e4810664 100644 --- a/src/intel/compiler/brw_fs_lower_regioning.cpp +++ b/src/intel/compiler/brw_fs_lower_regioning.cpp @@ -146,7 +146,6 @@ namespace { * don't support 64-bit types at all. */ if ((!devinfo->has_64bit_int || - devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4) return BRW_REGISTER_TYPE_UD; else if (has_dst_aligned_region_restriction(devinfo, inst)) diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h index d457cb6ca47..4861a2ae279 100644 --- a/src/intel/compiler/brw_ir_fs.h +++ b/src/intel/compiler/brw_ir_fs.h @@ -752,9 +752,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo, if (type_sz(dst_type) > 4 || type_sz(exec_type) > 4 || (type_sz(exec_type) == 4 && is_dword_multiply)) - return devinfo->platform == INTEL_PLATFORM_CHV || - intel_device_info_is_9lp(devinfo) || - devinfo->verx10 >= 125; + return intel_device_info_is_9lp(devinfo) || devinfo->verx10 >= 125; else if (brw_reg_type_is_floating_point(dst_type)) return devinfo->verx10 >= 125;