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radeonsi: expose 16-bit NIR types for ALU, MEM, and LDS (no inputs/outputs)

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
This commit is contained in:
Marek Olšák 2025-03-11 18:36:34 -04:00 • committed by Marge Bot
parent 58f3d6fa20
commit a4b71e5b2d
3 changed files with 18 additions and 9 deletions
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7
src/gallium/drivers/radeonsi/ci/gfx11-navi31-fail.csv
View file

@ -27,8 +27,15 @@ spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
# This is caused by lowering mediump before linking:
spec@glsl-es-1.00@linker@glsl-mismatched-uniform-precision-unused,Fail
# glcts failures
# glGetUniform returns mediump uniforms rounded to FP16 precision because we only store them as FP16.
# The test could be changed to allow this behavior because there is no point in storing FP32 values
# in the driver only for glGetUniform.
GTF-GL46.gtf21.GL2Tests.glGetUniform.glGetUniform,Fail
KHR-GL46.shaders.uniform_block.random.nested_structs_instance_arrays.0,Fail
## Fail because GFX10+ removed MS texture support (see si_get_sparse_texture_virtual_page_size)
KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r11f_g11f_b10f,Fail

1 # LLVM 20-dev (da439d3af47b)
27 spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
28 spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
29 # glcts failures # This is caused by lowering mediump before linking:
30 spec@glsl-es-1.00@linker@glsl-mismatched-uniform-precision-unused,Fail
31 # glcts failures
32 KHR-GL46.shaders.uniform_block.random.nested_structs_instance_arrays.0,Fail # glGetUniform returns mediump uniforms rounded to FP16 precision because we only store them as FP16.
33 ## Fail because GFX10+ removed MS texture support (see si_get_sparse_texture_virtual_page_size) # The test could be changed to allow this behavior because there is no point in storing FP32 values
34 # in the driver only for glGetUniform.
35 GTF-GL46.gtf21.GL2Tests.glGetUniform.glGetUniform,Fail
36 KHR-GL46.shaders.uniform_block.random.nested_structs_instance_arrays.0,Fail
37 ## Fail because GFX10+ removed MS texture support (see si_get_sparse_texture_virtual_page_size)
38 KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r11f_g11f_b10f,Fail
39 KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r11f_g11f_b10f,Fail KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r16,Fail
40 KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r16,Fail KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r16_snorm,Fail
41 KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r16_snorm,Fail KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r16f,Fail

2
src/gallium/drivers/radeonsi/si_debug_options.h
View file

@ -10,7 +10,7 @@ OPT_BOOL(vs_fetch_always_opencode, false,
OPT_BOOL(no_infinite_interp, false, "Kill PS with infinite interp coeff")
OPT_BOOL(clamp_div_by_zero, false, "Clamp div by zero (x / 0 becomes FLT_MAX instead of NaN)")
OPT_BOOL(vrs2x2, false, "Enable 2x2 coarse shading for non-GUI elements")
OPT_BOOL(fp16, false, "Enable FP16 for mediump.")
OPT_BOOL(mediump, false, "Use 16-bit IO for mediump.")
/* for Maya */
OPT_INT(tc_max_cpu_storage_size, 2500, "Enable the CPU storage for pipelined buffer uploads in TC.")
/* for Creo and Snx */

18
src/gallium/drivers/radeonsi/si_get.c
View file

@ -876,7 +876,7 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
(sscreen->info.family >= CHIP_GFX940 && !sscreen->info.has_graphics) ||
/* fma32 is too slow for gpu < gfx9, so apply the option only for gpu >= gfx9 */
(sscreen->info.gfx_level >= GFX9 && sscreen->options.force_use_fma32);
bool has_mediump = sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16;
bool has_mediump = sscreen->info.gfx_level >= GFX9 && sscreen->options.mediump;
nir_shader_compiler_options *options = sscreen->nir_options;
ac_nir_set_options(&sscreen->info, !sscreen->use_aco, options);
@ -952,14 +952,16 @@ void si_init_shader_caps(struct si_screen *sscreen)
caps->int64_atomics = true;
caps->tgsi_any_inout_decl_range = true;
/* We need f16c for fast FP16 conversions in glUniform. */
caps->fp16_const_buffers =
util_get_cpu_caps()->has_f16c && sscreen->nir_options->lower_mediump_io;
/* We need F16C for fast FP16 conversions in glUniform.
* It's supported since Intel Ivy Bridge and AMD Bulldozer.
*/
bool has_16bit_alu = sscreen->info.gfx_level >= GFX9 && util_get_cpu_caps()->has_f16c;
caps->fp16 =
caps->fp16_derivatives =
caps->glsl_16bit_consts =
caps->int16 = sscreen->nir_options->lower_mediump_io != NULL;
caps->fp16 = has_16bit_alu;
caps->fp16_derivatives = has_16bit_alu;
caps->fp16_const_buffers = has_16bit_alu;
caps->int16 = has_16bit_alu;
caps->glsl_16bit_consts = has_16bit_alu;
}
}