From a472d415bc5c11ee41ca26175d2fe2a759e57cc2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Wed, 27 Mar 2024 07:14:11 -0700
Subject: [PATCH] anv/xe2: Enable compute walker and BTD thread preemption
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GFX versions older than GFX 20 have 'Thread Preemption disable' while
GFX 20 has 'Thread Preemption' with value flipped in compute walker
instruction.
So here by default enabling thread preemption, only disabling it
when BTD mode is enabled as instructed in Wa_14017794102.

Similar for 3DSTATE_BTD, enabling preemption by default and
only disabling when platform is affected by Wa_14017794102.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29616>
---
 src/intel/genxml/gen20.xml          | 4 ++--
 src/intel/vulkan/genX_cmd_compute.c | 6 ++++++
 src/intel/vulkan/genX_init_state.c  | 3 +++
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/intel/genxml/gen20.xml b/src/intel/genxml/gen20.xml
index 9950b829799..7308301c134 100644
--- a/src/intel/genxml/gen20.xml
+++ b/src/intel/genxml/gen20.xml
@@ -64,7 +64,7 @@
       <value name="Ftz" value="0" />
       <value name="SetByKernel" value="1" />
     </field>
-    <field name="Thread Preemption" start="84" end="84" type="bool" />
+    <field name="Thread Preemption" start="84" end="84" type="bool" default="1" />
     <field name="Sampler Count" start="98" end="100" type="uint">
       <value name="No samplers used" value="0" />
       <value name="Between 1 and 4 samplers used" value="1" />
@@ -342,7 +342,7 @@
       <value name="512" value="2" />
       <value name="1024" value="3" />
     </field>
-    <field name="BTD Mid thread preemption" start="63" end="63" type="bool" />
+    <field name="BTD Mid thread preemption" start="63" end="63" type="bool" default="1" />
     <field name="Per DSS Memory Backed Buffer Size" start="64" end="66" type="uint" default="6">
       <value name="2KB" value="0" />
       <value name="4KB" value="1" />
diff --git a/src/intel/vulkan/genX_cmd_compute.c b/src/intel/vulkan/genX_cmd_compute.c
index 552fcb5c1fa..3bee556729c 100644
--- a/src/intel/vulkan/genX_cmd_compute.c
+++ b/src/intel/vulkan/genX_cmd_compute.c
@@ -1043,6 +1043,9 @@ cmd_buffer_trace_rays(struct anv_cmd_buffer *cmd_buffer,
                                       pipeline->base.scratch_size);
          btd.ScratchSpaceBuffer = scratch_surf >> 4;
       }
+#if INTEL_NEEDS_WA_14017794102
+      btd.BTDMidthreadpreemption = false;
+#endif
    }
 
    genX(cmd_buffer_ensure_cfe_state)(cmd_buffer, pipeline->base.scratch_size);
@@ -1079,6 +1082,9 @@ cmd_buffer_trace_rays(struct anv_cmd_buffer *cmd_buffer,
          .BindingTablePointer = surfaces->offset,
          .NumberofThreadsinGPGPUThreadGroup = 1,
          .BTDMode = true,
+#if INTEL_NEEDS_WA_14017794102
+         .ThreadPreemption = false,
+#endif
       };
 
       struct brw_rt_raygen_trampoline_params trampoline_params = {
diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c
index 13316958522..4938e5b6621 100644
--- a/src/intel/vulkan/genX_init_state.c
+++ b/src/intel/vulkan/genX_init_state.c
@@ -330,6 +330,9 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
              */
             .offset = device->btd_fifo_bo->offset,
          };
+#if INTEL_NEEDS_WA_14017794102
+         btd.BTDMidthreadpreemption = false;
+#endif
       }
    }
 #endif