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panfrost: Fix up some formatting for clang-format

Browse source 
clang-format will make a mess of these otherwise.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20425>
This commit is contained in:
Alyssa Rosenzweig 2022-12-22 21:22:15 -05:00 • committed by Marge Bot
parent e35719be6f
commit a4705afe63
35 changed files with 1088 additions and 1050 deletions
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16
src/gallium/drivers/panfrost/pan_cmdstream.c
View file

@ -2295,16 +2295,18 @@ pan_emit_vary(const struct panfrost_device *dev,
/* Special records */
/* clang-format off */
static const struct {
unsigned components;
enum mali_format format;
unsigned components;
enum mali_format format;
} pan_varying_formats[PAN_VARY_MAX] = {
[PAN_VARY_POSITION] = { 4, MALI_SNAP_4 },
[PAN_VARY_PSIZ] = { 1, MALI_R16F },
[PAN_VARY_PNTCOORD] = { 4, MALI_RGBA32F },
[PAN_VARY_FACE] = { 1, MALI_R32I },
[PAN_VARY_FRAGCOORD] = { 4, MALI_RGBA32F },
[PAN_VARY_POSITION] = { 4, MALI_SNAP_4 },
[PAN_VARY_PSIZ] = { 1, MALI_R16F },
[PAN_VARY_PNTCOORD] = { 4, MALI_RGBA32F },
[PAN_VARY_FACE] = { 1, MALI_R32I },
[PAN_VARY_FRAGCOORD] = { 4, MALI_RGBA32F },
};
/* clang-format on */
static mali_pixel_format
pan_special_format(const struct panfrost_device *dev,

2
src/gallium/drivers/panfrost/pan_helpers.c
View file

@ -179,7 +179,7 @@ pan_assign_vertex_buffer(struct pan_vertex_buffer *buffers,
buffers[idx] = (struct pan_vertex_buffer) {
.vbi = vbi,
.divisor = divisor
.divisor = divisor,
};
return idx;

2
src/gallium/drivers/panfrost/pan_mempool.h
View file

@ -75,7 +75,7 @@ panfrost_pool_take_ref(struct panfrost_pool *pool, mali_ptr ptr)
return (struct panfrost_pool_ref) {
.bo = pool->transient_bo,
.gpu = ptr
.gpu = ptr,
};
}

6
src/gallium/drivers/panfrost/pan_resource.c
View file

@ -121,7 +121,7 @@ panfrost_resource_from_handle(struct pipe_screen *pscreen,
panfrost_translate_texture_dimension(templat->target);
struct pan_image_explicit_layout explicit_layout = {
.offset = whandle->offset,
.row_stride = panfrost_from_legacy_stride(whandle->stride, templat->format, mod)
.row_stride = panfrost_from_legacy_stride(whandle->stride, templat->format, mod),
};
rsc->image.layout = (struct pan_image_layout) {
@ -504,7 +504,7 @@ panfrost_resource_setup(struct panfrost_device *dev,
.array_size = pres->base.array_size,
.nr_samples = MAX2(pres->base.nr_samples, 1),
.nr_slices = pres->base.last_level + 1,
.crc = panfrost_should_checksum(dev, pres)
.crc = panfrost_should_checksum(dev, pres),
};
ASSERTED bool valid = pan_image_layout_init(&pres->image.layout, NULL);
@ -1213,7 +1213,7 @@ pan_resource_modifier_convert(struct panfrost_context *ctx,
.src.format = rsrc->base.format,
.src.box = box,
.mask = util_format_get_mask(tmp_rsrc->base.format),
.filter = PIPE_TEX_FILTER_NEAREST
.filter = PIPE_TEX_FILTER_NEAREST,
};
for (int i = 0; i <= rsrc->base.last_level; i++) {

34
src/gallium/drivers/panfrost/pan_screen.c
View file

@ -54,26 +54,28 @@
#include "pan_context.h"
/* clang-format off */
static const struct debug_named_value panfrost_debug_options[] = {
{"perf", PAN_DBG_PERF, "Enable performance warnings"},
{"trace", PAN_DBG_TRACE, "Trace the command stream"},
{"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
{"dirty", PAN_DBG_DIRTY, "Always re-emit all state"},
{"sync", PAN_DBG_SYNC, "Wait for each job's completion and abort on GPU faults"},
{"nofp16", PAN_DBG_NOFP16, "Disable 16-bit support"},
{"gl3", PAN_DBG_GL3, "Enable experimental GL 3.x implementation, up to 3.3"},
{"noafbc", PAN_DBG_NO_AFBC, "Disable AFBC support"},
{"nocrc", PAN_DBG_NO_CRC, "Disable transaction elimination"},
{"msaa16", PAN_DBG_MSAA16, "Enable MSAA 8x and 16x support"},
{"indirect", PAN_DBG_INDIRECT, "Use experimental compute kernel for indirect draws"},
{"linear", PAN_DBG_LINEAR, "Force linear textures"},
{"nocache", PAN_DBG_NO_CACHE, "Disable BO cache"},
{"dump", PAN_DBG_DUMP, "Dump all graphics memory"},
{"perf", PAN_DBG_PERF, "Enable performance warnings"},
{"trace", PAN_DBG_TRACE, "Trace the command stream"},
{"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
{"dirty", PAN_DBG_DIRTY, "Always re-emit all state"},
{"sync", PAN_DBG_SYNC, "Wait for each job's completion and abort on GPU faults"},
{"nofp16", PAN_DBG_NOFP16, "Disable 16-bit support"},
{"gl3", PAN_DBG_GL3, "Enable experimental GL 3.x implementation, up to 3.3"},
{"noafbc", PAN_DBG_NO_AFBC, "Disable AFBC support"},
{"nocrc", PAN_DBG_NO_CRC, "Disable transaction elimination"},
{"msaa16", PAN_DBG_MSAA16, "Enable MSAA 8x and 16x support"},
{"indirect", PAN_DBG_INDIRECT, "Use experimental compute kernel for indirect draws"},
{"linear", PAN_DBG_LINEAR, "Force linear textures"},
{"nocache", PAN_DBG_NO_CACHE, "Disable BO cache"},
{"dump", PAN_DBG_DUMP, "Dump all graphics memory"},
#ifdef PAN_DBG_OVERFLOW
{"overflow", PAN_DBG_OVERFLOW, "Check for buffer overflows in pool uploads"},
{"overflow", PAN_DBG_OVERFLOW, "Check for buffer overflows in pool uploads"},
#endif
DEBUG_NAMED_VALUE_END
DEBUG_NAMED_VALUE_END
};
/* clang-format on */
static const char *
panfrost_get_name(struct pipe_screen *screen)

4
src/panfrost/bifrost/bi_opt_message_preload.c
View file

@ -105,7 +105,7 @@ bi_opt_message_preload(bi_context *ctx)
.enabled = true,
.varying_index = I->varying_index,
.fp16 = (I->register_format == BI_REGISTER_FORMAT_F16),
.num_components = I->vecsize + 1
.num_components = I->vecsize + 1,
};
} else if (bi_is_var_tex(I->op)) {
msg = (struct bifrost_message_preload) {
@ -115,7 +115,7 @@ bi_opt_message_preload(bi_context *ctx)
.texture_index = I->texture_index,
.fp16 = (I->op == BI_OPCODE_VAR_TEX_F16),
.skip = I->skip,
.zero_lod = I->lod_mode
.zero_lod = I->lod_mode,
};
} else {
continue;

2
src/panfrost/bifrost/bi_opt_push_ubo.c
View file

@ -113,7 +113,7 @@ bi_pick_ubo(struct panfrost_ubo_push *push, struct bi_ubo_analysis *analysis)
for (unsigned offs = 0; offs < range; ++offs) {
struct panfrost_ubo_word word = {
.ubo = ubo,
.offset = (r + offs) * 4
.offset = (r + offs) * 4,
};
push->words[push->count++] = word;

8
src/panfrost/bifrost/bi_pack.c
View file

@ -58,7 +58,7 @@ bi_pack_header(bi_clause *clause, bi_clause *next_1, bi_clause *next_2)
.dependency_slot = clause->scoreboard_id,
.message_type = clause->message_type,
.next_message_type = next_1 ? next_1->message_type : 0,
.flush_to_zero = clause->ftz ? BIFROST_FTZ_ALWAYS : BIFROST_FTZ_DISABLE
.flush_to_zero = clause->ftz ? BIFROST_FTZ_ALWAYS : BIFROST_FTZ_DISABLE,
};
uint64_t u = 0;
@ -362,7 +362,7 @@ bi_pack_tuple(bi_clause *clause, bi_tuple *tuple, bi_tuple *prev, bool first_tup
struct bi_packed_tuple packed = {
.lo = reg | (fma << 35) | ((add & 0b111111) << 58),
.hi = add >> 6
.hi = add >> 6,
};
return packed;
@ -423,7 +423,7 @@ bi_pack_constants(unsigned tuple_count, uint64_t *constants,
{ 4, 8 },
{ 7, 11, 14 },
{ 6, 10, 13 },
{ 9, 12 }
{ 9, 12 },
};
/* Compute the pos, and check everything is reasonable */
@ -670,7 +670,7 @@ bi_pack_clause(bi_context *ctx, bi_clause *clause,
unsigned m0 = (clause->pcrel_idx == 0) ? 4 : 0;
unsigned counts[8] = {
1, 2, 3, 3, 4, 5, 5, 6
1, 2, 3, 3, 4, 5, 5, 6,
};
unsigned indices[8][6] = {

2
src/panfrost/bifrost/bi_ra.c
View file

@ -568,7 +568,7 @@ bi_fixup_dual_tex_register(bi_instr *I)
assert(I->src[3].type == BI_INDEX_CONSTANT);
struct bifrost_dual_texture_operation desc = {
.secondary_register = I->dest[1].value
.secondary_register = I->dest[1].value,
};
I->src[3].value |= bi_dual_tex_as_u32(desc);

84
src/panfrost/bifrost/bifrost.h
View file

@ -301,22 +301,24 @@ struct bi_clause_format {
enum bi_clause_subword s7; /* 15 bits */
};
/* clang-format off */
static const struct bi_clause_format bi_clause_formats[] = {
{ 0, 0, L(0), L(5), U(0), T(0), T(0), H, H },
{ 0, 0, Z, L(1), U(0), T(0), T(0), H, H },
{ 1, 1, Z, L(0), L(3), T(1), T(1), R, U(1) },
{ 2, 1, L(0), L(4), U(1), T(1), T(1), T(2), T(2) },
{ 3, 2, Z, L(0), L(4), EC, M, T(2), U(2) },
{ 4, 2, L(0), L(0), L(1), T(3), T(3), T(2), U(23) },
{ 4, 2, Z, L(0), L(5), T(3), T(3), T(2), U(23) },
{ 5, 2, L(2), U(3), U(2), T(3), T(3), T(2), EC },
{ 6, 3, Z, L(2), U(4), T(4), T(4), EC, EC },
{ 7, 3, L(1), L(4), U(4), T(4), T(4), T(5), T(5) },
{ 8, 4, Z, L(0), L(6), EC, M, T(5), U(5) },
{ 9, 4, Z, L(0), L(7), T(6), T(6), T(5), U(56) },
{ 10, 4, L(3), U(6), U(5), T(6), T(6), T(5), EC },
{ 11, 5, Z, L(3), U(7), T(7), T(7), EC, EC },
{ 0, 0, L(0), L(5), U(0), T(0), T(0), H, H },
{ 0, 0, Z, L(1), U(0), T(0), T(0), H, H },
{ 1, 1, Z, L(0), L(3), T(1), T(1), R, U(1) },
{ 2, 1, L(0), L(4), U(1), T(1), T(1), T(2), T(2) },
{ 3, 2, Z, L(0), L(4), EC, M, T(2), U(2) },
{ 4, 2, L(0), L(0), L(1), T(3), T(3), T(2), U(23) },
{ 4, 2, Z, L(0), L(5), T(3), T(3), T(2), U(23) },
{ 5, 2, L(2), U(3), U(2), T(3), T(3), T(2), EC },
{ 6, 3, Z, L(2), U(4), T(4), T(4), EC, EC },
{ 7, 3, L(1), L(4), U(4), T(4), T(4), T(5), T(5) },
{ 8, 4, Z, L(0), L(6), EC, M, T(5), U(5) },
{ 9, 4, Z, L(0), L(7), T(6), T(6), T(5), U(56) },
{ 10, 4, L(3), U(6), U(5), T(6), T(6), T(5), EC },
{ 11, 5, Z, L(3), U(7), T(7), T(7), EC, EC },
};
/* clang-format on */
#undef L
#undef U
@ -381,36 +383,38 @@ struct bifrost_reg_ctrl_23 {
bool slot3_fma;
};
/* clang-format off */
#ifndef __cplusplus
static const struct bifrost_reg_ctrl_23 bifrost_reg_ctrl_lut[32] = {
[BIFROST_R_WL_FMA] = { BIFROST_OP_READ, BIFROST_OP_WRITE_LO, true },
[BIFROST_R_WH_FMA] = { BIFROST_OP_READ, BIFROST_OP_WRITE_HI, true },
[BIFROST_R_W_FMA] = { BIFROST_OP_READ, BIFROST_OP_WRITE, true },
[BIFROST_R_WL_ADD] = { BIFROST_OP_READ, BIFROST_OP_WRITE_LO, false },
[BIFROST_R_WH_ADD] = { BIFROST_OP_READ, BIFROST_OP_WRITE_HI, false },
[BIFROST_R_W_ADD] = { BIFROST_OP_READ, BIFROST_OP_WRITE, false },
[BIFROST_WL_WL_ADD] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE_LO, false },
[BIFROST_WL_WH_ADD] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE_HI, false },
[BIFROST_WL_W_ADD] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE, false },
[BIFROST_WH_WL_ADD] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE_LO, false },
[BIFROST_WH_WH_ADD] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE_HI, false },
[BIFROST_WH_W_ADD] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE, false },
[BIFROST_W_WL_ADD] = { BIFROST_OP_WRITE, BIFROST_OP_WRITE_LO, false },
[BIFROST_W_WH_ADD] = { BIFROST_OP_WRITE, BIFROST_OP_WRITE_HI, false },
[BIFROST_W_W_ADD] = { BIFROST_OP_WRITE, BIFROST_OP_WRITE, false },
[BIFROST_IDLE_1] = { BIFROST_OP_IDLE, BIFROST_OP_IDLE, true },
[BIFROST_I_W_FMA] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE, true },
[BIFROST_I_WL_FMA] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_LO, true },
[BIFROST_I_WH_FMA] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_HI, true },
[BIFROST_R_I] = { BIFROST_OP_READ, BIFROST_OP_IDLE, false },
[BIFROST_I_W_ADD] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE, false },
[BIFROST_I_WL_ADD] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_LO, false },
[BIFROST_I_WH_ADD] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_HI, false },
[BIFROST_WL_WH_MIX] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE_HI, false },
[BIFROST_WH_WL_MIX] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE_LO, false },
[BIFROST_IDLE] = { BIFROST_OP_IDLE, BIFROST_OP_IDLE, true },
[BIFROST_R_WL_FMA] = { BIFROST_OP_READ, BIFROST_OP_WRITE_LO, true },
[BIFROST_R_WH_FMA] = { BIFROST_OP_READ, BIFROST_OP_WRITE_HI, true },
[BIFROST_R_W_FMA] = { BIFROST_OP_READ, BIFROST_OP_WRITE, true },
[BIFROST_R_WL_ADD] = { BIFROST_OP_READ, BIFROST_OP_WRITE_LO, false },
[BIFROST_R_WH_ADD] = { BIFROST_OP_READ, BIFROST_OP_WRITE_HI, false },
[BIFROST_R_W_ADD] = { BIFROST_OP_READ, BIFROST_OP_WRITE, false },
[BIFROST_WL_WL_ADD] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE_LO, false },
[BIFROST_WL_WH_ADD] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE_HI, false },
[BIFROST_WL_W_ADD] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE, false },
[BIFROST_WH_WL_ADD] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE_LO, false },
[BIFROST_WH_WH_ADD] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE_HI, false },
[BIFROST_WH_W_ADD] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE, false },
[BIFROST_W_WL_ADD] = { BIFROST_OP_WRITE, BIFROST_OP_WRITE_LO, false },
[BIFROST_W_WH_ADD] = { BIFROST_OP_WRITE, BIFROST_OP_WRITE_HI, false },
[BIFROST_W_W_ADD] = { BIFROST_OP_WRITE, BIFROST_OP_WRITE, false },
[BIFROST_IDLE_1] = { BIFROST_OP_IDLE, BIFROST_OP_IDLE, true },
[BIFROST_I_W_FMA] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE, true },
[BIFROST_I_WL_FMA] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_LO, true },
[BIFROST_I_WH_FMA] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_HI, true },
[BIFROST_R_I] = { BIFROST_OP_READ, BIFROST_OP_IDLE, false },
[BIFROST_I_W_ADD] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE, false },
[BIFROST_I_WL_ADD] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_LO, false },
[BIFROST_I_WH_ADD] = { BIFROST_OP_IDLE, BIFROST_OP_WRITE_HI, false },
[BIFROST_WL_WH_MIX] = { BIFROST_OP_WRITE_LO, BIFROST_OP_WRITE_HI, false },
[BIFROST_WH_WL_MIX] = { BIFROST_OP_WRITE_HI, BIFROST_OP_WRITE_LO, false },
[BIFROST_IDLE] = { BIFROST_OP_IDLE, BIFROST_OP_IDLE, true },
};
#endif
/* clang-format on */
/* Texture operator descriptors in various states. Usually packed in the
* compiler and stored as a constant */

34
src/panfrost/bifrost/bifrost_compile.c
View file

@ -41,23 +41,25 @@
#include "bi_builder.h"
#include "bifrost_nir.h"
/* clang-format off */
static const struct debug_named_value bifrost_debug_options[] = {
{"msgs", BIFROST_DBG_MSGS, "Print debug messages"},
{"shaders", BIFROST_DBG_SHADERS, "Dump shaders in NIR and MIR"},
{"shaderdb", BIFROST_DBG_SHADERDB, "Print statistics"},
{"verbose", BIFROST_DBG_VERBOSE, "Disassemble verbosely"},
{"internal", BIFROST_DBG_INTERNAL, "Dump even internal shaders"},
{"nosched", BIFROST_DBG_NOSCHED, "Force trivial bundling"},
{"nopsched", BIFROST_DBG_NOPSCHED, "Disable scheduling for pressure"},
{"inorder", BIFROST_DBG_INORDER, "Force in-order bundling"},
{"novalidate",BIFROST_DBG_NOVALIDATE, "Skip IR validation"},
{"noopt", BIFROST_DBG_NOOPT, "Skip optimization passes"},
{"noidvs", BIFROST_DBG_NOIDVS, "Disable IDVS"},
{"nosb", BIFROST_DBG_NOSB, "Disable scoreboarding"},
{"nopreload", BIFROST_DBG_NOPRELOAD, "Disable message preloading"},
{"spill", BIFROST_DBG_SPILL, "Test register spilling"},
DEBUG_NAMED_VALUE_END
{"msgs", BIFROST_DBG_MSGS, "Print debug messages"},
{"shaders", BIFROST_DBG_SHADERS, "Dump shaders in NIR and MIR"},
{"shaderdb", BIFROST_DBG_SHADERDB, "Print statistics"},
{"verbose", BIFROST_DBG_VERBOSE, "Disassemble verbosely"},
{"internal", BIFROST_DBG_INTERNAL, "Dump even internal shaders"},
{"nosched", BIFROST_DBG_NOSCHED, "Force trivial bundling"},
{"nopsched", BIFROST_DBG_NOPSCHED, "Disable scheduling for pressure"},
{"inorder", BIFROST_DBG_INORDER, "Force in-order bundling"},
{"novalidate", BIFROST_DBG_NOVALIDATE, "Skip IR validation"},
{"noopt", BIFROST_DBG_NOOPT, "Skip optimization passes"},
{"noidvs", BIFROST_DBG_NOIDVS, "Disable IDVS"},
{"nosb", BIFROST_DBG_NOSB, "Disable scoreboarding"},
{"nopreload", BIFROST_DBG_NOPRELOAD, "Disable message preloading"},
{"spill", BIFROST_DBG_SPILL, "Test register spilling"},
DEBUG_NAMED_VALUE_END
};
/* clang-format on */
DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug, "BIFROST_MESA_DEBUG", bifrost_debug_options, 0)
@ -5192,7 +5194,7 @@ bi_compile_variant(nir_shader *nir,
.bifrost = &info->bifrost,
.tls_size = info->tls_size,
.sysvals = &info->sysvals,
.push_offset = info->push.count
.push_offset = info->push.count,
};
unsigned offset = binary->size;

4
src/panfrost/lib/genxml/decode.c
View file

@ -282,7 +282,7 @@ pandecode_fbd(uint64_t gpu_va, bool is_fragment, unsigned gpu_id)
return (struct pandecode_fbd) {
.rt_count = params.render_target_count,
.has_extra = params.has_zs_crc_extension
.has_extra = params.has_zs_crc_extension,
};
#else
/* Dummy unpack of the padding section to make sure all words are 0.
@ -292,7 +292,7 @@ pandecode_fbd(uint64_t gpu_va, bool is_fragment, unsigned gpu_id)
pan_section_unpack(fb, FRAMEBUFFER, PADDING_2, padding2);
return (struct pandecode_fbd) {
.rt_count = 1
.rt_count = 1,
};
#endif
}

34
src/panfrost/lib/pan_afbc.c
View file

@ -142,25 +142,25 @@ panfrost_afbc_format(unsigned arch, enum pipe_format format)
/* We handle swizzling orthogonally to AFBC */
format = unswizzled_format(format);
switch (format) {
case PIPE_FORMAT_R8_UNORM: return PAN_AFBC_MODE_R8;
case PIPE_FORMAT_R8G8_UNORM: return PAN_AFBC_MODE_R8G8;
case PIPE_FORMAT_R8G8B8_UNORM: return PAN_AFBC_MODE_R8G8B8;
case PIPE_FORMAT_R8G8B8A8_UNORM: return PAN_AFBC_MODE_R8G8B8A8;
case PIPE_FORMAT_R5G6B5_UNORM: return PAN_AFBC_MODE_R5G6B5;
case PIPE_FORMAT_R5G5B5A1_UNORM: return PAN_AFBC_MODE_R5G5B5A1;
case PIPE_FORMAT_R10G10B10A2_UNORM: return PAN_AFBC_MODE_R10G10B10A2;
case PIPE_FORMAT_R4G4B4A4_UNORM: return PAN_AFBC_MODE_R4G4B4A4;
case PIPE_FORMAT_Z16_UNORM: return PAN_AFBC_MODE_R8G8;
/* clang-format off */
switch (format) {
case PIPE_FORMAT_R8_UNORM: return PAN_AFBC_MODE_R8;
case PIPE_FORMAT_R8G8_UNORM: return PAN_AFBC_MODE_R8G8;
case PIPE_FORMAT_R8G8B8_UNORM: return PAN_AFBC_MODE_R8G8B8;
case PIPE_FORMAT_R8G8B8A8_UNORM: return PAN_AFBC_MODE_R8G8B8A8;
case PIPE_FORMAT_R5G6B5_UNORM: return PAN_AFBC_MODE_R5G6B5;
case PIPE_FORMAT_R5G5B5A1_UNORM: return PAN_AFBC_MODE_R5G5B5A1;
case PIPE_FORMAT_R10G10B10A2_UNORM: return PAN_AFBC_MODE_R10G10B10A2;
case PIPE_FORMAT_R4G4B4A4_UNORM: return PAN_AFBC_MODE_R4G4B4A4;
case PIPE_FORMAT_Z16_UNORM: return PAN_AFBC_MODE_R8G8;
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_X24S8_UINT:
return PAN_AFBC_MODE_R8G8B8A8;
case PIPE_FORMAT_Z24_UNORM_S8_UINT: return PAN_AFBC_MODE_R8G8B8A8;
case PIPE_FORMAT_Z24X8_UNORM: return PAN_AFBC_MODE_R8G8B8A8;
case PIPE_FORMAT_X24S8_UINT: return PAN_AFBC_MODE_R8G8B8A8;
default:
return PAN_AFBC_MODE_INVALID;
}
default: return PAN_AFBC_MODE_INVALID;
}
/* clang-format on */
}
/* A format may be compressed as AFBC if it has an AFBC internal format */

2
src/panfrost/lib/pan_blend.c
View file

@ -641,7 +641,7 @@ GENX(pan_blend_create_shader)(const struct panfrost_device *dev,
.logicop_enable = state->logicop_enable,
.logicop_func = state->logicop_func,
.rt[0].colormask = rt_state->equation.color_mask,
.format[0] = rt_state->format
.format[0] = rt_state->format,
};
if (!rt_state->equation.blend_enable) {

14
src/panfrost/lib/pan_clear.c
View file

@ -79,14 +79,16 @@ struct mali_tib_layout {
unsigned int_a, frac_a;
};
/* clang-format off */
static const struct mali_tib_layout tib_layouts[] = {
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A8] = { 8, 0, 8, 0, 8, 0, 8, 0 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R10G10B10A2] = { 10, 0, 10, 0, 10, 0, 2, 0 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A2] = { 8, 2, 8, 2, 8, 2, 2, 0 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R4G4B4A4] = { 4, 4, 4, 4, 4, 4, 4, 4 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R5G6B5A0] = { 5, 5, 6, 4, 5, 5, 0, 2 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R5G5B5A1] = { 5, 5, 5, 5, 5, 5, 1, 1 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A8] = { 8, 0, 8, 0, 8, 0, 8, 0 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R10G10B10A2] = { 10, 0, 10, 0, 10, 0, 2, 0 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A2] = { 8, 2, 8, 2, 8, 2, 2, 0 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R4G4B4A4] = { 4, 4, 4, 4, 4, 4, 4, 4 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R5G6B5A0] = { 5, 5, 6, 4, 5, 5, 0, 2 },
[MALI_COLOR_BUFFER_INTERNAL_FORMAT_R5G5B5A1] = { 5, 5, 5, 5, 5, 5, 1, 1 },
};
/* clang-format on */
/* Raw values are stored as-is but replicated for multisampling */

68
src/panfrost/lib/pan_cs.c
View file

@ -355,25 +355,27 @@ pan_select_max_tile_size(unsigned tile_buffer_bytes, unsigned bytes_per_pixel)
static enum mali_color_format
pan_mfbd_raw_format(unsigned bits)
{
switch (bits) {
case 8: return MALI_COLOR_FORMAT_RAW8;
case 16: return MALI_COLOR_FORMAT_RAW16;
case 24: return MALI_COLOR_FORMAT_RAW24;
case 32: return MALI_COLOR_FORMAT_RAW32;
case 48: return MALI_COLOR_FORMAT_RAW48;
case 64: return MALI_COLOR_FORMAT_RAW64;
case 96: return MALI_COLOR_FORMAT_RAW96;
case 128: return MALI_COLOR_FORMAT_RAW128;
case 192: return MALI_COLOR_FORMAT_RAW192;
case 256: return MALI_COLOR_FORMAT_RAW256;
case 384: return MALI_COLOR_FORMAT_RAW384;
case 512: return MALI_COLOR_FORMAT_RAW512;
case 768: return MALI_COLOR_FORMAT_RAW768;
case 1024: return MALI_COLOR_FORMAT_RAW1024;
case 1536: return MALI_COLOR_FORMAT_RAW1536;
case 2048: return MALI_COLOR_FORMAT_RAW2048;
default: unreachable("invalid raw bpp");
}
/* clang-format off */
switch (bits) {
case 8: return MALI_COLOR_FORMAT_RAW8;
case 16: return MALI_COLOR_FORMAT_RAW16;
case 24: return MALI_COLOR_FORMAT_RAW24;
case 32: return MALI_COLOR_FORMAT_RAW32;
case 48: return MALI_COLOR_FORMAT_RAW48;
case 64: return MALI_COLOR_FORMAT_RAW64;
case 96: return MALI_COLOR_FORMAT_RAW96;
case 128: return MALI_COLOR_FORMAT_RAW128;
case 192: return MALI_COLOR_FORMAT_RAW192;
case 256: return MALI_COLOR_FORMAT_RAW256;
case 384: return MALI_COLOR_FORMAT_RAW384;
case 512: return MALI_COLOR_FORMAT_RAW512;
case 768: return MALI_COLOR_FORMAT_RAW768;
case 1024: return MALI_COLOR_FORMAT_RAW1024;
case 1536: return MALI_COLOR_FORMAT_RAW1536;
case 2048: return MALI_COLOR_FORMAT_RAW2048;
default: unreachable("invalid raw bpp");
}
/* clang-format on */
}
static void
@ -434,19 +436,21 @@ pan_afbc_compression_mode(enum pipe_format format)
* needs to handle the subset of formats returned by
* panfrost_afbc_format.
*/
switch (panfrost_afbc_format(PAN_ARCH, format)) {
case PAN_AFBC_MODE_R8: return MALI_AFBC_COMPRESSION_MODE_R8;
case PAN_AFBC_MODE_R8G8: return MALI_AFBC_COMPRESSION_MODE_R8G8;
case PAN_AFBC_MODE_R5G6B5: return MALI_AFBC_COMPRESSION_MODE_R5G6B5;
case PAN_AFBC_MODE_R4G4B4A4: return MALI_AFBC_COMPRESSION_MODE_R4G4B4A4;
case PAN_AFBC_MODE_R5G5B5A1: return MALI_AFBC_COMPRESSION_MODE_R5G5B5A1;
case PAN_AFBC_MODE_R8G8B8: return MALI_AFBC_COMPRESSION_MODE_R8G8B8;
case PAN_AFBC_MODE_R8G8B8A8: return MALI_AFBC_COMPRESSION_MODE_R8G8B8A8;
case PAN_AFBC_MODE_R10G10B10A2: return MALI_AFBC_COMPRESSION_MODE_R10G10B10A2;
case PAN_AFBC_MODE_R11G11B10: return MALI_AFBC_COMPRESSION_MODE_R11G11B10;
case PAN_AFBC_MODE_S8: return MALI_AFBC_COMPRESSION_MODE_S8;
case PAN_AFBC_MODE_INVALID: unreachable("Invalid AFBC format");
}
/* clang-format off */
switch (panfrost_afbc_format(PAN_ARCH, format)) {
case PAN_AFBC_MODE_R8: return MALI_AFBC_COMPRESSION_MODE_R8;
case PAN_AFBC_MODE_R8G8: return MALI_AFBC_COMPRESSION_MODE_R8G8;
case PAN_AFBC_MODE_R5G6B5: return MALI_AFBC_COMPRESSION_MODE_R5G6B5;
case PAN_AFBC_MODE_R4G4B4A4: return MALI_AFBC_COMPRESSION_MODE_R4G4B4A4;
case PAN_AFBC_MODE_R5G5B5A1: return MALI_AFBC_COMPRESSION_MODE_R5G5B5A1;
case PAN_AFBC_MODE_R8G8B8: return MALI_AFBC_COMPRESSION_MODE_R8G8B8;
case PAN_AFBC_MODE_R8G8B8A8: return MALI_AFBC_COMPRESSION_MODE_R8G8B8A8;
case PAN_AFBC_MODE_R10G10B10A2: return MALI_AFBC_COMPRESSION_MODE_R10G10B10A2;
case PAN_AFBC_MODE_R11G11B10: return MALI_AFBC_COMPRESSION_MODE_R11G11B10;
case PAN_AFBC_MODE_S8: return MALI_AFBC_COMPRESSION_MODE_S8;
case PAN_AFBC_MODE_INVALID: unreachable("Invalid AFBC format");
}
/* clang-format on */
unreachable("all AFBC formats handled");
}

2
src/panfrost/lib/pan_earlyzs.c
View file

@ -95,7 +95,7 @@ analyze(const struct pan_shader_info *s,
return (struct pan_earlyzs_state) {
.update = late_update ? PAN_EARLYZS_FORCE_LATE : early_mode,
.kill = late_kill ? PAN_EARLYZS_FORCE_LATE : early_mode
.kill = late_kill ? PAN_EARLYZS_FORCE_LATE : early_mode,
};
}

800
src/panfrost/lib/pan_format.c
View file

@ -51,7 +51,7 @@
{ MALI_BLEND_PU_ ## internal | (srgb ? (1 << 20) : 0) | \
PAN_V6_SWIZZLE(R, G, B, A), \
MALI_BLEND_AU_ ## internal | (srgb ? (1 << 20) : 0) | \
PAN_V6_SWIZZLE(R, G, B, A) } \
PAN_V6_SWIZZLE(R, G, B, A), }, \
}
#else
#define BFMT2(pipe, internal, writeback, srgb) \
@ -59,7 +59,7 @@
MALI_COLOR_BUFFER_INTERNAL_FORMAT_## internal, \
MALI_COLOR_FORMAT_## writeback, \
{ MALI_BLEND_PU_ ## internal | (srgb ? (1 << 20) : 0), \
MALI_BLEND_AU_ ## internal | (srgb ? (1 << 20) : 0) } \
MALI_BLEND_AU_ ## internal | (srgb ? (1 << 20) : 0), }, \
}
#endif
@ -150,7 +150,7 @@ GENX(panfrost_blendable_formats)[PIPE_FORMAT_COUNT] = {
.hw = ( V6_ ## swizzle ) | \
(( MALI_ ## mali ) << 12) | \
((( SRGB_ ## srgb)) << 20), \
.bind = FLAGS_ ## flags \
.bind = FLAGS_ ## flags, \
}
#else
@ -165,434 +165,436 @@ GENX(panfrost_blendable_formats)[PIPE_FORMAT_COUNT] = {
.hw = ( MALI_RGB_COMPONENT_ORDER_ ## swizzle ) | \
(( MALI_ ## mali ) << 12) | \
((( SRGB_ ## srgb)) << 20), \
.bind = FLAGS_ ## flags \
.bind = FLAGS_ ## flags, \
}
#endif
/* clang-format off */
const struct panfrost_format GENX(panfrost_pipe_format)[PIPE_FORMAT_COUNT] = {
FMT(NONE, CONSTANT, 0000, L, VTR_),
FMT(NONE, CONSTANT, 0000, L, VTR_),
#if PAN_ARCH <= 7
FMT(ETC1_RGB8, ETC2_RGB8, RGB1, L, _T__),
FMT(ETC2_RGB8, ETC2_RGB8, RGB1, L, _T__),
FMT(ETC2_SRGB8, ETC2_RGB8, RGB1, S, _T__),
FMT(ETC2_R11_UNORM, ETC2_R11_UNORM, R001, L, _T__),
FMT(ETC2_RGBA8, ETC2_RGBA8, RGBA, L, _T__),
FMT(ETC2_SRGBA8, ETC2_RGBA8, RGBA, S, _T__),
FMT(ETC2_RG11_UNORM, ETC2_RG11_UNORM, RG01, L, _T__),
FMT(ETC2_R11_SNORM, ETC2_R11_SNORM, R001, L, _T__),
FMT(ETC2_RG11_SNORM, ETC2_RG11_SNORM, RG01, L, _T__),
FMT(ETC2_RGB8A1, ETC2_RGB8A1, RGBA, L, _T__),
FMT(ETC2_SRGB8A1, ETC2_RGB8A1, RGBA, S, _T__),
FMT(DXT1_RGB, BC1_UNORM, RGB1, L, _T__),
FMT(DXT1_RGBA, BC1_UNORM, RGBA, L, _T__),
FMT(DXT1_SRGB, BC1_UNORM, RGB1, S, _T__),
FMT(DXT1_SRGBA, BC1_UNORM, RGBA, S, _T__),
FMT(DXT3_RGBA, BC2_UNORM, RGBA, L, _T__),
FMT(DXT3_SRGBA, BC2_UNORM, RGBA, S, _T__),
FMT(DXT5_RGBA, BC3_UNORM, RGBA, L, _T__),
FMT(DXT5_SRGBA, BC3_UNORM, RGBA, S, _T__),
FMT(RGTC1_UNORM, BC4_UNORM, R001, L, _T__),
FMT(RGTC1_SNORM, BC4_SNORM, R001, L, _T__),
FMT(RGTC2_UNORM, BC5_UNORM, RG01, L, _T__),
FMT(RGTC2_SNORM, BC5_SNORM, RG01, L, _T__),
FMT(BPTC_RGB_FLOAT, BC6H_SF16, RGB1, L, _T__),
FMT(BPTC_RGB_UFLOAT, BC6H_UF16, RGB1, L, _T__),
FMT(BPTC_RGBA_UNORM, BC7_UNORM, RGBA, L, _T__),
FMT(BPTC_SRGBA, BC7_UNORM, RGBA, S, _T__),
FMT(ASTC_4x4, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_5x4, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_5x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_6x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_6x6, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_8x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_8x6, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_8x8, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x6, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x8, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x10, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_12x10, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_12x12, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_4x4_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_5x4_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_5x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_6x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_6x6_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_8x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_8x6_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_8x8_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x6_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x8_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x10_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_12x10_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_12x12_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_3x3x3, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_4x3x3, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_4x4x3, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_4x4x4, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_5x4x4, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_5x5x4, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_5x5x5, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_6x5x5, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_6x6x5, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_6x6x6, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_3x3x3_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_4x3x3_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_4x4x3_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_4x4x4_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_5x4x4_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_5x5x4_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_5x5x5_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_6x5x5_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_6x6x5_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_6x6x6_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ETC1_RGB8, ETC2_RGB8, RGB1, L, _T__),
FMT(ETC2_RGB8, ETC2_RGB8, RGB1, L, _T__),
FMT(ETC2_SRGB8, ETC2_RGB8, RGB1, S, _T__),
FMT(ETC2_R11_UNORM, ETC2_R11_UNORM, R001, L, _T__),
FMT(ETC2_RGBA8, ETC2_RGBA8, RGBA, L, _T__),
FMT(ETC2_SRGBA8, ETC2_RGBA8, RGBA, S, _T__),
FMT(ETC2_RG11_UNORM, ETC2_RG11_UNORM, RG01, L, _T__),
FMT(ETC2_R11_SNORM, ETC2_R11_SNORM, R001, L, _T__),
FMT(ETC2_RG11_SNORM, ETC2_RG11_SNORM, RG01, L, _T__),
FMT(ETC2_RGB8A1, ETC2_RGB8A1, RGBA, L, _T__),
FMT(ETC2_SRGB8A1, ETC2_RGB8A1, RGBA, S, _T__),
FMT(DXT1_RGB, BC1_UNORM, RGB1, L, _T__),
FMT(DXT1_RGBA, BC1_UNORM, RGBA, L, _T__),
FMT(DXT1_SRGB, BC1_UNORM, RGB1, S, _T__),
FMT(DXT1_SRGBA, BC1_UNORM, RGBA, S, _T__),
FMT(DXT3_RGBA, BC2_UNORM, RGBA, L, _T__),
FMT(DXT3_SRGBA, BC2_UNORM, RGBA, S, _T__),
FMT(DXT5_RGBA, BC3_UNORM, RGBA, L, _T__),
FMT(DXT5_SRGBA, BC3_UNORM, RGBA, S, _T__),
FMT(RGTC1_UNORM, BC4_UNORM, R001, L, _T__),
FMT(RGTC1_SNORM, BC4_SNORM, R001, L, _T__),
FMT(RGTC2_UNORM, BC5_UNORM, RG01, L, _T__),
FMT(RGTC2_SNORM, BC5_SNORM, RG01, L, _T__),
FMT(BPTC_RGB_FLOAT, BC6H_SF16, RGB1, L, _T__),
FMT(BPTC_RGB_UFLOAT, BC6H_UF16, RGB1, L, _T__),
FMT(BPTC_RGBA_UNORM, BC7_UNORM, RGBA, L, _T__),
FMT(BPTC_SRGBA, BC7_UNORM, RGBA, S, _T__),
FMT(ASTC_4x4, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_5x4, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_5x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_6x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_6x6, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_8x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_8x6, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_8x8, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x5, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x6, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x8, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_10x10, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_12x10, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_12x12, ASTC_2D_HDR, RGBA, L, _T__),
FMT(ASTC_4x4_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_5x4_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_5x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_6x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_6x6_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_8x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_8x6_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_8x8_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x5_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x6_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x8_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_10x10_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_12x10_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_12x12_SRGB, ASTC_2D_LDR, RGBA, S, _T__),
FMT(ASTC_3x3x3, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_4x3x3, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_4x4x3, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_4x4x4, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_5x4x4, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_5x5x4, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_5x5x5, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_6x5x5, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_6x6x5, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_6x6x6, ASTC_3D_HDR, RGBA, L, _T__),
FMT(ASTC_3x3x3_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_4x3x3_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_4x4x3_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_4x4x4_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_5x4x4_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_5x5x4_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_5x5x5_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_6x5x5_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_6x6x5_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
FMT(ASTC_6x6x6_SRGB, ASTC_3D_LDR, RGBA, S, _T__),
#else
/* Map to interchange format, as compression is specified in the plane
* descriptor on Valhall.
*/
FMT(ETC1_RGB8, RGBA8_UNORM, RGB1, L, _T__),
FMT(ETC2_RGB8, RGBA8_UNORM, RGB1, L, _T__),
FMT(ETC2_SRGB8, RGBA8_UNORM, RGB1, S, _T__),
FMT(ETC2_R11_UNORM, R16_UNORM, R001, L, _T__),
FMT(ETC2_RGBA8, RGBA8_UNORM, RGBA, L, _T__),
FMT(ETC2_SRGBA8, RGBA8_UNORM, RGBA, S, _T__),
FMT(ETC2_RG11_UNORM, RG16_UNORM, RG01, L, _T__),
FMT(ETC2_R11_SNORM, R16_SNORM, R001, L, _T__),
FMT(ETC2_RG11_SNORM, RG16_SNORM, RG01, L, _T__),
FMT(ETC2_RGB8A1, RGBA8_UNORM, RGBA, L, _T__),
FMT(ETC2_SRGB8A1, RGBA8_UNORM, RGBA, S, _T__),
FMT(DXT1_RGB, RGBA8_UNORM, RGB1, L, _T__),
FMT(DXT1_RGBA, RGBA8_UNORM, RGBA, L, _T__),
FMT(DXT1_SRGB, RGBA8_UNORM, RGB1, S, _T__),
FMT(DXT1_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
FMT(DXT3_RGBA, RGBA8_UNORM, RGBA, L, _T__),
FMT(DXT3_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
FMT(DXT5_RGBA, RGBA8_UNORM, RGBA, L, _T__),
FMT(DXT5_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
FMT(RGTC1_UNORM, R16_UNORM, R001, L, _T__),
FMT(RGTC1_SNORM, R16_SNORM, R001, L, _T__),
FMT(RGTC2_UNORM, RG16_UNORM, RG01, L, _T__),
FMT(RGTC2_SNORM, RG16_SNORM, RG01, L, _T__),
FMT(BPTC_RGB_FLOAT, RGBA16F, RGB1, L, _T__),
FMT(BPTC_RGB_UFLOAT, RGBA16F, RGB1, L, _T__),
FMT(BPTC_RGBA_UNORM, RGBA8_UNORM, RGBA, L, _T__),
FMT(BPTC_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
/* Map to interchange format, as compression is specified in the plane
* descriptor on Valhall.
*/
FMT(ETC1_RGB8, RGBA8_UNORM, RGB1, L, _T__),
FMT(ETC2_RGB8, RGBA8_UNORM, RGB1, L, _T__),
FMT(ETC2_SRGB8, RGBA8_UNORM, RGB1, S, _T__),
FMT(ETC2_R11_UNORM, R16_UNORM, R001, L, _T__),
FMT(ETC2_RGBA8, RGBA8_UNORM, RGBA, L, _T__),
FMT(ETC2_SRGBA8, RGBA8_UNORM, RGBA, S, _T__),
FMT(ETC2_RG11_UNORM, RG16_UNORM, RG01, L, _T__),
FMT(ETC2_R11_SNORM, R16_SNORM, R001, L, _T__),
FMT(ETC2_RG11_SNORM, RG16_SNORM, RG01, L, _T__),
FMT(ETC2_RGB8A1, RGBA8_UNORM, RGBA, L, _T__),
FMT(ETC2_SRGB8A1, RGBA8_UNORM, RGBA, S, _T__),
FMT(DXT1_RGB, RGBA8_UNORM, RGB1, L, _T__),
FMT(DXT1_RGBA, RGBA8_UNORM, RGBA, L, _T__),
FMT(DXT1_SRGB, RGBA8_UNORM, RGB1, S, _T__),
FMT(DXT1_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
FMT(DXT3_RGBA, RGBA8_UNORM, RGBA, L, _T__),
FMT(DXT3_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
FMT(DXT5_RGBA, RGBA8_UNORM, RGBA, L, _T__),
FMT(DXT5_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
FMT(RGTC1_UNORM, R16_UNORM, R001, L, _T__),
FMT(RGTC1_SNORM, R16_SNORM, R001, L, _T__),
FMT(RGTC2_UNORM, RG16_UNORM, RG01, L, _T__),
FMT(RGTC2_SNORM, RG16_SNORM, RG01, L, _T__),
FMT(BPTC_RGB_FLOAT, RGBA16F, RGB1, L, _T__),
FMT(BPTC_RGB_UFLOAT, RGBA16F, RGB1, L, _T__),
FMT(BPTC_RGBA_UNORM, RGBA8_UNORM, RGBA, L, _T__),
FMT(BPTC_SRGBA, RGBA8_UNORM, RGBA, S, _T__),
/* Mesa does not yet support astc_decode_mode extensions, so non-sRGB
* formats must be assumed to be wide.
*/
FMT(ASTC_4x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x6, RGBA16F, RGBA, L, _T__),
FMT(ASTC_8x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_8x6, RGBA16F, RGBA, L, _T__),
FMT(ASTC_8x8, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x6, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x8, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x10, RGBA16F, RGBA, L, _T__),
FMT(ASTC_12x10, RGBA16F, RGBA, L, _T__),
FMT(ASTC_12x12, RGBA16F, RGBA, L, _T__),
FMT(ASTC_3x3x3, RGBA16F, RGBA, L, _T__),
FMT(ASTC_4x3x3, RGBA16F, RGBA, L, _T__),
FMT(ASTC_4x4x3, RGBA16F, RGBA, L, _T__),
FMT(ASTC_4x4x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x4x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x5x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x5x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x5x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x6x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x6x6, RGBA16F, RGBA, L, _T__),
/* Mesa does not yet support astc_decode_mode extensions, so non-sRGB
* formats must be assumed to be wide.
*/
FMT(ASTC_4x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x6, RGBA16F, RGBA, L, _T__),
FMT(ASTC_8x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_8x6, RGBA16F, RGBA, L, _T__),
FMT(ASTC_8x8, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x6, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x8, RGBA16F, RGBA, L, _T__),
FMT(ASTC_10x10, RGBA16F, RGBA, L, _T__),
FMT(ASTC_12x10, RGBA16F, RGBA, L, _T__),
FMT(ASTC_12x12, RGBA16F, RGBA, L, _T__),
FMT(ASTC_3x3x3, RGBA16F, RGBA, L, _T__),
FMT(ASTC_4x3x3, RGBA16F, RGBA, L, _T__),
FMT(ASTC_4x4x3, RGBA16F, RGBA, L, _T__),
FMT(ASTC_4x4x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x4x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x5x4, RGBA16F, RGBA, L, _T__),
FMT(ASTC_5x5x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x5x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x6x5, RGBA16F, RGBA, L, _T__),
FMT(ASTC_6x6x6, RGBA16F, RGBA, L, _T__),
/* By definition, sRGB formats are narrow */
FMT(ASTC_4x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x6_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_8x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_8x6_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_8x8_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x6_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x8_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x10_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_12x10_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_12x12_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_3x3x3_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_4x3x3_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_4x4x3_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_4x4x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x4x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x5x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x5x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x5x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x6x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
/* By definition, sRGB formats are narrow */
FMT(ASTC_4x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x6_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_8x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_8x6_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_8x8_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x6_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x8_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_10x10_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_12x10_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_12x12_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_3x3x3_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_4x3x3_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_4x4x3_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_4x4x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x4x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x5x4_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_5x5x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x5x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
FMT(ASTC_6x6x5_SRGB, RGBA8_UNORM, RGBA, S, _T__),
#endif
FMT(R5G6B5_UNORM, RGB565, RGB1, L, VTR_),
FMT(B5G6R5_UNORM, RGB565, BGR1, L, VTR_),
FMT(R5G5B5X1_UNORM, RGB5_A1_UNORM, RGB1, L, VT__),
FMT(B5G5R5X1_UNORM, RGB5_A1_UNORM, BGR1, L, VT__),
FMT(R5G5B5A1_UNORM, RGB5_A1_UNORM, RGBA, L, VTR_),
FMT(B5G5R5A1_UNORM, RGB5_A1_UNORM, BGRA, L, VTR_),
FMT(R10G10B10X2_UNORM, RGB10_A2_UNORM, RGB1, L, VTR_),
FMT(B10G10R10X2_UNORM, RGB10_A2_UNORM, BGR1, L, VTR_),
FMT(R10G10B10A2_UNORM, RGB10_A2_UNORM, RGBA, L, VTR_),
FMT(B10G10R10A2_UNORM, RGB10_A2_UNORM, BGRA, L, VTR_),
FMT(R5G6B5_UNORM, RGB565, RGB1, L, VTR_),
FMT(B5G6R5_UNORM, RGB565, BGR1, L, VTR_),
FMT(R5G5B5X1_UNORM, RGB5_A1_UNORM, RGB1, L, VT__),
FMT(B5G5R5X1_UNORM, RGB5_A1_UNORM, BGR1, L, VT__),
FMT(R5G5B5A1_UNORM, RGB5_A1_UNORM, RGBA, L, VTR_),
FMT(B5G5R5A1_UNORM, RGB5_A1_UNORM, BGRA, L, VTR_),
FMT(R10G10B10X2_UNORM, RGB10_A2_UNORM, RGB1, L, VTR_),
FMT(B10G10R10X2_UNORM, RGB10_A2_UNORM, BGR1, L, VTR_),
FMT(R10G10B10A2_UNORM, RGB10_A2_UNORM, RGBA, L, VTR_),
FMT(B10G10R10A2_UNORM, RGB10_A2_UNORM, BGRA, L, VTR_),
#if PAN_ARCH <= 5
FMT(R10G10B10X2_SNORM, RGB10_A2_SNORM, RGB1, L, VT__),
FMT(R10G10B10A2_SNORM, RGB10_A2_SNORM, RGBA, L, VT__),
FMT(B10G10R10A2_SNORM, RGB10_A2_SNORM, BGRA, L, VT__),
FMT(R3G3B2_UNORM, RGB332_UNORM, RGB1, L, VT__),
FMT(R10G10B10X2_SNORM, RGB10_A2_SNORM, RGB1, L, VT__),
FMT(R10G10B10A2_SNORM, RGB10_A2_SNORM, RGBA, L, VT__),
FMT(B10G10R10A2_SNORM, RGB10_A2_SNORM, BGRA, L, VT__),
FMT(R3G3B2_UNORM, RGB332_UNORM, RGB1, L, VT__),
#else
FMT(R10G10B10X2_SNORM, RGB10_A2_SNORM, RGB1, L, V___),
FMT(R10G10B10A2_SNORM, RGB10_A2_SNORM, RGBA, L, V___),
FMT(B10G10R10A2_SNORM, RGB10_A2_SNORM, BGRA, L, V___),
FMT(R10G10B10X2_SNORM, RGB10_A2_SNORM, RGB1, L, V___),
FMT(R10G10B10A2_SNORM, RGB10_A2_SNORM, RGBA, L, V___),
FMT(B10G10R10A2_SNORM, RGB10_A2_SNORM, BGRA, L, V___),
#endif
FMT(R10G10B10A2_UINT, RGB10_A2UI, RGBA, L, VTR_),
FMT(B10G10R10A2_UINT, RGB10_A2UI, BGRA, L, VTR_),
FMT(R10G10B10A2_USCALED, RGB10_A2UI, RGBA, L, V___),
FMT(B10G10R10A2_USCALED, RGB10_A2UI, BGRA, L, V___),
FMT(R10G10B10A2_SINT, RGB10_A2I, RGBA, L, VTR_),
FMT(B10G10R10A2_SINT, RGB10_A2I, BGRA, L, VTR_),
FMT(R10G10B10A2_SSCALED, RGB10_A2I, RGBA, L, V___),
FMT(B10G10R10A2_SSCALED, RGB10_A2I, BGRA, L, V___),
FMT(R8_SSCALED, R8I, R001, L, V___),
FMT(R8G8_SSCALED, RG8I, RG01, L, V___),
FMT(R8G8B8_SSCALED, RGB8I, RGB1, L, V___),
FMT(B8G8R8_SSCALED, RGB8I, BGR1, L, V___),
FMT(R8G8B8A8_SSCALED, RGBA8I, RGBA, L, V___),
FMT(B8G8R8A8_SSCALED, RGBA8I, BGRA, L, V___),
FMT(A8B8G8R8_SSCALED, RGBA8I, ABGR, L, V___),
FMT(R8_USCALED, R8UI, R001, L, V___),
FMT(R8G8_USCALED, RG8UI, RG01, L, V___),
FMT(R8G8B8_USCALED, RGB8UI, RGB1, L, V___),
FMT(B8G8R8_USCALED, RGB8UI, BGR1, L, V___),
FMT(R8G8B8A8_USCALED, RGBA8UI, RGBA, L, V___),
FMT(B8G8R8A8_USCALED, RGBA8UI, BGRA, L, V___),
FMT(A8B8G8R8_USCALED, RGBA8UI, ABGR, L, V___),
FMT(R16_USCALED, R16UI, R001, L, V___),
FMT(R16G16_USCALED, RG16UI, RG01, L, V___),
FMT(R16G16B16A16_USCALED, RGBA16UI, RGBA, L, V___),
FMT(R16_SSCALED, R16I, R001, L, V___),
FMT(R16G16_SSCALED, RG16I, RG01, L, V___),
FMT(R16G16B16A16_SSCALED, RGBA16I, RGBA, L, V___),
FMT(R32_USCALED, R32UI, R001, L, V___),
FMT(R32G32_USCALED, RG32UI, RG01, L, V___),
FMT(R32G32B32_USCALED, RGB32UI, RGB1, L, V___),
FMT(R32G32B32A32_USCALED, RGBA32UI, RGBA, L, V___),
FMT(R32_SSCALED, R32I, R001, L, V___),
FMT(R32G32_SSCALED, RG32I, RG01, L, V___),
FMT(R32G32B32_SSCALED, RGB32I, RGB1, L, V___),
FMT(R32G32B32A32_SSCALED, RGBA32I, RGBA, L, V___),
FMT(R32_FIXED, R32_FIXED, R001, L, V___),
FMT(R32G32_FIXED, RG32_FIXED, RG01, L, V___),
FMT(R32G32B32_FIXED, RGB32_FIXED, RGB1, L, V___),
FMT(R32G32B32A32_FIXED, RGBA32_FIXED, RGBA, L, V___),
FMT(R11G11B10_FLOAT, R11F_G11F_B10F, RGB1, L, VTR_),
FMT(R9G9B9E5_FLOAT, R9F_G9F_B9F_E5F, RGB1, L, VT__),
FMT(R8_SNORM, R8_SNORM, R001, L, VT__),
FMT(R16_SNORM, R16_SNORM, R001, L, VT__),
FMT(R8G8_SNORM, RG8_SNORM, RG01, L, VT__),
FMT(R16G16_SNORM, RG16_SNORM, RG01, L, VT__),
FMT(R8G8B8_SNORM, RGB8_SNORM, RGB1, L, VT__),
FMT(R8G8B8A8_SNORM, RGBA8_SNORM, RGBA, L, VT__),
FMT(R16G16B16A16_SNORM, RGBA16_SNORM, RGBA, L, VT__),
FMT(I8_SINT, R8I, RRRR, L, VTR_),
FMT(L8_SINT, R8I, RRR1, L, VTR_),
FMT(I8_UINT, R8UI, RRRR, L, VTR_),
FMT(L8_UINT, R8UI, RRR1, L, VTR_),
FMT(I16_SINT, R16I, RRRR, L, VTR_),
FMT(L16_SINT, R16I, RRR1, L, VTR_),
FMT(I16_UINT, R16UI, RRRR, L, VTR_),
FMT(L16_UINT, R16UI, RRR1, L, VTR_),
FMT(I32_SINT, R32I, RRRR, L, VTR_),
FMT(L32_SINT, R32I, RRR1, L, VTR_),
FMT(I32_UINT, R32UI, RRRR, L, VTR_),
FMT(L32_UINT, R32UI, RRR1, L, VTR_),
FMT(B8G8R8_UINT, RGB8UI, BGR1, L, VTR_),
FMT(B8G8R8A8_UINT, RGBA8UI, BGRA, L, VTR_),
FMT(B8G8R8_SINT, RGB8I, BGR1, L, VTR_),
FMT(B8G8R8A8_SINT, RGBA8I, BGRA, L, VTR_),
FMT(A8R8G8B8_UINT, RGBA8UI, GBAR, L, VTR_),
FMT(A8B8G8R8_UINT, RGBA8UI, ABGR, L, VTR_),
FMT(R8_UINT, R8UI, R001, L, VTR_),
FMT(R16_UINT, R16UI, R001, L, VTR_),
FMT(R32_UINT, R32UI, R001, L, VTR_),
FMT(R8G8_UINT, RG8UI, RG01, L, VTR_),
FMT(R16G16_UINT, RG16UI, RG01, L, VTR_),
FMT(R32G32_UINT, RG32UI, RG01, L, VTR_),
FMT(R8G8B8_UINT, RGB8UI, RGB1, L, VTR_),
FMT(R32G32B32_UINT, RGB32UI, RGB1, L, VTR_),
FMT(R8G8B8A8_UINT, RGBA8UI, RGBA, L, VTR_),
FMT(R16G16B16A16_UINT, RGBA16UI, RGBA, L, VTR_),
FMT(R32G32B32A32_UINT, RGBA32UI, RGBA, L, VTR_),
FMT(R32_FLOAT, R32F, R001, L, VTR_),
FMT(R32G32_FLOAT, RG32F, RG01, L, VTR_),
FMT(R32G32B32_FLOAT, RGB32F, RGB1, L, VTR_),
FMT(R32G32B32A32_FLOAT, RGBA32F, RGBA, L, VTR_),
FMT(R8_UNORM, R8_UNORM, R001, L, VTR_),
FMT(R16_UNORM, R16_UNORM, R001, L, VTR_),
FMT(R8G8_UNORM, RG8_UNORM, RG01, L, VTR_),
FMT(R16G16_UNORM, RG16_UNORM, RG01, L, VTR_),
FMT(R8G8B8_UNORM, RGB8_UNORM, RGB1, L, VTR_),
FMT(R10G10B10A2_UINT, RGB10_A2UI, RGBA, L, VTR_),
FMT(B10G10R10A2_UINT, RGB10_A2UI, BGRA, L, VTR_),
FMT(R10G10B10A2_USCALED, RGB10_A2UI, RGBA, L, V___),
FMT(B10G10R10A2_USCALED, RGB10_A2UI, BGRA, L, V___),
FMT(R10G10B10A2_SINT, RGB10_A2I, RGBA, L, VTR_),
FMT(B10G10R10A2_SINT, RGB10_A2I, BGRA, L, VTR_),
FMT(R10G10B10A2_SSCALED, RGB10_A2I, RGBA, L, V___),
FMT(B10G10R10A2_SSCALED, RGB10_A2I, BGRA, L, V___),
FMT(R8_SSCALED, R8I, R001, L, V___),
FMT(R8G8_SSCALED, RG8I, RG01, L, V___),
FMT(R8G8B8_SSCALED, RGB8I, RGB1, L, V___),
FMT(B8G8R8_SSCALED, RGB8I, BGR1, L, V___),
FMT(R8G8B8A8_SSCALED, RGBA8I, RGBA, L, V___),
FMT(B8G8R8A8_SSCALED, RGBA8I, BGRA, L, V___),
FMT(A8B8G8R8_SSCALED, RGBA8I, ABGR, L, V___),
FMT(R8_USCALED, R8UI, R001, L, V___),
FMT(R8G8_USCALED, RG8UI, RG01, L, V___),
FMT(R8G8B8_USCALED, RGB8UI, RGB1, L, V___),
FMT(B8G8R8_USCALED, RGB8UI, BGR1, L, V___),
FMT(R8G8B8A8_USCALED, RGBA8UI, RGBA, L, V___),
FMT(B8G8R8A8_USCALED, RGBA8UI, BGRA, L, V___),
FMT(A8B8G8R8_USCALED, RGBA8UI, ABGR, L, V___),
FMT(R16_USCALED, R16UI, R001, L, V___),
FMT(R16G16_USCALED, RG16UI, RG01, L, V___),
FMT(R16G16B16A16_USCALED, RGBA16UI, RGBA, L, V___),
FMT(R16_SSCALED, R16I, R001, L, V___),
FMT(R16G16_SSCALED, RG16I, RG01, L, V___),
FMT(R16G16B16A16_SSCALED, RGBA16I, RGBA, L, V___),
FMT(R32_USCALED, R32UI, R001, L, V___),
FMT(R32G32_USCALED, RG32UI, RG01, L, V___),
FMT(R32G32B32_USCALED, RGB32UI, RGB1, L, V___),
FMT(R32G32B32A32_USCALED, RGBA32UI, RGBA, L, V___),
FMT(R32_SSCALED, R32I, R001, L, V___),
FMT(R32G32_SSCALED, RG32I, RG01, L, V___),
FMT(R32G32B32_SSCALED, RGB32I, RGB1, L, V___),
FMT(R32G32B32A32_SSCALED, RGBA32I, RGBA, L, V___),
FMT(R32_FIXED, R32_FIXED, R001, L, V___),
FMT(R32G32_FIXED, RG32_FIXED, RG01, L, V___),
FMT(R32G32B32_FIXED, RGB32_FIXED, RGB1, L, V___),
FMT(R32G32B32A32_FIXED, RGBA32_FIXED, RGBA, L, V___),
FMT(R11G11B10_FLOAT, R11F_G11F_B10F, RGB1, L, VTR_),
FMT(R9G9B9E5_FLOAT, R9F_G9F_B9F_E5F, RGB1, L, VT__),
FMT(R8_SNORM, R8_SNORM, R001, L, VT__),
FMT(R16_SNORM, R16_SNORM, R001, L, VT__),
FMT(R8G8_SNORM, RG8_SNORM, RG01, L, VT__),
FMT(R16G16_SNORM, RG16_SNORM, RG01, L, VT__),
FMT(R8G8B8_SNORM, RGB8_SNORM, RGB1, L, VT__),
FMT(R8G8B8A8_SNORM, RGBA8_SNORM, RGBA, L, VT__),
FMT(R16G16B16A16_SNORM, RGBA16_SNORM, RGBA, L, VT__),
FMT(I8_SINT, R8I, RRRR, L, VTR_),
FMT(L8_SINT, R8I, RRR1, L, VTR_),
FMT(I8_UINT, R8UI, RRRR, L, VTR_),
FMT(L8_UINT, R8UI, RRR1, L, VTR_),
FMT(I16_SINT, R16I, RRRR, L, VTR_),
FMT(L16_SINT, R16I, RRR1, L, VTR_),
FMT(I16_UINT, R16UI, RRRR, L, VTR_),
FMT(L16_UINT, R16UI, RRR1, L, VTR_),
FMT(I32_SINT, R32I, RRRR, L, VTR_),
FMT(L32_SINT, R32I, RRR1, L, VTR_),
FMT(I32_UINT, R32UI, RRRR, L, VTR_),
FMT(L32_UINT, R32UI, RRR1, L, VTR_),
FMT(B8G8R8_UINT, RGB8UI, BGR1, L, VTR_),
FMT(B8G8R8A8_UINT, RGBA8UI, BGRA, L, VTR_),
FMT(B8G8R8_SINT, RGB8I, BGR1, L, VTR_),
FMT(B8G8R8A8_SINT, RGBA8I, BGRA, L, VTR_),
FMT(A8R8G8B8_UINT, RGBA8UI, GBAR, L, VTR_),
FMT(A8B8G8R8_UINT, RGBA8UI, ABGR, L, VTR_),
FMT(R8_UINT, R8UI, R001, L, VTR_),
FMT(R16_UINT, R16UI, R001, L, VTR_),
FMT(R32_UINT, R32UI, R001, L, VTR_),
FMT(R8G8_UINT, RG8UI, RG01, L, VTR_),
FMT(R16G16_UINT, RG16UI, RG01, L, VTR_),
FMT(R32G32_UINT, RG32UI, RG01, L, VTR_),
FMT(R8G8B8_UINT, RGB8UI, RGB1, L, VTR_),
FMT(R32G32B32_UINT, RGB32UI, RGB1, L, VTR_),
FMT(R8G8B8A8_UINT, RGBA8UI, RGBA, L, VTR_),
FMT(R16G16B16A16_UINT, RGBA16UI, RGBA, L, VTR_),
FMT(R32G32B32A32_UINT, RGBA32UI, RGBA, L, VTR_),
FMT(R32_FLOAT, R32F, R001, L, VTR_),
FMT(R32G32_FLOAT, RG32F, RG01, L, VTR_),
FMT(R32G32B32_FLOAT, RGB32F, RGB1, L, VTR_),
FMT(R32G32B32A32_FLOAT, RGBA32F, RGBA, L, VTR_),
FMT(R8_UNORM, R8_UNORM, R001, L, VTR_),
FMT(R16_UNORM, R16_UNORM, R001, L, VTR_),
FMT(R8G8_UNORM, RG8_UNORM, RG01, L, VTR_),
FMT(R16G16_UNORM, RG16_UNORM, RG01, L, VTR_),
FMT(R8G8B8_UNORM, RGB8_UNORM, RGB1, L, VTR_),
/* 32-bit NORM is not texturable in v7 onwards. It's renderable
* everywhere, but rendering without texturing is not useful.
*/
/* 32-bit NORM is not texturable in v7 onwards. It's renderable
* everywhere, but rendering without texturing is not useful.
*/
#if PAN_ARCH <= 6
FMT(R32_UNORM, R32_UNORM, R001, L, VTR_),
FMT(R32G32_UNORM, RG32_UNORM, RG01, L, VTR_),
FMT(R32G32B32_UNORM, RGB32_UNORM, RGB1, L, VT__),
FMT(R32G32B32A32_UNORM, RGBA32_UNORM, RGBA, L, VTR_),
FMT(R32_SNORM, R32_SNORM, R001, L, VT__),
FMT(R32G32_SNORM, RG32_SNORM, RG01, L, VT__),
FMT(R32G32B32_SNORM, RGB32_SNORM, RGB1, L, VT__),
FMT(R32G32B32A32_SNORM, RGBA32_SNORM, RGBA, L, VT__),
FMT(R32_UNORM, R32_UNORM, R001, L, VTR_),
FMT(R32G32_UNORM, RG32_UNORM, RG01, L, VTR_),
FMT(R32G32B32_UNORM, RGB32_UNORM, RGB1, L, VT__),
FMT(R32G32B32A32_UNORM, RGBA32_UNORM, RGBA, L, VTR_),
FMT(R32_SNORM, R32_SNORM, R001, L, VT__),
FMT(R32G32_SNORM, RG32_SNORM, RG01, L, VT__),
FMT(R32G32B32_SNORM, RGB32_SNORM, RGB1, L, VT__),
FMT(R32G32B32A32_SNORM, RGBA32_SNORM, RGBA, L, VT__),
#else
FMT(R32_UNORM, R32_UNORM, R001, L, V___),
FMT(R32G32_UNORM, RG32_UNORM, RG01, L, V___),
FMT(R32G32B32_UNORM, RGB32_UNORM, RGB1, L, V___),
FMT(R32G32B32A32_UNORM, RGBA32_UNORM, RGBA, L, V___),
FMT(R32_SNORM, R32_SNORM, R001, L, V___),
FMT(R32G32_SNORM, RG32_SNORM, RG01, L, V___),
FMT(R32G32B32_SNORM, RGB32_SNORM, RGB1, L, V___),
FMT(R32G32B32A32_SNORM, RGBA32_SNORM, RGBA, L, V___),
FMT(R32_UNORM, R32_UNORM, R001, L, V___),
FMT(R32G32_UNORM, RG32_UNORM, RG01, L, V___),
FMT(R32G32B32_UNORM, RGB32_UNORM, RGB1, L, V___),
FMT(R32G32B32A32_UNORM, RGBA32_UNORM, RGBA, L, V___),
FMT(R32_SNORM, R32_SNORM, R001, L, V___),
FMT(R32G32_SNORM, RG32_SNORM, RG01, L, V___),
FMT(R32G32B32_SNORM, RGB32_SNORM, RGB1, L, V___),
FMT(R32G32B32A32_SNORM, RGBA32_SNORM, RGBA, L, V___),
#endif
/* Don't allow render/texture for 48-bit */
FMT(R16G16B16_UNORM, RGB16_UNORM, RGB1, L, V___),
FMT(R16G16B16_SINT, RGB16I, RGB1, L, V___),
FMT(R16G16B16_FLOAT, RGB16F, RGB1, L, V___),
FMT(R16G16B16_USCALED, RGB16UI, RGB1, L, V___),
FMT(R16G16B16_SSCALED, RGB16I, RGB1, L, V___),
FMT(R16G16B16_SNORM, RGB16_SNORM, RGB1, L, V___),
FMT(R16G16B16_UINT, RGB16UI, RGB1, L, V___),
FMT(R4G4B4A4_UNORM, RGBA4_UNORM, RGBA, L, VTR_),
FMT(B4G4R4A4_UNORM, RGBA4_UNORM, BGRA, L, VTR_),
FMT(R16G16B16A16_UNORM, RGBA16_UNORM, RGBA, L, VTR_),
FMT(B8G8R8A8_UNORM, RGBA8_UNORM, BGRA, L, VTR_),
FMT(B8G8R8X8_UNORM, RGBA8_UNORM, BGR1, L, VTR_),
FMT(A8R8G8B8_UNORM, RGBA8_UNORM, GBAR, L, VTR_),
FMT(X8R8G8B8_UNORM, RGBA8_UNORM, GBA1, L, VTR_),
FMT(A8B8G8R8_UNORM, RGBA8_UNORM, ABGR, L, VTR_),
FMT(X8B8G8R8_UNORM, RGBA8_UNORM, ABG1, L, VTR_),
FMT(R8G8B8X8_UNORM, RGBA8_UNORM, RGB1, L, VTR_),
FMT(R8G8B8A8_UNORM, RGBA8_UNORM, RGBA, L, VTR_),
FMT(R8G8B8X8_SNORM, RGBA8_SNORM, RGB1, L, VT__),
FMT(R8G8B8X8_SRGB, RGBA8_UNORM, RGB1, S, VTR_),
FMT(R8G8B8X8_UINT, RGBA8UI, RGB1, L, VTR_),
FMT(R8G8B8X8_SINT, RGBA8I, RGB1, L, VTR_),
FMT(L8_UNORM, R8_UNORM, RRR1, L, VTR_),
FMT(I8_UNORM, R8_UNORM, RRRR, L, VTR_),
FMT(L16_UNORM, R16_UNORM, RRR1, L, VT__),
FMT(I16_UNORM, R16_UNORM, RRRR, L, VT__),
FMT(L8_SNORM, R8_SNORM, RRR1, L, VT__),
FMT(I8_SNORM, R8_SNORM, RRRR, L, VT__),
FMT(L16_SNORM, R16_SNORM, RRR1, L, VT__),
FMT(I16_SNORM, R16_SNORM, RRRR, L, VT__),
FMT(L16_FLOAT, R16F, RRR1, L, VTR_),
FMT(I16_FLOAT, RG16F, RRRR, L, VTR_),
FMT(L8_SRGB, R8_UNORM, RRR1, S, VTR_),
FMT(R8_SRGB, R8_UNORM, R001, S, VTR_),
FMT(R8G8_SRGB, RG8_UNORM, RG01, S, VTR_),
FMT(R8G8B8_SRGB, RGB8_UNORM, RGB1, S, VTR_),
FMT(B8G8R8_SRGB, RGB8_UNORM, BGR1, S, VTR_),
FMT(R8G8B8A8_SRGB, RGBA8_UNORM, RGBA, S, VTR_),
FMT(A8B8G8R8_SRGB, RGBA8_UNORM, ABGR, S, VTR_),
FMT(X8B8G8R8_SRGB, RGBA8_UNORM, ABG1, S, VTR_),
FMT(B8G8R8A8_SRGB, RGBA8_UNORM, BGRA, S, VTR_),
FMT(B8G8R8X8_SRGB, RGBA8_UNORM, BGR1, S, VTR_),
FMT(A8R8G8B8_SRGB, RGBA8_UNORM, GBAR, S, VTR_),
FMT(X8R8G8B8_SRGB, RGBA8_UNORM, GBA1, S, VTR_),
FMT(R8_SINT, R8I, R001, L, VTR_),
FMT(R16_SINT, R16I, R001, L, VTR_),
FMT(R32_SINT, R32I, R001, L, VTR_),
FMT(R16_FLOAT, R16F, R001, L, VTR_),
FMT(R8G8_SINT, RG8I, RG01, L, VTR_),
FMT(R16G16_SINT, RG16I, RG01, L, VTR_),
FMT(R32G32_SINT, RG32I, RG01, L, VTR_),
FMT(R16G16_FLOAT, RG16F, RG01, L, VTR_),
FMT(R8G8B8_SINT, RGB8I, RGB1, L, VTR_),
FMT(R32G32B32_SINT, RGB32I, RGB1, L, VTR_),
FMT(R8G8B8A8_SINT, RGBA8I, RGBA, L, VTR_),
FMT(R16G16B16A16_SINT, RGBA16I, RGBA, L, VTR_),
FMT(R32G32B32A32_SINT, RGBA32I, RGBA, L, VTR_),
FMT(R16G16B16A16_FLOAT, RGBA16F, RGBA, L, VTR_),
FMT(R16G16B16X16_UNORM, RGBA16_UNORM, RGB1, L, VTR_),
FMT(R16G16B16X16_SNORM, RGBA16_SNORM, RGB1, L, VT__),
FMT(R16G16B16X16_FLOAT, RGBA16F, RGB1, L, VTR_),
FMT(R16G16B16X16_UINT, RGBA16UI, RGB1, L, VTR_),
FMT(R16G16B16X16_SINT, RGBA16I, RGB1, L, VTR_),
FMT(R32G32B32X32_FLOAT, RGBA32F, RGB1, L, VTR_),
FMT(R32G32B32X32_UINT, RGBA32UI, RGB1, L, VTR_),
FMT(R32G32B32X32_SINT, RGBA32I, RGB1, L, VTR_),
/* Don't allow render/texture for 48-bit */
FMT(R16G16B16_UNORM, RGB16_UNORM, RGB1, L, V___),
FMT(R16G16B16_SINT, RGB16I, RGB1, L, V___),
FMT(R16G16B16_FLOAT, RGB16F, RGB1, L, V___),
FMT(R16G16B16_USCALED, RGB16UI, RGB1, L, V___),
FMT(R16G16B16_SSCALED, RGB16I, RGB1, L, V___),
FMT(R16G16B16_SNORM, RGB16_SNORM, RGB1, L, V___),
FMT(R16G16B16_UINT, RGB16UI, RGB1, L, V___),
FMT(R4G4B4A4_UNORM, RGBA4_UNORM, RGBA, L, VTR_),
FMT(B4G4R4A4_UNORM, RGBA4_UNORM, BGRA, L, VTR_),
FMT(R16G16B16A16_UNORM, RGBA16_UNORM, RGBA, L, VTR_),
FMT(B8G8R8A8_UNORM, RGBA8_UNORM, BGRA, L, VTR_),
FMT(B8G8R8X8_UNORM, RGBA8_UNORM, BGR1, L, VTR_),
FMT(A8R8G8B8_UNORM, RGBA8_UNORM, GBAR, L, VTR_),
FMT(X8R8G8B8_UNORM, RGBA8_UNORM, GBA1, L, VTR_),
FMT(A8B8G8R8_UNORM, RGBA8_UNORM, ABGR, L, VTR_),
FMT(X8B8G8R8_UNORM, RGBA8_UNORM, ABG1, L, VTR_),
FMT(R8G8B8X8_UNORM, RGBA8_UNORM, RGB1, L, VTR_),
FMT(R8G8B8A8_UNORM, RGBA8_UNORM, RGBA, L, VTR_),
FMT(R8G8B8X8_SNORM, RGBA8_SNORM, RGB1, L, VT__),
FMT(R8G8B8X8_SRGB, RGBA8_UNORM, RGB1, S, VTR_),
FMT(R8G8B8X8_UINT, RGBA8UI, RGB1, L, VTR_),
FMT(R8G8B8X8_SINT, RGBA8I, RGB1, L, VTR_),
FMT(L8_UNORM, R8_UNORM, RRR1, L, VTR_),
FMT(I8_UNORM, R8_UNORM, RRRR, L, VTR_),
FMT(L16_UNORM, R16_UNORM, RRR1, L, VT__),
FMT(I16_UNORM, R16_UNORM, RRRR, L, VT__),
FMT(L8_SNORM, R8_SNORM, RRR1, L, VT__),
FMT(I8_SNORM, R8_SNORM, RRRR, L, VT__),
FMT(L16_SNORM, R16_SNORM, RRR1, L, VT__),
FMT(I16_SNORM, R16_SNORM, RRRR, L, VT__),
FMT(L16_FLOAT, R16F, RRR1, L, VTR_),
FMT(I16_FLOAT, RG16F, RRRR, L, VTR_),
FMT(L8_SRGB, R8_UNORM, RRR1, S, VTR_),
FMT(R8_SRGB, R8_UNORM, R001, S, VTR_),
FMT(R8G8_SRGB, RG8_UNORM, RG01, S, VTR_),
FMT(R8G8B8_SRGB, RGB8_UNORM, RGB1, S, VTR_),
FMT(B8G8R8_SRGB, RGB8_UNORM, BGR1, S, VTR_),
FMT(R8G8B8A8_SRGB, RGBA8_UNORM, RGBA, S, VTR_),
FMT(A8B8G8R8_SRGB, RGBA8_UNORM, ABGR, S, VTR_),
FMT(X8B8G8R8_SRGB, RGBA8_UNORM, ABG1, S, VTR_),
FMT(B8G8R8A8_SRGB, RGBA8_UNORM, BGRA, S, VTR_),
FMT(B8G8R8X8_SRGB, RGBA8_UNORM, BGR1, S, VTR_),
FMT(A8R8G8B8_SRGB, RGBA8_UNORM, GBAR, S, VTR_),
FMT(X8R8G8B8_SRGB, RGBA8_UNORM, GBA1, S, VTR_),
FMT(R8_SINT, R8I, R001, L, VTR_),
FMT(R16_SINT, R16I, R001, L, VTR_),
FMT(R32_SINT, R32I, R001, L, VTR_),
FMT(R16_FLOAT, R16F, R001, L, VTR_),
FMT(R8G8_SINT, RG8I, RG01, L, VTR_),
FMT(R16G16_SINT, RG16I, RG01, L, VTR_),
FMT(R32G32_SINT, RG32I, RG01, L, VTR_),
FMT(R16G16_FLOAT, RG16F, RG01, L, VTR_),
FMT(R8G8B8_SINT, RGB8I, RGB1, L, VTR_),
FMT(R32G32B32_SINT, RGB32I, RGB1, L, VTR_),
FMT(R8G8B8A8_SINT, RGBA8I, RGBA, L, VTR_),
FMT(R16G16B16A16_SINT, RGBA16I, RGBA, L, VTR_),
FMT(R32G32B32A32_SINT, RGBA32I, RGBA, L, VTR_),
FMT(R16G16B16A16_FLOAT, RGBA16F, RGBA, L, VTR_),
FMT(R16G16B16X16_UNORM, RGBA16_UNORM, RGB1, L, VTR_),
FMT(R16G16B16X16_SNORM, RGBA16_SNORM, RGB1, L, VT__),
FMT(R16G16B16X16_FLOAT, RGBA16F, RGB1, L, VTR_),
FMT(R16G16B16X16_UINT, RGBA16UI, RGB1, L, VTR_),
FMT(R16G16B16X16_SINT, RGBA16I, RGB1, L, VTR_),
FMT(R32G32B32X32_FLOAT, RGBA32F, RGB1, L, VTR_),
FMT(R32G32B32X32_UINT, RGBA32UI, RGB1, L, VTR_),
FMT(R32G32B32X32_SINT, RGBA32I, RGB1, L, VTR_),
#if PAN_ARCH <= 6
FMT(Z16_UNORM, R16_UNORM, RRRR, L, _T_Z),
FMT(Z24_UNORM_S8_UINT, Z24X8_UNORM, RRRR, L, _T_Z),
FMT(Z24X8_UNORM, Z24X8_UNORM, RRRR, L, _T_Z),
FMT(Z32_FLOAT, R32F, RRRR, L, _T_Z),
FMT(Z32_FLOAT_S8X24_UINT, RG32F, RRRR, L, _T_Z),
FMT(X32_S8X24_UINT, X32_S8X24, GGGG, L, _T_Z),
FMT(X24S8_UINT, RGBA8UI, AAAA, L, _T_Z),
FMT(S8_UINT, R8UI, RRRR, L, _T__),
FMT(Z16_UNORM, R16_UNORM, RRRR, L, _T_Z),
FMT(Z24_UNORM_S8_UINT, Z24X8_UNORM, RRRR, L, _T_Z),
FMT(Z24X8_UNORM, Z24X8_UNORM, RRRR, L, _T_Z),
FMT(Z32_FLOAT, R32F, RRRR, L, _T_Z),
FMT(Z32_FLOAT_S8X24_UINT, RG32F, RRRR, L, _T_Z),
FMT(X32_S8X24_UINT, X32_S8X24, GGGG, L, _T_Z),
FMT(X24S8_UINT, RGBA8UI, AAAA, L, _T_Z),
FMT(S8_UINT, R8UI, RRRR, L, _T__),
FMT(A8_UNORM, R8_UNORM, 000R, L, VTR_),
FMT(L8A8_UNORM, RG8_UNORM, RRRG, L, VTR_),
FMT(L8A8_SRGB, RG8_UNORM, RRRG, S, VTR_),
FMT(A8_UNORM, R8_UNORM, 000R, L, VTR_),
FMT(L8A8_UNORM, RG8_UNORM, RRRG, L, VTR_),
FMT(L8A8_SRGB, RG8_UNORM, RRRG, S, VTR_),
/* These formats were removed in v7 */
FMT(A8_SNORM, R8_SNORM, 000R, L, VT__),
FMT(A8_SINT, R8I, 000R, L, VTR_),
FMT(A8_UINT, R8UI, 000R, L, VTR_),
FMT(A16_SINT, R16I, 000R, L, VTR_),
FMT(A16_UINT, R16UI, 000R, L, VTR_),
FMT(A32_SINT, R32I, 000R, L, VTR_),
FMT(A32_UINT, R32UI, 000R, L, VTR_),
FMT(A16_UNORM, R16_UNORM, 000R, L, VT__),
FMT(A16_SNORM, R16_SNORM, 000R, L, VT__),
FMT(A16_FLOAT, R16F, 000R, L, VTR_),
/* These formats were removed in v7 */
FMT(A8_SNORM, R8_SNORM, 000R, L, VT__),
FMT(A8_SINT, R8I, 000R, L, VTR_),
FMT(A8_UINT, R8UI, 000R, L, VTR_),
FMT(A16_SINT, R16I, 000R, L, VTR_),
FMT(A16_UINT, R16UI, 000R, L, VTR_),
FMT(A32_SINT, R32I, 000R, L, VTR_),
FMT(A32_UINT, R32UI, 000R, L, VTR_),
FMT(A16_UNORM, R16_UNORM, 000R, L, VT__),
FMT(A16_SNORM, R16_SNORM, 000R, L, VT__),
FMT(A16_FLOAT, R16F, 000R, L, VTR_),
#else
FMT(Z16_UNORM, Z16_UNORM, RGBA, L, _T_Z),
FMT(Z24_UNORM_S8_UINT, Z24X8_UNORM, RGBA, L, _T_Z),
FMT(Z24X8_UNORM, Z24X8_UNORM, RGBA, L, _T_Z),
FMT(Z32_FLOAT, R32F, RGBA, L, _T_Z),
FMT(Z16_UNORM, Z16_UNORM, RGBA, L, _T_Z),
FMT(Z24_UNORM_S8_UINT, Z24X8_UNORM, RGBA, L, _T_Z),
FMT(Z24X8_UNORM, Z24X8_UNORM, RGBA, L, _T_Z),
FMT(Z32_FLOAT, R32F, RGBA, L, _T_Z),
#if PAN_ARCH >= 9
/* Specify interchange formats, the actual format for depth/stencil is
* determined by the plane descriptor on Valhall.
*
* On Valhall, S8 logically acts like "X8S8", so "S8 RGBA" is logically
* "0s00" and "S8 GRBA" is logically "s000". For Bifrost compatibility
* we want stencil in the red channel, so we use the GRBA swizzles.
*/
FMT(Z32_FLOAT_S8X24_UINT, R32F, GRBA, L, _T_Z),
FMT(X32_S8X24_UINT, S8, GRBA, L, _T__),
FMT(X24S8_UINT, S8, GRBA, L, _T_Z),
FMT(S8_UINT, S8, GRBA, L, _T__),
/* Specify interchange formats, the actual format for depth/stencil is
* determined by the plane descriptor on Valhall.
*
* On Valhall, S8 logically acts like "X8S8", so "S8 RGBA" is logically
* "0s00" and "S8 GRBA" is logically "s000". For Bifrost compatibility
* we want stencil in the red channel, so we use the GRBA swizzles.
*/
FMT(Z32_FLOAT_S8X24_UINT, R32F, GRBA, L, _T_Z),
FMT(X32_S8X24_UINT, S8, GRBA, L, _T__),
FMT(X24S8_UINT, S8, GRBA, L, _T_Z),
FMT(S8_UINT, S8, GRBA, L, _T__),
#else
/* Specify real formats on Bifrost */
FMT(Z32_FLOAT_S8X24_UINT, Z32_X32, RGBA, L, _T_Z),
FMT(X32_S8X24_UINT, X32_S8X24, GRBA, L, _T__),
FMT(X24S8_UINT, X24S8, GRBA, L, _T_Z),
FMT(S8_UINT, S8, GRBA, L, _T__),
/* Specify real formats on Bifrost */
FMT(Z32_FLOAT_S8X24_UINT, Z32_X32, RGBA, L, _T_Z),
FMT(X32_S8X24_UINT, X32_S8X24, GRBA, L, _T__),
FMT(X24S8_UINT, X24S8, GRBA, L, _T_Z),
FMT(S8_UINT, S8, GRBA, L, _T__),
/* Obsolete formats removed in Valhall */
FMT(A8_UNORM, A8_UNORM, 000A, L, VTR_),
FMT(L8A8_UNORM, R8A8_UNORM, RRRA, L, VTR_),
FMT(L8A8_SRGB, R8A8_UNORM, RRRA, S, VTR_),
/* Obsolete formats removed in Valhall */
FMT(A8_UNORM, A8_UNORM, 000A, L, VTR_),
FMT(L8A8_UNORM, R8A8_UNORM, RRRA, L, VTR_),
FMT(L8A8_SRGB, R8A8_UNORM, RRRA, S, VTR_),
#endif
#endif
};
/* clang-format on */
#if PAN_ARCH == 7
/*
@ -616,8 +618,8 @@ GENX(pan_decompose_swizzle)(enum mali_rgb_component_order order)
return (struct pan_decomposed_swizzle) { \
MALI_RGB_COMPONENT_ORDER_##pre_, { \
PIPE_SWIZZLE_##R_, PIPE_SWIZZLE_##G_, \
PIPE_SWIZZLE_##B_, PIPE_SWIZZLE_##A_ \
} \
PIPE_SWIZZLE_##B_, PIPE_SWIZZLE_##A_, \
}, \
};
switch (order) {

51
src/panfrost/lib/pan_layout.c
View file

@ -27,44 +27,43 @@
#include "util/u_math.h"
#include "pan_texture.h"
/* List of supported modifiers, in descending order of preference. AFBC is
/*
* List of supported modifiers, in descending order of preference. AFBC is
* faster than u-interleaved tiling which is faster than linear. Within AFBC,
* enabling the YUV-like transform is typically a win where possible. */
* enabling the YUV-like transform is typically a win where possible.
*/
/* clang-format on */
uint64_t pan_best_modifiers[PAN_MODIFIER_COUNT] = {
DRM_FORMAT_MOD_ARM_AFBC(
AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_TILED |
AFBC_FORMAT_MOD_SC |
AFBC_FORMAT_MOD_SPARSE |
AFBC_FORMAT_MOD_YTR),
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_TILED |
AFBC_FORMAT_MOD_SC |
AFBC_FORMAT_MOD_SPARSE |
AFBC_FORMAT_MOD_YTR),
DRM_FORMAT_MOD_ARM_AFBC(
AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_TILED |
AFBC_FORMAT_MOD_SC |
AFBC_FORMAT_MOD_SPARSE),
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_TILED |
AFBC_FORMAT_MOD_SC |
AFBC_FORMAT_MOD_SPARSE),
DRM_FORMAT_MOD_ARM_AFBC(
AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_SPARSE |
AFBC_FORMAT_MOD_YTR),
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_SPARSE |
AFBC_FORMAT_MOD_YTR),
DRM_FORMAT_MOD_ARM_AFBC(
AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_SPARSE),
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
AFBC_FORMAT_MOD_SPARSE),
DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED,
DRM_FORMAT_MOD_LINEAR
DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED,
DRM_FORMAT_MOD_LINEAR
};
/* Table of AFBC superblock sizes */
static const struct pan_block_size
afbc_superblock_sizes[] = {
[AFBC_FORMAT_MOD_BLOCK_SIZE_16x16] = { 16, 16 },
[AFBC_FORMAT_MOD_BLOCK_SIZE_32x8] = { 32, 8 },
[AFBC_FORMAT_MOD_BLOCK_SIZE_64x4] = { 64, 4 },
[AFBC_FORMAT_MOD_BLOCK_SIZE_16x16] = { 16, 16 },
[AFBC_FORMAT_MOD_BLOCK_SIZE_32x8] = { 32, 8 },
[AFBC_FORMAT_MOD_BLOCK_SIZE_64x4] = { 64, 4 },
};
/* clang-format off */
/*
* Given an AFBC modifier, return the superblock size.

34
src/panfrost/lib/pan_props.c
View file

@ -53,24 +53,26 @@
}
/* Table of supported Mali GPUs */
/* clang-format off */
const struct panfrost_model panfrost_model_list[] = {
MODEL(0x620, "T620", "T62x", NO_ANISO, 8192, {}),
MODEL(0x720, "T720", "T72x", NO_ANISO, 8192, { .no_hierarchical_tiling = true }),
MODEL(0x750, "T760", "T76x", NO_ANISO, 8192, {}),
MODEL(0x820, "T820", "T82x", NO_ANISO, 8192, { .no_hierarchical_tiling = true }),
MODEL(0x830, "T830", "T83x", NO_ANISO, 8192, { .no_hierarchical_tiling = true }),
MODEL(0x860, "T860", "T86x", NO_ANISO, 8192, {}),
MODEL(0x880, "T880", "T88x", NO_ANISO, 8192, {}),
MODEL(0x620, "T620", "T62x", NO_ANISO, 8192, {}),
MODEL(0x720, "T720", "T72x", NO_ANISO, 8192, { .no_hierarchical_tiling = true }),
MODEL(0x750, "T760", "T76x", NO_ANISO, 8192, {}),
MODEL(0x820, "T820", "T82x", NO_ANISO, 8192, { .no_hierarchical_tiling = true }),
MODEL(0x830, "T830", "T83x", NO_ANISO, 8192, { .no_hierarchical_tiling = true }),
MODEL(0x860, "T860", "T86x", NO_ANISO, 8192, {}),
MODEL(0x880, "T880", "T88x", NO_ANISO, 8192, {}),
MODEL(0x6000, "G71", "TMIx", NO_ANISO, 8192, {}),
MODEL(0x6221, "G72", "THEx", 0x0030 /* r0p3 */, 16384, {}),
MODEL(0x7090, "G51", "TSIx", 0x1010 /* r1p1 */, 16384, {}),
MODEL(0x7093, "G31", "TDVx", HAS_ANISO, 16384, {}),
MODEL(0x7211, "G76", "TNOx", HAS_ANISO, 16384, {}),
MODEL(0x7212, "G52", "TGOx", HAS_ANISO, 16384, {}),
MODEL(0x7402, "G52 r1", "TGOx", HAS_ANISO, 16384, {}),
MODEL(0x9093, "G57", "TNAx", HAS_ANISO, 16384, {}),
MODEL(0x6000, "G71", "TMIx", NO_ANISO, 8192, {}),
MODEL(0x6221, "G72", "THEx", 0x0030 /* r0p3 */, 16384, {}),
MODEL(0x7090, "G51", "TSIx", 0x1010 /* r1p1 */, 16384, {}),
MODEL(0x7093, "G31", "TDVx", HAS_ANISO, 16384, {}),
MODEL(0x7211, "G76", "TNOx", HAS_ANISO, 16384, {}),
MODEL(0x7212, "G52", "TGOx", HAS_ANISO, 16384, {}),
MODEL(0x7402, "G52 r1", "TGOx", HAS_ANISO, 16384, {}),
MODEL(0x9093, "G57", "TNAx", HAS_ANISO, 16384, {}),
};
/* clang-format on */
#undef NO_ANISO
#undef HAS_ANISO
@ -149,7 +151,7 @@ panfrost_query_tiler_features(int fd)
/* Bin size is log2 in the first byte, max levels in the second byte */
return (struct panfrost_tiler_features) {
.bin_size = (1 << (raw & BITFIELD_MASK(5))),
.max_levels = (raw >> 8) & BITFIELD_MASK(4)
.max_levels = (raw >> 8) & BITFIELD_MASK(4),
};
}

119
src/panfrost/lib/pan_samples.c
View file

@ -60,71 +60,72 @@ struct mali_sample_positions {
#define SAMPLE8(x, y) SAMPLE16((x) * 2, (y) * 2)
#define SAMPLE4(x, y) SAMPLE16((x) * 4, (y) * 4)
/* clang-format off */
const struct mali_sample_positions sample_position_lut[] = {
[MALI_SAMPLE_PATTERN_SINGLE_SAMPLED] = {
.positions = {
SAMPLE4(0, 0)
},
.origin = SAMPLE4(0, 0)
},
[MALI_SAMPLE_PATTERN_SINGLE_SAMPLED] = {
.positions = {
SAMPLE4(0, 0)
},
.origin = SAMPLE4(0, 0)
},
[MALI_SAMPLE_PATTERN_ORDERED_4X_GRID] = {
.positions = {
SAMPLE4(-1, -1),
SAMPLE4( 1, -1),
SAMPLE4(-1, 1),
SAMPLE4( 1, 1),
},
.origin = SAMPLE4(0, 0)
},
[MALI_SAMPLE_PATTERN_ORDERED_4X_GRID] = {
.positions = {
SAMPLE4(-1, -1),
SAMPLE4( 1, -1),
SAMPLE4(-1, 1),
SAMPLE4( 1, 1),
},
.origin = SAMPLE4(0, 0)
},
[MALI_SAMPLE_PATTERN_ROTATED_4X_GRID] = {
.positions = {
SAMPLE8(-1, -3),
SAMPLE8( 3, -1),
SAMPLE8(-3, 1),
SAMPLE8( 1, 3),
},
.origin = SAMPLE8(0, 0)
},
[MALI_SAMPLE_PATTERN_ROTATED_4X_GRID] = {
.positions = {
SAMPLE8(-1, -3),
SAMPLE8( 3, -1),
SAMPLE8(-3, 1),
SAMPLE8( 1, 3),
},
.origin = SAMPLE8(0, 0)
},
[MALI_SAMPLE_PATTERN_D3D_8X_GRID] = {
.positions = {
SAMPLE16( 1, -3),
SAMPLE16(-1, 3),
SAMPLE16( 5, 1),
SAMPLE16(-3, -5),
SAMPLE16(-5, 5),
SAMPLE16(-7, -1),
SAMPLE16( 3, 7),
SAMPLE16( 7, -7),
},
.origin = SAMPLE16(0, 0)
},
[MALI_SAMPLE_PATTERN_D3D_8X_GRID] = {
.positions = {
SAMPLE16( 1, -3),
SAMPLE16(-1, 3),
SAMPLE16( 5, 1),
SAMPLE16(-3, -5),
SAMPLE16(-5, 5),
SAMPLE16(-7, -1),
SAMPLE16( 3, 7),
SAMPLE16( 7, -7),
},
.origin = SAMPLE16(0, 0)
},
[MALI_SAMPLE_PATTERN_D3D_16X_GRID] = {
.positions = {
SAMPLE16( 1, 1),
SAMPLE16(-1, -3),
SAMPLE16(-3, 2),
SAMPLE16( 4, -1),
SAMPLE16(-5, -2),
SAMPLE16( 2, 5),
SAMPLE16( 5, 3),
SAMPLE16( 3, -5),
SAMPLE16(-2, 6),
SAMPLE16( 0, 7),
SAMPLE16(-4, -6),
SAMPLE16(-6, 4),
SAMPLE16(-8, 0),
SAMPLE16( 7, -4),
SAMPLE16( 6, 7),
SAMPLE16(-7, -8),
},
.origin = SAMPLE16(0, 0)
}
[MALI_SAMPLE_PATTERN_D3D_16X_GRID] = {
.positions = {
SAMPLE16( 1, 1),
SAMPLE16(-1, -3),
SAMPLE16(-3, 2),
SAMPLE16( 4, -1),
SAMPLE16(-5, -2),
SAMPLE16( 2, 5),
SAMPLE16( 5, 3),
SAMPLE16( 3, -5),
SAMPLE16(-2, 6),
SAMPLE16( 0, 7),
SAMPLE16(-4, -6),
SAMPLE16(-6, 4),
SAMPLE16(-8, 0),
SAMPLE16( 7, -4),
SAMPLE16( 6, 7),
SAMPLE16(-7, -8),
},
.origin = SAMPLE16(0, 0)
}
};
/* clang-format on */
mali_ptr
panfrost_sample_positions(const struct panfrost_device *dev,

78
src/panfrost/lib/pan_texture.c
View file

@ -275,48 +275,50 @@ panfrost_get_surface_pointer(const struct pan_image_layout *layout,
#if PAN_ARCH >= 9
/* clang-format off */
#define CLUMP_FMT(pipe, mali) [PIPE_FORMAT_ ## pipe] = MALI_CLUMP_FORMAT_ ## mali
static enum mali_clump_format special_clump_formats[PIPE_FORMAT_COUNT] = {
CLUMP_FMT(X32_S8X24_UINT, X32S8X24),
CLUMP_FMT(X24S8_UINT, X24S8),
CLUMP_FMT(S8X24_UINT, S8X24),
CLUMP_FMT(S8_UINT, S8),
CLUMP_FMT(L4A4_UNORM, L4A4),
CLUMP_FMT(L8A8_UNORM, L8A8),
CLUMP_FMT(L8A8_UINT, L8A8),
CLUMP_FMT(L8A8_SINT, L8A8),
CLUMP_FMT(A8_UNORM, A8),
CLUMP_FMT(A8_UINT, A8),
CLUMP_FMT(A8_SINT, A8),
CLUMP_FMT(ETC1_RGB8, ETC2_RGB8),
CLUMP_FMT(ETC2_RGB8, ETC2_RGB8),
CLUMP_FMT(ETC2_SRGB8, ETC2_RGB8),
CLUMP_FMT(ETC2_RGB8A1, ETC2_RGB8A1),
CLUMP_FMT(ETC2_SRGB8A1, ETC2_RGB8A1),
CLUMP_FMT(ETC2_RGBA8, ETC2_RGBA8),
CLUMP_FMT(ETC2_SRGBA8, ETC2_RGBA8),
CLUMP_FMT(ETC2_R11_UNORM, ETC2_R11_UNORM),
CLUMP_FMT(ETC2_R11_SNORM, ETC2_R11_SNORM),
CLUMP_FMT(ETC2_RG11_UNORM, ETC2_RG11_UNORM),
CLUMP_FMT(ETC2_RG11_SNORM, ETC2_RG11_SNORM),
CLUMP_FMT(DXT1_RGB, BC1_UNORM),
CLUMP_FMT(DXT1_RGBA, BC1_UNORM),
CLUMP_FMT(DXT1_SRGB, BC1_UNORM),
CLUMP_FMT(DXT1_SRGBA, BC1_UNORM),
CLUMP_FMT(DXT3_RGBA, BC2_UNORM),
CLUMP_FMT(DXT3_SRGBA, BC2_UNORM),
CLUMP_FMT(DXT5_RGBA, BC3_UNORM),
CLUMP_FMT(DXT5_SRGBA, BC3_UNORM),
CLUMP_FMT(RGTC1_UNORM, BC4_UNORM),
CLUMP_FMT(RGTC1_SNORM, BC4_SNORM),
CLUMP_FMT(RGTC2_UNORM, BC5_UNORM),
CLUMP_FMT(RGTC2_SNORM, BC5_SNORM),
CLUMP_FMT(BPTC_RGB_FLOAT, BC6H_SF16),
CLUMP_FMT(BPTC_RGB_UFLOAT, BC6H_UF16),
CLUMP_FMT(BPTC_RGBA_UNORM, BC7_UNORM),
CLUMP_FMT(BPTC_SRGBA, BC7_UNORM),
CLUMP_FMT(X32_S8X24_UINT, X32S8X24),
CLUMP_FMT(X24S8_UINT, X24S8),
CLUMP_FMT(S8X24_UINT, S8X24),
CLUMP_FMT(S8_UINT, S8),
CLUMP_FMT(L4A4_UNORM, L4A4),
CLUMP_FMT(L8A8_UNORM, L8A8),
CLUMP_FMT(L8A8_UINT, L8A8),
CLUMP_FMT(L8A8_SINT, L8A8),
CLUMP_FMT(A8_UNORM, A8),
CLUMP_FMT(A8_UINT, A8),
CLUMP_FMT(A8_SINT, A8),
CLUMP_FMT(ETC1_RGB8, ETC2_RGB8),
CLUMP_FMT(ETC2_RGB8, ETC2_RGB8),
CLUMP_FMT(ETC2_SRGB8, ETC2_RGB8),
CLUMP_FMT(ETC2_RGB8A1, ETC2_RGB8A1),
CLUMP_FMT(ETC2_SRGB8A1, ETC2_RGB8A1),
CLUMP_FMT(ETC2_RGBA8, ETC2_RGBA8),
CLUMP_FMT(ETC2_SRGBA8, ETC2_RGBA8),
CLUMP_FMT(ETC2_R11_UNORM, ETC2_R11_UNORM),
CLUMP_FMT(ETC2_R11_SNORM, ETC2_R11_SNORM),
CLUMP_FMT(ETC2_RG11_UNORM, ETC2_RG11_UNORM),
CLUMP_FMT(ETC2_RG11_SNORM, ETC2_RG11_SNORM),
CLUMP_FMT(DXT1_RGB, BC1_UNORM),
CLUMP_FMT(DXT1_RGBA, BC1_UNORM),
CLUMP_FMT(DXT1_SRGB, BC1_UNORM),
CLUMP_FMT(DXT1_SRGBA, BC1_UNORM),
CLUMP_FMT(DXT3_RGBA, BC2_UNORM),
CLUMP_FMT(DXT3_SRGBA, BC2_UNORM),
CLUMP_FMT(DXT5_RGBA, BC3_UNORM),
CLUMP_FMT(DXT5_SRGBA, BC3_UNORM),
CLUMP_FMT(RGTC1_UNORM, BC4_UNORM),
CLUMP_FMT(RGTC1_SNORM, BC4_SNORM),
CLUMP_FMT(RGTC2_UNORM, BC5_UNORM),
CLUMP_FMT(RGTC2_SNORM, BC5_SNORM),
CLUMP_FMT(BPTC_RGB_FLOAT, BC6H_SF16),
CLUMP_FMT(BPTC_RGB_UFLOAT, BC6H_UF16),
CLUMP_FMT(BPTC_RGBA_UNORM, BC7_UNORM),
CLUMP_FMT(BPTC_SRGBA, BC7_UNORM),
};
#undef CLUMP_FMT
/* clang-format on */
static enum mali_clump_format
panfrost_clump_format(enum pipe_format format)

2
src/panfrost/lib/tests/test-blend.c
View file

@ -36,6 +36,7 @@ struct test {
uint32_t hardware;
};
/* clang-format off */
#define RGBA(key, value) \
.rgb_ ## key = value, \
.alpha_ ## key = value
@ -290,6 +291,7 @@ static const struct test blend_tests[] = {
.hardware = 0xC0431132 /* 0 + dest * (2*src); equivalent 0xC0431122 */
}
};
/* clang-format on */
#define ASSERT_EQ(x, y) do { \
if (x == y) { \

2
src/panfrost/lib/tests/test-clear.c
View file

@ -40,6 +40,7 @@ struct test {
#define D (true)
#define _ (false)
/* clang-format off */
static const struct test clear_tests[] = {
/* Basic tests */
{ PIPE_FORMAT_R8G8B8A8_UNORM, D, F(0.0, 0.0, 0.0, 0.0), RRRR(0x00000000) },
@ -137,6 +138,7 @@ static const struct test clear_tests[] = {
UI(0xCAFEBABE, 0xABAD1DEA, 0xDEADBEEF, 0xABCDEF01),
{ 0xCAFEBABE, 0xABAD1DEA, 0xDEADBEEF, 0xABCDEF01 } },
};
/* clang-format on */
#define ASSERT_EQ(x, y) do { \
if ((x[0] == y[0]) && (x[1] == y[1]) && (x[2] == y[2]) && (x[3] == y[3])) { \

4
src/panfrost/midgard/compiler.h
View file

@ -542,7 +542,7 @@ v_mov(unsigned src, unsigned dest)
.dest = dest,
.dest_type = nir_type_uint32,
.op = midgard_alu_op_imov,
.outmod = midgard_outmod_keeplo
.outmod = midgard_outmod_keeplo,
};
return ins;
@ -586,7 +586,7 @@ v_load_store_scratch(
},
/* If we spill an unspill, RA goes into an infinite loop */
.no_spill = (1 << REG_CLASS_WORK)
.no_spill = (1 << REG_CLASS_WORK),
};
ins.constants.u32[0] = byte;

26
src/panfrost/midgard/midgard_compile.c
View file

@ -52,13 +52,13 @@
#include "disassemble.h"
static const struct debug_named_value midgard_debug_options[] = {
{"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
{"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
{"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
{"inorder", MIDGARD_DBG_INORDER, "Disables out-of-order scheduling"},
{"verbose", MIDGARD_DBG_VERBOSE, "Dump shaders verbosely"},
{"internal", MIDGARD_DBG_INTERNAL, "Dump internal shaders"},
DEBUG_NAMED_VALUE_END
{"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
{"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
{"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
{"inorder", MIDGARD_DBG_INORDER, "Disables out-of-order scheduling"},
{"verbose", MIDGARD_DBG_VERBOSE, "Dump shaders verbosely"},
{"internal", MIDGARD_DBG_INTERNAL, "Dump internal shaders"},
DEBUG_NAMED_VALUE_END
};
DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", midgard_debug_options, 0)
@ -111,8 +111,8 @@ schedule_barrier(compiler_context *ctx)
.swizzle = SWIZZLE_IDENTITY_4, \
.op = midgard_op_##name, \
.load_store = { \
.signed_offset = address \
} \
.signed_offset = address, \
}, \
}; \
\
if (store) { \
@ -192,7 +192,7 @@ v_branch(bool conditional, bool invert)
.compact_branch = true,
.branch = {
.conditional = conditional,
.invert_conditional = invert
.invert_conditional = invert,
},
.dest = ~0,
.src = { ~0, ~0, ~0, ~0 },
@ -1383,8 +1383,8 @@ emit_atomic(
.type = TAG_LOAD_STORE_4,
.mask = 0xF,
.dest = dest,
.src = { ~0, ~0, ~0, val },
.src_types = { 0, 0, 0, type | bitsize },
.src = { ~0, ~0, ~0, val, },
.src_types = { 0, 0, 0, type | bitsize, },
.op = op
};
@ -2443,7 +2443,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
.format = midgard_tex_format(instr->sampler_dim),
.texture_handle = texture_index,
.sampler_handle = sampler_index,
.mode = mdg_texture_mode(instr)
.mode = mdg_texture_mode(instr),
}
};

6
src/panfrost/midgard/midgard_derivatives.c
View file

@ -103,9 +103,9 @@ midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr)
.mask = mask_of(nr_components),
.dest = nir_dest_index(&instr->dest.dest),
.dest_type = nir_type_float32,
.src = { ~0, nir_src_index(ctx, &instr->src[0].src), ~0, ~0 },
.src = { ~0, nir_src_index(ctx, &instr->src[0].src), ~0, ~0, },
.swizzle = SWIZZLE_IDENTITY_4,
.src_types = { nir_type_float32, nir_type_float32 },
.src_types = { nir_type_float32, nir_type_float32, },
.op = midgard_tex_op_derivative,
.texture = {
.mode = mir_derivative_mode(instr->op),
@ -113,7 +113,7 @@ midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr)
.in_reg_full = 1,
.out_full = 1,
.sampler_type = MALI_SAMPLER_FLOAT,
}
},
};
if (!instr->dest.dest.is_ssa)

18
src/panfrost/midgard/midgard_emit.c
View file

@ -110,7 +110,7 @@ mir_pack_scalar_source(unsigned mod, bool is_full, unsigned component)
midgard_scalar_alu_src s = {
.mod = mod,
.full = is_full,
.component = component << (is_full ? 1 : 0)
.component = component << (is_full ? 1 : 0),
};
unsigned o;
@ -140,7 +140,7 @@ vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
.src2 = packed_src[1],
.outmod = v.outmod,
.output_full = is_full,
.output_component = comp
.output_component = comp,
};
/* Full components are physically spaced out */
@ -348,7 +348,7 @@ mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu)
midgard_vector_alu_src pack = {
.mod = mir_pack_mod(ins, i, false),
.expand_mode = expand_mode,
.swizzle = swizzle
.swizzle = swizzle,
};
unsigned p = vector_alu_srco_unsigned(pack);
@ -638,7 +638,7 @@ texture_word_from_instr(midgard_instruction *ins)
midgard_tex_register_select sel = {
.select = SSA_REG_FROM_FIXED(ins->src[2]) & 1,
.full = 1,
.component = ins->swizzle[2][0]
.component = ins->swizzle[2][0],
};
uint8_t packed;
memcpy(&packed, &sel, sizeof(packed));
@ -672,7 +672,7 @@ vector_alu_from_instr(midgard_instruction *ins)
midgard_vector_alu alu = {
.op = ins->op,
.outmod = ins->outmod,
.reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins))
.reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)),
};
if (ins->has_inline_constant) {
@ -714,7 +714,7 @@ midgard_create_branch_extended( midgard_condition cond,
.op = op,
.dest_tag = dest_tag,
.offset = quadword_offset,
.cond = duplicated_cond
.cond = duplicated_cond,
};
return branch;
@ -803,7 +803,7 @@ emit_branch(midgard_instruction *ins,
.op = op,
.dest_tag = dest_tag,
.offset = quadword_offset,
.cond = cond
.cond = cond,
};
memcpy(util_dynarray_grow_bytes(emission, size, 1), &branch, size);
} else {
@ -812,7 +812,7 @@ emit_branch(midgard_instruction *ins,
.op = op,
.dest_tag = dest_tag,
.offset = quadword_offset,
.call_mode = midgard_call_mode_default
.call_mode = midgard_call_mode_default,
};
assert(branch.offset == quadword_offset);
memcpy(util_dynarray_grow_bytes(emission, size, 1), &branch, size);
@ -1000,7 +1000,7 @@ emit_binary_bundle(compiler_context *ctx,
.type = bundle->tag,
.next_type = next_tag,
.word1 = current64,
.word2 = next64
.word2 = next64,
};
util_dynarray_append(emission, midgard_load_store, instruction);

636
src/panfrost/midgard/midgard_ops.c
View file

@ -30,178 +30,181 @@
#include "midgard_ops.h"
/* Table of mapping opcodes to accompanying properties. This is used for both
/*
* Table of mapping opcodes to accompanying properties. This is used for both
* the disassembler and the compiler. It is placed in a .c file like this to
* avoid duplications in the binary */
* avoid duplications in the binary.
*/
/* clang-format off */
struct mir_op_props alu_opcode_props[256] = {
[midgard_alu_op_fadd] = {"FADD", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fadd_rtz] = {"FADD.rtz", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fadd_rtn] = {"FADD.rtn", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fadd_rtp] = {"FADD.rtp", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fmul] = {"FMUL", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmul_rtz] = {"FMUL.rtz", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmul_rtn] = {"FMUL.rtn", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmul_rtp] = {"FMUL.rtp", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmin] = {"FMIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fmin_nan] = {"FMIN.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmin] = {"FABSMIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmin_nan] = {"FABSMIN.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fmax] = {"FMAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fmax_nan] = {"FMAX.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmax] = {"FABSMAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmax_nan] = {"FABSMAX.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_imin] = {"MIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_imax] = {"MAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umin] = {"MIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umax] = {"MAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iavg] = {"AVG.rtz", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uavg] = {"AVG.rtz", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_iravg] = {"AVG.round", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uravg] = {"AVG.round", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fadd] = {"FADD", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fadd_rtz] = {"FADD.rtz", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fadd_rtn] = {"FADD.rtn", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fadd_rtp] = {"FADD.rtp", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fmul] = {"FMUL", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmul_rtz] = {"FMUL.rtz", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmul_rtn] = {"FMUL.rtn", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmul_rtp] = {"FMUL.rtp", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
[midgard_alu_op_fmin] = {"FMIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fmin_nan] = {"FMIN.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmin] = {"FABSMIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmin_nan] = {"FABSMIN.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fmax] = {"FMAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fmax_nan] = {"FMAX.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmax] = {"FABSMAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_fabsmax_nan] = {"FABSMAX.nan", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_imin] = {"MIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_imax] = {"MAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umin] = {"MIN", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umax] = {"MAX", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iavg] = {"AVG.rtz", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uavg] = {"AVG.rtz", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_iravg] = {"AVG.round", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uravg] = {"AVG.round", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_fmov] = {"FMOV", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_fmov_rtz] = {"FMOV.rtz", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_fmov_rtn] = {"FMOV.rtn", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_fmov_rtp] = {"FMOV.rtp", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_froundaway] = {"FROUNDAWAY", UNITS_ADD},
[midgard_alu_op_froundeven] = {"FROUNDEVEN", UNITS_ADD},
[midgard_alu_op_ftrunc] = {"FTRUNC", UNITS_ADD},
[midgard_alu_op_ffloor] = {"FFLOOR", UNITS_ADD},
[midgard_alu_op_fceil] = {"FCEIL", UNITS_ADD},
[midgard_alu_op_fmov] = {"FMOV", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_fmov_rtz] = {"FMOV.rtz", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_fmov_rtn] = {"FMOV.rtn", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_fmov_rtp] = {"FMOV.rtp", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_froundaway] = {"FROUNDAWAY", UNITS_ADD},
[midgard_alu_op_froundeven] = {"FROUNDEVEN", UNITS_ADD},
[midgard_alu_op_ftrunc] = {"FTRUNC", UNITS_ADD},
[midgard_alu_op_ffloor] = {"FFLOOR", UNITS_ADD},
[midgard_alu_op_fceil] = {"FCEIL", UNITS_ADD},
/* Multiplies the X/Y components of the first arg and adds the second
* arg. Like other LUTs, it must be scalarized. */
[midgard_alu_op_ffma] = {"FMA", UNIT_VLUT},
[midgard_alu_op_ffma_rtz] = {"FMA.rtz", UNIT_VLUT},
[midgard_alu_op_ffma_rtn] = {"FMA.rtn", UNIT_VLUT},
[midgard_alu_op_ffma_rtp] = {"FMA.rtp", UNIT_VLUT},
/* Multiplies the X/Y components of the first arg and adds the second
* arg. Like other LUTs, it must be scalarized. */
[midgard_alu_op_ffma] = {"FMA", UNIT_VLUT},
[midgard_alu_op_ffma_rtz] = {"FMA.rtz", UNIT_VLUT},
[midgard_alu_op_ffma_rtn] = {"FMA.rtn", UNIT_VLUT},
[midgard_alu_op_ffma_rtp] = {"FMA.rtp", UNIT_VLUT},
/* Though they output a scalar, they need to run on a vector unit
* since they process vectors */
[midgard_alu_op_fdot3] = {"FDOT3", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
[midgard_alu_op_fdot3r] = {"FDOT3R", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
[midgard_alu_op_fdot4] = {"FDOT4", UNIT_VMUL | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
/* Though they output a scalar, they need to run on a vector unit
* since they process vectors */
[midgard_alu_op_fdot3] = {"FDOT3", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
[midgard_alu_op_fdot3r] = {"FDOT3R", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
[midgard_alu_op_fdot4] = {"FDOT4", UNIT_VMUL | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
/* Incredibly, iadd can run on vmul, etc */
[midgard_alu_op_iadd] = {"ADD", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ishladd] = {"ADD", UNITS_MUL},
[midgard_alu_op_iaddsat] = {"ADDSAT", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uaddsat] = {"ADDSAT", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uabsdiff] = {"ABSDIFF", UNITS_ADD},
[midgard_alu_op_iabsdiff] = {"ABSDIFF", UNITS_ADD},
[midgard_alu_op_ichoose] = {"CHOOSE", UNITS_ADD},
[midgard_alu_op_isub] = {"SUB", UNITS_MOST},
[midgard_alu_op_ishlsub] = {"SUB", UNITS_MUL},
[midgard_alu_op_isubsat] = {"SUBSAT", UNITS_ADD},
[midgard_alu_op_usubsat] = {"SUBSAT", UNITS_ADD},
[midgard_alu_op_imul] = {"MUL", UNITS_MUL | OP_COMMUTES},
[midgard_alu_op_iwmul] = {"WMUL.s", UNIT_VMUL | OP_COMMUTES},
[midgard_alu_op_uwmul] = {"WMUL.u", UNIT_VMUL | OP_COMMUTES},
[midgard_alu_op_iuwmul] = {"WMUL.su", UNIT_VMUL | OP_COMMUTES},
[midgard_alu_op_imov] = {"MOV", UNITS_ALL | QUIRK_FLIPPED_R24},
/* Incredibly, iadd can run on vmul, etc */
[midgard_alu_op_iadd] = {"ADD", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ishladd] = {"ADD", UNITS_MUL},
[midgard_alu_op_iaddsat] = {"ADDSAT", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uaddsat] = {"ADDSAT", UNITS_ADD | OP_COMMUTES},
[midgard_alu_op_uabsdiff] = {"ABSDIFF", UNITS_ADD},
[midgard_alu_op_iabsdiff] = {"ABSDIFF", UNITS_ADD},
[midgard_alu_op_ichoose] = {"CHOOSE", UNITS_ADD},
[midgard_alu_op_isub] = {"SUB", UNITS_MOST},
[midgard_alu_op_ishlsub] = {"SUB", UNITS_MUL},
[midgard_alu_op_isubsat] = {"SUBSAT", UNITS_ADD},
[midgard_alu_op_usubsat] = {"SUBSAT", UNITS_ADD},
[midgard_alu_op_imul] = {"MUL", UNITS_MUL | OP_COMMUTES},
[midgard_alu_op_iwmul] = {"WMUL.s", UNIT_VMUL | OP_COMMUTES},
[midgard_alu_op_uwmul] = {"WMUL.u", UNIT_VMUL | OP_COMMUTES},
[midgard_alu_op_iuwmul] = {"WMUL.su", UNIT_VMUL | OP_COMMUTES},
[midgard_alu_op_imov] = {"MOV", UNITS_ALL | QUIRK_FLIPPED_R24},
/* For vector comparisons, use ball etc */
[midgard_alu_op_feq] = {"FCMP.eq", UNITS_MOST | OP_TYPE_CONVERT | OP_COMMUTES},
[midgard_alu_op_fne] = {"FCMP.ne", UNITS_MOST | OP_TYPE_CONVERT | OP_COMMUTES},
[midgard_alu_op_fle] = {"FCMP.le", UNITS_MOST | OP_TYPE_CONVERT},
[midgard_alu_op_flt] = {"FCMP.lt", UNITS_MOST | OP_TYPE_CONVERT},
[midgard_alu_op_ieq] = {"CMP.eq", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ine] = {"CMP.ne", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ilt] = {"CMP.lt", UNITS_MOST},
[midgard_alu_op_ile] = {"CMP.le", UNITS_MOST},
[midgard_alu_op_ult] = {"CMP.lt", UNITS_MOST},
[midgard_alu_op_ule] = {"CMP.le", UNITS_MOST},
/* For vector comparisons, use ball etc */
[midgard_alu_op_feq] = {"FCMP.eq", UNITS_MOST | OP_TYPE_CONVERT | OP_COMMUTES},
[midgard_alu_op_fne] = {"FCMP.ne", UNITS_MOST | OP_TYPE_CONVERT | OP_COMMUTES},
[midgard_alu_op_fle] = {"FCMP.le", UNITS_MOST | OP_TYPE_CONVERT},
[midgard_alu_op_flt] = {"FCMP.lt", UNITS_MOST | OP_TYPE_CONVERT},
[midgard_alu_op_ieq] = {"CMP.eq", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ine] = {"CMP.ne", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ilt] = {"CMP.lt", UNITS_MOST},
[midgard_alu_op_ile] = {"CMP.le", UNITS_MOST},
[midgard_alu_op_ult] = {"CMP.lt", UNITS_MOST},
[midgard_alu_op_ule] = {"CMP.le", UNITS_MOST},
/* CSEL (MUX) runs in the second pipeline stage, sourcing its selector
* the previous scalar or vector stage as indicated in the opcode. It
* muxes individual bits based on the selector, implementing both
* bit_select and bcsel (the latter because CMP returns 0/~0 booleans).
*
* It is legal to schedule (F)CSEL.vector to the scalar unit, but it
* isn't usually useful. Our scheduler does not handle that case, so
* don't try to and fall over.
*/
[midgard_alu_op_icsel] = {"CSEL.scalar", UNIT_VADD | UNIT_SMUL},
[midgard_alu_op_icsel_v] = {"CSEL.vector", UNIT_VADD},
[midgard_alu_op_fcsel_v] = {"FCSEL.vector", UNIT_VADD},
[midgard_alu_op_fcsel] = {"FCSEL.scalar", UNIT_VADD | UNIT_SMUL},
/* CSEL (MUX) runs in the second pipeline stage, sourcing its selector
* the previous scalar or vector stage as indicated in the opcode. It
* muxes individual bits based on the selector, implementing both
* bit_select and bcsel (the latter because CMP returns 0/~0 booleans).
*
* It is legal to schedule (F)CSEL.vector to the scalar unit, but it
* isn't usually useful. Our scheduler does not handle that case, so
* don't try to and fall over.
*/
[midgard_alu_op_icsel] = {"CSEL.scalar", UNIT_VADD | UNIT_SMUL},
[midgard_alu_op_icsel_v] = {"CSEL.vector", UNIT_VADD},
[midgard_alu_op_fcsel_v] = {"FCSEL.vector", UNIT_VADD},
[midgard_alu_op_fcsel] = {"FCSEL.scalar", UNIT_VADD | UNIT_SMUL},
[midgard_alu_op_frcp] = {"FRCP", UNIT_VLUT},
[midgard_alu_op_frsqrt] = {"FRSQRT", UNIT_VLUT},
[midgard_alu_op_fsqrt] = {"FSQRT", UNIT_VLUT},
[midgard_alu_op_fpow_pt1] = {"FPOW_PT1", UNIT_VLUT},
[midgard_alu_op_fpown_pt1] = {"FPOWN_PT1", UNIT_VLUT},
[midgard_alu_op_fpowr_pt1] = {"FPOWR_PT1", UNIT_VLUT},
[midgard_alu_op_fexp2] = {"FEXP2", UNIT_VLUT},
[midgard_alu_op_flog2] = {"FLOG2", UNIT_VLUT},
[midgard_alu_op_frcp] = {"FRCP", UNIT_VLUT},
[midgard_alu_op_frsqrt] = {"FRSQRT", UNIT_VLUT},
[midgard_alu_op_fsqrt] = {"FSQRT", UNIT_VLUT},
[midgard_alu_op_fpow_pt1] = {"FPOW_PT1", UNIT_VLUT},
[midgard_alu_op_fpown_pt1] = {"FPOWN_PT1", UNIT_VLUT},
[midgard_alu_op_fpowr_pt1] = {"FPOWR_PT1", UNIT_VLUT},
[midgard_alu_op_fexp2] = {"FEXP2", UNIT_VLUT},
[midgard_alu_op_flog2] = {"FLOG2", UNIT_VLUT},
[midgard_alu_op_f2i_rte] = {"F2I", UNITS_ADD | OP_TYPE_CONVERT | MIDGARD_ROUNDS},
[midgard_alu_op_f2i_rtz] = {"F2I.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2i_rtn] = {"F2I.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2i_rtp] = {"F2I.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2u_rte] = {"F2U", UNITS_ADD | OP_TYPE_CONVERT | MIDGARD_ROUNDS},
[midgard_alu_op_f2u_rtz] = {"F2U.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2u_rtn] = {"F2U.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2u_rtp] = {"F2U.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rte] = {"I2F", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rtz] = {"I2F.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rtn] = {"I2F.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rtp] = {"I2F.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rte] = {"U2F", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rtz] = {"U2F.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rtn] = {"U2F.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rtp] = {"U2F.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2i_rte] = {"F2I", UNITS_ADD | OP_TYPE_CONVERT | MIDGARD_ROUNDS},
[midgard_alu_op_f2i_rtz] = {"F2I.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2i_rtn] = {"F2I.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2i_rtp] = {"F2I.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2u_rte] = {"F2U", UNITS_ADD | OP_TYPE_CONVERT | MIDGARD_ROUNDS},
[midgard_alu_op_f2u_rtz] = {"F2U.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2u_rtn] = {"F2U.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_f2u_rtp] = {"F2U.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rte] = {"I2F", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rtz] = {"I2F.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rtn] = {"I2F.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_i2f_rtp] = {"I2F.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rte] = {"U2F", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rtz] = {"U2F.rtz", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rtn] = {"U2F.rtn", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_u2f_rtp] = {"U2F.rtp", UNITS_ADD | OP_TYPE_CONVERT},
[midgard_alu_op_fsinpi] = {"FSINPI", UNIT_VLUT},
[midgard_alu_op_fcospi] = {"FCOSPI", UNIT_VLUT},
[midgard_alu_op_fsinpi] = {"FSINPI", UNIT_VLUT},
[midgard_alu_op_fcospi] = {"FCOSPI", UNIT_VLUT},
[midgard_alu_op_iand] = {"AND", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iandnot] = {"ANDNOT", UNITS_MOST},
[midgard_alu_op_iand] = {"AND", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iandnot] = {"ANDNOT", UNITS_MOST},
[midgard_alu_op_ior] = {"OR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iornot] = {"ORNOT", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_inor] = {"NOR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ixor] = {"XOR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_inxor] = {"NXOR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iclz] = {"CLZ", UNITS_ADD},
[midgard_alu_op_ipopcnt] = {"POPCNT", UNIT_VADD},
[midgard_alu_op_inand] = {"NAND", UNITS_MOST},
[midgard_alu_op_ishl] = {"SHL", UNITS_ADD},
[midgard_alu_op_ishlsat] = {"SHL.sat", UNITS_ADD},
[midgard_alu_op_ushlsat] = {"SHL.sat", UNITS_ADD},
[midgard_alu_op_iasr] = {"ASR", UNITS_ADD},
[midgard_alu_op_ilsr] = {"LSR", UNITS_ADD},
[midgard_alu_op_ior] = {"OR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iornot] = {"ORNOT", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_inor] = {"NOR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ixor] = {"XOR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_inxor] = {"NXOR", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_iclz] = {"CLZ", UNITS_ADD},
[midgard_alu_op_ipopcnt] = {"POPCNT", UNIT_VADD},
[midgard_alu_op_inand] = {"NAND", UNITS_MOST},
[midgard_alu_op_ishl] = {"SHL", UNITS_ADD},
[midgard_alu_op_ishlsat] = {"SHL.sat", UNITS_ADD},
[midgard_alu_op_ushlsat] = {"SHL.sat", UNITS_ADD},
[midgard_alu_op_iasr] = {"ASR", UNITS_ADD},
[midgard_alu_op_ilsr] = {"LSR", UNITS_ADD},
[midgard_alu_op_fball_eq] = {"FCMP.all.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fball_neq] = {"FCMP.all.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fball_lt] = {"FCMP.all.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fball_lte] = {"FCMP.all.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fball_eq] = {"FCMP.all.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fball_neq] = {"FCMP.all.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fball_lt] = {"FCMP.all.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fball_lte] = {"FCMP.all.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_eq] = {"FCMP.any.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_neq] = {"FCMP.any.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_lt] = {"FCMP.any.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_lte] = {"FCMP.any.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_eq] = {"FCMP.any.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_neq] = {"FCMP.any.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_lt] = {"FCMP.any.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_fbany_lte] = {"FCMP.any.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES | OP_TYPE_CONVERT},
[midgard_alu_op_iball_eq] = {"CMP.all.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_iball_neq] = {"CMP.all.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_iball_lt] = {"CMP.all.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_iball_lte] = {"CMP.all.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_uball_lt] = {"CMP.all.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_uball_lte] = {"CMP.all.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_iball_eq] = {"CMP.all.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_iball_neq] = {"CMP.all.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_iball_lt] = {"CMP.all.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_iball_lte] = {"CMP.all.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_uball_lt] = {"CMP.all.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_uball_lte] = {"CMP.all.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_eq] = {"CMP.any.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_neq] = {"CMP.any.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_lt] = {"CMP.any.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_lte] = {"CMP.any.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ubany_lt] = {"CMP.any.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ubany_lte] = {"CMP.any.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_eq] = {"CMP.any.eq", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_neq] = {"CMP.any.ne", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_lt] = {"CMP.any.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ibany_lte] = {"CMP.any.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ubany_lt] = {"CMP.any.lt", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_ubany_lte] = {"CMP.any.le", UNITS_VECTOR | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
[midgard_alu_op_fatan2_pt1] = {"FATAN2_PT1", UNIT_VLUT},
[midgard_alu_op_fatan2_pt2] = {"FATAN2_PT2", UNIT_VLUT},
[midgard_alu_op_fatan2_pt1] = {"FATAN2_PT1", UNIT_VLUT},
[midgard_alu_op_fatan2_pt2] = {"FATAN2_PT2", UNIT_VLUT},
/* Haven't seen in a while */
[midgard_alu_op_freduce] = {"FREDUCE", 0},
/* Haven't seen in a while */
[midgard_alu_op_freduce] = {"FREDUCE", 0},
};
/* Define shorthands */
@ -212,173 +215,173 @@ struct mir_op_props alu_opcode_props[256] = {
#define M64 midgard_reg_mode_64
struct mir_ldst_op_props load_store_opcode_props[256] = {
[midgard_op_unpack_colour_f32] = {"UNPACK.f32", M32},
[midgard_op_unpack_colour_f16] = {"UNPACK.f16", M32},
[midgard_op_unpack_colour_u32] = {"UNPACK.u32", M32},
[midgard_op_unpack_colour_s32] = {"UNPACK.s32", M32},
[midgard_op_pack_colour_f32] = {"PACK.f32", M32},
[midgard_op_pack_colour_f16] = {"PACK.f16", M32},
[midgard_op_pack_colour_u32] = {"PACK.u32", M32},
[midgard_op_pack_colour_s32] = {"PACK.s32", M32},
[midgard_op_lea] = {"LEA", M32 | LDST_ADDRESS },
[midgard_op_lea_image] = {"LEA_IMAGE", M32 | LDST_ATTRIB },
[midgard_op_ld_cubemap_coords] = {"CUBEMAP", M32},
[midgard_op_ldst_mov] = {"LDST_MOV", M32},
[midgard_op_ldst_perspective_div_y] = {"LDST_PERSPECTIVE_DIV_Y", M32},
[midgard_op_ldst_perspective_div_z] = {"LDST_PERSPECTIVE_DIV_Z", M32},
[midgard_op_ldst_perspective_div_w] = {"LDST_PERSPECTIVE_DIV_W", M32},
[midgard_op_unpack_colour_f32] = {"UNPACK.f32", M32},
[midgard_op_unpack_colour_f16] = {"UNPACK.f16", M32},
[midgard_op_unpack_colour_u32] = {"UNPACK.u32", M32},
[midgard_op_unpack_colour_s32] = {"UNPACK.s32", M32},
[midgard_op_pack_colour_f32] = {"PACK.f32", M32},
[midgard_op_pack_colour_f16] = {"PACK.f16", M32},
[midgard_op_pack_colour_u32] = {"PACK.u32", M32},
[midgard_op_pack_colour_s32] = {"PACK.s32", M32},
[midgard_op_lea] = {"LEA", M32 | LDST_ADDRESS },
[midgard_op_lea_image] = {"LEA_IMAGE", M32 | LDST_ATTRIB },
[midgard_op_ld_cubemap_coords] = {"CUBEMAP", M32},
[midgard_op_ldst_mov] = {"LDST_MOV", M32},
[midgard_op_ldst_perspective_div_y] = {"LDST_PERSPECTIVE_DIV_Y", M32},
[midgard_op_ldst_perspective_div_z] = {"LDST_PERSPECTIVE_DIV_Z", M32},
[midgard_op_ldst_perspective_div_w] = {"LDST_PERSPECTIVE_DIV_W", M32},
[midgard_op_atomic_add] = {"AADD.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and] = {"AAND.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or] = {"AOR.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor] = {"AXOR.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin] = {"AMIN.s32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin] = {"AMIN.u32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax] = {"AMAX.s32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax] = {"AMAX.u32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg] = {"XCHG.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg] = {"CMPXCHG.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_add] = {"AADD.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and] = {"AAND.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or] = {"AOR.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor] = {"AXOR.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin] = {"AMIN.s32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin] = {"AMIN.u32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax] = {"AMAX.s32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax] = {"AMAX.u32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg] = {"XCHG.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg] = {"CMPXCHG.32", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg64] = {"CMPXCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg64] = {"CMPXCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_add_be] = {"AADD.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and_be] = {"AAND.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or_be] = {"AOR.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor_be] = {"AXOR.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin_be] = {"AMIN.s32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin_be] = {"AMIN.u32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax_be] = {"AMAX.s32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax_be] = {"AMAX.u32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg_be] = {"XCHG.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg_be] = {"CMPXCHG.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_add_be] = {"AADD.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and_be] = {"AAND.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or_be] = {"AOR.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor_be] = {"AXOR.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin_be] = {"AMIN.s32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin_be] = {"AMIN.u32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax_be] = {"AMAX.s32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax_be] = {"AMAX.u32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg_be] = {"XCHG.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg_be] = {"CMPXCHG.32.be", M32 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_add64] = {"AADD.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and64] = {"AAND.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or64] = {"AOR.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor64] = {"AXOR.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin64] = {"AMIN.s64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin64] = {"AMIN.u64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax64] = {"AMAX.s64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax64] = {"AMAX.u64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg64] = {"XCHG.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg64] = {"CMPXCHG.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_add64] = {"AADD.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_and64] = {"AAND.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_or64] = {"AOR.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xor64] = {"AXOR.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imin64] = {"AMIN.s64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umin64] = {"AMIN.u64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_imax64] = {"AMAX.s64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_umax64] = {"AMAX.u64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_xchg64] = {"XCHG.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_atomic_cmpxchg64] = {"CMPXCHG.64.be", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[midgard_op_ld_u8] = {"LD.u8", M32 | LDST_ADDRESS},
[midgard_op_ld_i8] = {"LD.s8", M32 | LDST_ADDRESS},
[midgard_op_ld_u16] = {"LD.u16", M32 | LDST_ADDRESS},
[midgard_op_ld_i16] = {"LD.s16", M32 | LDST_ADDRESS},
[midgard_op_ld_u16_be] = {"LD.u16.be", M32 | LDST_ADDRESS},
[midgard_op_ld_i16_be] = {"LD.s16.be", M32 | LDST_ADDRESS},
[midgard_op_ld_32] = {"LD.32", M32 | LDST_ADDRESS},
[midgard_op_ld_32_bswap2] = {"LD.32.bswap2", M32 | LDST_ADDRESS},
[midgard_op_ld_32_bswap4] = {"LD.32.bswap4", M32 | LDST_ADDRESS},
[midgard_op_ld_64] = {"LD.64", M32 | LDST_ADDRESS},
[midgard_op_ld_64_bswap2] = {"LD.64.bswap2", M32 | LDST_ADDRESS},
[midgard_op_ld_64_bswap4] = {"LD.64.bswap4", M32 | LDST_ADDRESS},
[midgard_op_ld_64_bswap8] = {"LD.64.bswap8", M32 | LDST_ADDRESS},
[midgard_op_ld_128] = {"LD.128", M32 | LDST_ADDRESS},
[midgard_op_ld_128_bswap2] = {"LD.128.bswap2", M32 | LDST_ADDRESS},
[midgard_op_ld_128_bswap4] = {"LD.128.bswap4", M32 | LDST_ADDRESS},
[midgard_op_ld_128_bswap8] = {"LD.128.bswap8", M32 | LDST_ADDRESS},
[midgard_op_ld_u8] = {"LD.u8", M32 | LDST_ADDRESS},
[midgard_op_ld_i8] = {"LD.s8", M32 | LDST_ADDRESS},
[midgard_op_ld_u16] = {"LD.u16", M32 | LDST_ADDRESS},
[midgard_op_ld_i16] = {"LD.s16", M32 | LDST_ADDRESS},
[midgard_op_ld_u16_be] = {"LD.u16.be", M32 | LDST_ADDRESS},
[midgard_op_ld_i16_be] = {"LD.s16.be", M32 | LDST_ADDRESS},
[midgard_op_ld_32] = {"LD.32", M32 | LDST_ADDRESS},
[midgard_op_ld_32_bswap2] = {"LD.32.bswap2", M32 | LDST_ADDRESS},
[midgard_op_ld_32_bswap4] = {"LD.32.bswap4", M32 | LDST_ADDRESS},
[midgard_op_ld_64] = {"LD.64", M32 | LDST_ADDRESS},
[midgard_op_ld_64_bswap2] = {"LD.64.bswap2", M32 | LDST_ADDRESS},
[midgard_op_ld_64_bswap4] = {"LD.64.bswap4", M32 | LDST_ADDRESS},
[midgard_op_ld_64_bswap8] = {"LD.64.bswap8", M32 | LDST_ADDRESS},
[midgard_op_ld_128] = {"LD.128", M32 | LDST_ADDRESS},
[midgard_op_ld_128_bswap2] = {"LD.128.bswap2", M32 | LDST_ADDRESS},
[midgard_op_ld_128_bswap4] = {"LD.128.bswap4", M32 | LDST_ADDRESS},
[midgard_op_ld_128_bswap8] = {"LD.128.bswap8", M32 | LDST_ADDRESS},
[midgard_op_ld_attr_32] = {"LD_ATTR.f32", M32 | LDST_ATTRIB},
[midgard_op_ld_attr_32i] = {"LD_ATTR.s32", M32 | LDST_ATTRIB},
[midgard_op_ld_attr_32u] = {"LD_ATTR.u32", M32 | LDST_ATTRIB},
[midgard_op_ld_attr_16] = {"LD_ATTR.f16", M32 | LDST_ATTRIB},
[midgard_op_ld_attr_32] = {"LD_ATTR.f32", M32 | LDST_ATTRIB},
[midgard_op_ld_attr_32i] = {"LD_ATTR.s32", M32 | LDST_ATTRIB},
[midgard_op_ld_attr_32u] = {"LD_ATTR.u32", M32 | LDST_ATTRIB},
[midgard_op_ld_attr_16] = {"LD_ATTR.f16", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_32] = {"LD_VARY.f32", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_16] = {"LD_VARY.f16", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_32i] = {"LD_VARY.s32", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_32u] = {"LD_VARY.u32", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_32] = {"LD_VARY.f32", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_16] = {"LD_VARY.f16", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_32i] = {"LD_VARY.s32", M32 | LDST_ATTRIB},
[midgard_op_ld_vary_32u] = {"LD_VARY.u32", M32 | LDST_ATTRIB},
[midgard_op_ld_special_32f] = {"LD_SPECIAL.f32", M32 | LDST_SPECIAL_MASK},
[midgard_op_ld_special_16f] = {"LD_SPECIAL.f16", M16 | LDST_SPECIAL_MASK},
[midgard_op_ld_special_32u] = {"LD_SPECIAL.u32", M32},
[midgard_op_ld_special_32i] = {"LD_SPECIAL.s32", M32},
[midgard_op_ld_special_32f] = {"LD_SPECIAL.f32", M32 | LDST_SPECIAL_MASK},
[midgard_op_ld_special_16f] = {"LD_SPECIAL.f16", M16 | LDST_SPECIAL_MASK},
[midgard_op_ld_special_32u] = {"LD_SPECIAL.u32", M32},
[midgard_op_ld_special_32i] = {"LD_SPECIAL.s32", M32},
[midgard_op_ld_tilebuffer_32f] = {"LD_TILEBUFFER.f32", M32},
[midgard_op_ld_tilebuffer_16f] = {"LD_TILEBUFFER.f16", M16},
[midgard_op_ld_tilebuffer_raw] = {"LD_TILEBUFFER.raw", M32},
[midgard_op_ld_tilebuffer_32f] = {"LD_TILEBUFFER.f32", M32},
[midgard_op_ld_tilebuffer_16f] = {"LD_TILEBUFFER.f16", M16},
[midgard_op_ld_tilebuffer_raw] = {"LD_TILEBUFFER.raw", M32},
[midgard_op_ld_ubo_u8] = {"LD_UBO.u8", M32},
[midgard_op_ld_ubo_i8] = {"LD_UBO.s8", M32},
[midgard_op_ld_ubo_u16] = {"LD_UBO.u16", M16},
[midgard_op_ld_ubo_i16] = {"LD_UBO.s16", M16},
[midgard_op_ld_ubo_u16_be] = {"LD_UBO.u16.be", M16},
[midgard_op_ld_ubo_i16_be] = {"LD_UBO.s16.be", M16},
[midgard_op_ld_ubo_32] = {"LD_UBO.32", M32},
[midgard_op_ld_ubo_32_bswap2] = {"LD_UBO.32.bswap2", M32},
[midgard_op_ld_ubo_32_bswap4] = {"LD_UBO.32.bswap4", M32},
[midgard_op_ld_ubo_64] = {"LD_UBO.64", M32},
[midgard_op_ld_ubo_64_bswap2] = {"LD_UBO.64.bswap2", M32},
[midgard_op_ld_ubo_64_bswap4] = {"LD_UBO.64.bswap4", M32},
[midgard_op_ld_ubo_64_bswap8] = {"LD_UBO.64.bswap8", M32},
[midgard_op_ld_ubo_128] = {"LD_UBO.128", M32},
[midgard_op_ld_ubo_128_bswap2] = {"LD_UBO.128.bswap2", M32},
[midgard_op_ld_ubo_128_bswap4] = {"LD_UBO.128.bswap4", M32},
[midgard_op_ld_ubo_128_bswap8] = {"LD_UBO.128.bswap8", M32},
[midgard_op_ld_ubo_u8] = {"LD_UBO.u8", M32},
[midgard_op_ld_ubo_i8] = {"LD_UBO.s8", M32},
[midgard_op_ld_ubo_u16] = {"LD_UBO.u16", M16},
[midgard_op_ld_ubo_i16] = {"LD_UBO.s16", M16},
[midgard_op_ld_ubo_u16_be] = {"LD_UBO.u16.be", M16},
[midgard_op_ld_ubo_i16_be] = {"LD_UBO.s16.be", M16},
[midgard_op_ld_ubo_32] = {"LD_UBO.32", M32},
[midgard_op_ld_ubo_32_bswap2] = {"LD_UBO.32.bswap2", M32},
[midgard_op_ld_ubo_32_bswap4] = {"LD_UBO.32.bswap4", M32},
[midgard_op_ld_ubo_64] = {"LD_UBO.64", M32},
[midgard_op_ld_ubo_64_bswap2] = {"LD_UBO.64.bswap2", M32},
[midgard_op_ld_ubo_64_bswap4] = {"LD_UBO.64.bswap4", M32},
[midgard_op_ld_ubo_64_bswap8] = {"LD_UBO.64.bswap8", M32},
[midgard_op_ld_ubo_128] = {"LD_UBO.128", M32},
[midgard_op_ld_ubo_128_bswap2] = {"LD_UBO.128.bswap2", M32},
[midgard_op_ld_ubo_128_bswap4] = {"LD_UBO.128.bswap4", M32},
[midgard_op_ld_ubo_128_bswap8] = {"LD_UBO.128.bswap8", M32},
[midgard_op_ld_image_32f] = {"LD_IMAGE.f32", M32 | LDST_ATTRIB},
[midgard_op_ld_image_16f] = {"LD_IMAGE.f16", M16 | LDST_ATTRIB},
[midgard_op_ld_image_32i] = {"LD_IMAGE.s32", M32 | LDST_ATTRIB},
[midgard_op_ld_image_32u] = {"LD_IMAGE.u32", M32 | LDST_ATTRIB},
[midgard_op_ld_image_32f] = {"LD_IMAGE.f32", M32 | LDST_ATTRIB},
[midgard_op_ld_image_16f] = {"LD_IMAGE.f16", M16 | LDST_ATTRIB},
[midgard_op_ld_image_32i] = {"LD_IMAGE.s32", M32 | LDST_ATTRIB},
[midgard_op_ld_image_32u] = {"LD_IMAGE.u32", M32 | LDST_ATTRIB},
[midgard_op_st_u8] = {"ST.u8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_i8] = {"ST.s8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_u16] = {"ST.u16", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_i16] = {"ST.s16", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_u16_be] = {"ST.u16.be", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_i16_be] = {"ST.s16.be", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_32] = {"ST.32", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_32_bswap2] = {"ST.32.bswap2", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_32_bswap4] = {"ST.32.bswap4", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64] = {"ST.64", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64_bswap2] = {"ST.64.bswap2", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64_bswap4] = {"ST.64.bswap4", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64_bswap8] = {"ST.64.bswap8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128] = {"ST.128", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128_bswap2] = {"ST.128.bswap2", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128_bswap4] = {"ST.128.bswap4", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128_bswap8] = {"ST.128.bswap8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_u8] = {"ST.u8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_i8] = {"ST.s8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_u16] = {"ST.u16", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_i16] = {"ST.s16", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_u16_be] = {"ST.u16.be", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_i16_be] = {"ST.s16.be", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_32] = {"ST.32", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_32_bswap2] = {"ST.32.bswap2", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_32_bswap4] = {"ST.32.bswap4", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64] = {"ST.64", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64_bswap2] = {"ST.64.bswap2", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64_bswap4] = {"ST.64.bswap4", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_64_bswap8] = {"ST.64.bswap8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128] = {"ST.128", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128_bswap2] = {"ST.128.bswap2", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128_bswap4] = {"ST.128.bswap4", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_128_bswap8] = {"ST.128.bswap8", M32 | LDST_STORE | LDST_ADDRESS},
[midgard_op_st_vary_32] = {"ST_VARY.f32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_vary_32i] = {"ST_VARY.s32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_vary_32u] = {"ST_VARY.u32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_vary_16] = {"ST_VARY.f16", M16 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_vary_32] = {"ST_VARY.f32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_vary_32i] = {"ST_VARY.s32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_vary_32u] = {"ST_VARY.u32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_vary_16] = {"ST_VARY.f16", M16 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_32f] = {"ST_IMAGE.f32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_16f] = {"ST_IMAGE.f16", M16 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_32i] = {"ST_IMAGE.u32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_32u] = {"ST_IMAGE.s32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_32f] = {"ST_IMAGE.f32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_16f] = {"ST_IMAGE.f16", M16 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_32i] = {"ST_IMAGE.u32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_image_32u] = {"ST_IMAGE.s32", M32 | LDST_STORE | LDST_ATTRIB},
[midgard_op_st_special_32f] = {"ST_SPECIAL.f32", M32},
[midgard_op_st_special_16f] = {"ST_SPECIAL.f16", M16},
[midgard_op_st_special_32u] = {"ST_SPECIAL.u32", M32},
[midgard_op_st_special_32i] = {"ST_SPECIAL.s32", M32},
[midgard_op_st_special_32f] = {"ST_SPECIAL.f32", M32},
[midgard_op_st_special_16f] = {"ST_SPECIAL.f16", M16},
[midgard_op_st_special_32u] = {"ST_SPECIAL.u32", M32},
[midgard_op_st_special_32i] = {"ST_SPECIAL.s32", M32},
[midgard_op_st_tilebuffer_32f] = {"ST_TILEBUFFER.f32", M32},
[midgard_op_st_tilebuffer_16f] = {"ST_TILEBUFFER.f16", M16},
[midgard_op_st_tilebuffer_raw] = {"ST_TILEBUFFER.raw", M32},
[midgard_op_st_tilebuffer_32f] = {"ST_TILEBUFFER.f32", M32},
[midgard_op_st_tilebuffer_16f] = {"ST_TILEBUFFER.f16", M16},
[midgard_op_st_tilebuffer_raw] = {"ST_TILEBUFFER.raw", M32},
};
struct mir_tex_op_props tex_opcode_props[16] = {
[midgard_tex_op_normal] = {"TEX", M32},
[midgard_tex_op_gradient] = {"TEX_GRAD", M32},
[midgard_tex_op_fetch] = {"TEX_FETCH", M32},
[midgard_tex_op_grad_from_derivative] = {"DER_TO_GRAD", M32},
[midgard_tex_op_grad_from_coords] = {"COORDS_TO_GRAD", M32},
[midgard_tex_op_mov] = {"MOV", M32},
[midgard_tex_op_barrier] = {"BARRIER", M32},
[midgard_tex_op_derivative] = {"DERIVATIVE", M32}
[midgard_tex_op_normal] = {"TEX", M32},
[midgard_tex_op_gradient] = {"TEX_GRAD", M32},
[midgard_tex_op_fetch] = {"TEX_FETCH", M32},
[midgard_tex_op_grad_from_derivative] = {"DER_TO_GRAD", M32},
[midgard_tex_op_grad_from_coords] = {"COORDS_TO_GRAD", M32},
[midgard_tex_op_mov] = {"MOV", M32},
[midgard_tex_op_barrier] = {"BARRIER", M32},
[midgard_tex_op_derivative] = {"DERIVATIVE", M32}
};
#undef M8
@ -387,20 +390,21 @@ struct mir_tex_op_props tex_opcode_props[16] = {
#undef M64
struct mir_tag_props midgard_tag_props[16] = {
[TAG_INVALID] = {"invalid", 0},
[TAG_BREAK] = {"break", 0},
[TAG_TEXTURE_4_VTX] = {"tex/vt", 1},
[TAG_TEXTURE_4] = {"tex", 1},
[TAG_TEXTURE_4_BARRIER] = {"tex/bar", 1},
[TAG_LOAD_STORE_4] = {"ldst", 1},
[TAG_UNKNOWN_1] = {"unk1", 1},
[TAG_UNKNOWN_2] = {"unk2", 1},
[TAG_ALU_4] = {"alu/4", 1},
[TAG_ALU_8] = {"alu/8", 2},
[TAG_ALU_12] = {"alu/12", 3},
[TAG_ALU_16] = {"alu/16", 4},
[TAG_ALU_4_WRITEOUT] = {"aluw/4", 1},
[TAG_ALU_8_WRITEOUT] = {"aluw/8", 2},
[TAG_ALU_12_WRITEOUT] = {"aluw/12", 3},
[TAG_ALU_16_WRITEOUT] = {"aluw/16", 4}
[TAG_INVALID] = {"invalid", 0},
[TAG_BREAK] = {"break", 0},
[TAG_TEXTURE_4_VTX] = {"tex/vt", 1},
[TAG_TEXTURE_4] = {"tex", 1},
[TAG_TEXTURE_4_BARRIER] = {"tex/bar", 1},
[TAG_LOAD_STORE_4] = {"ldst", 1},
[TAG_UNKNOWN_1] = {"unk1", 1},
[TAG_UNKNOWN_2] = {"unk2", 1},
[TAG_ALU_4] = {"alu/4", 1},
[TAG_ALU_8] = {"alu/8", 2},
[TAG_ALU_12] = {"alu/12", 3},
[TAG_ALU_16] = {"alu/16", 4},
[TAG_ALU_4_WRITEOUT] = {"aluw/4", 1},
[TAG_ALU_8_WRITEOUT] = {"aluw/8", 2},
[TAG_ALU_12_WRITEOUT] = {"aluw/12", 3},
[TAG_ALU_16_WRITEOUT] = {"aluw/16", 4}
};
/* clang-format on */

6
src/panfrost/midgard/midgard_opt_perspective.c
View file

@ -118,15 +118,15 @@ midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block)
.mask = ins->mask,
.dest = to,
.dest_type = nir_type_float32,
.src = { frcp_from, ~0, ~0, ~0 },
.src_types = { nir_type_float32 },
.src = { frcp_from, ~0, ~0, ~0, },
.src_types = { nir_type_float32, },
.swizzle = SWIZZLE_IDENTITY_4,
.op = frcp_component == COMPONENT_W ?
midgard_op_ldst_perspective_div_w :
midgard_op_ldst_perspective_div_z,
.load_store = {
.bitsize_toggle = true,
}
},
};
mir_insert_instruction_before(ctx, ins, accel);

6
src/panfrost/midgard/midgard_ra.c
View file

@ -70,7 +70,7 @@ default_phys_reg(int reg, unsigned shift)
struct phys_reg r = {
.reg = reg,
.offset = 0,
.shift = shift
.shift = shift,
};
return r;
@ -93,7 +93,7 @@ index_to_reg(compiler_context *ctx, struct lcra_state *l, unsigned reg, unsigned
struct phys_reg r = {
.reg = l->solutions[reg] / 16,
.offset = l->solutions[reg] & 0xF,
.shift = shift
.shift = shift,
};
/* Report that we actually use this register, and return it */
@ -1180,7 +1180,7 @@ mir_demote_uniforms(compiler_context *ctx, unsigned new_cutoff)
.load_store = {
.index_reg = REGISTER_LDST_ZERO,
},
.constants.u32[0] = ctx->info->push.words[idx].offset
.constants.u32[0] = ctx->info->push.words[idx].offset,
};
midgard_pack_ubo_index_imm(&ld.load_store,

12
src/panfrost/midgard/midgard_schedule.c
View file

@ -824,7 +824,7 @@ mir_choose_bundle(
.tag = ~0,
.unit = ~0,
.destructive = false,
.exclude = ~0
.exclude = ~0,
};
midgard_instruction *chosen = mir_choose_instruction(instructions, liveness, worklist, count, &predicate);
@ -1045,7 +1045,7 @@ mir_schedule_texture(
struct midgard_predicate predicate = {
.tag = TAG_TEXTURE_4,
.destructive = true,
.exclude = ~0
.exclude = ~0,
};
midgard_instruction *ins =
@ -1059,7 +1059,7 @@ mir_schedule_texture(
(ins->op == midgard_tex_op_fetch) || is_vertex ?
TAG_TEXTURE_4_VTX : TAG_TEXTURE_4,
.instruction_count = 1,
.instructions = { ins }
.instructions = { ins },
};
return out;
@ -1075,7 +1075,7 @@ mir_schedule_ldst(
struct midgard_predicate predicate = {
.tag = TAG_LOAD_STORE_4,
.destructive = true,
.exclude = ~0
.exclude = ~0,
};
/* Try to pick two load/store ops. Second not gauranteed to exist */
@ -1091,7 +1091,7 @@ mir_schedule_ldst(
struct midgard_bundle out = {
.tag = TAG_LOAD_STORE_4,
.instruction_count = pair ? 2 : 1,
.instructions = { ins, pair }
.instructions = { ins, pair },
};
*num_ldst -= out.instruction_count;
@ -1188,7 +1188,7 @@ mir_schedule_alu(
.tag = TAG_ALU_4,
.destructive = true,
.exclude = ~0,
.constants = &bundle.constants
.constants = &bundle.constants,
};
midgard_instruction *vmul = NULL;

2
src/panfrost/midgard/mir_promote_uniforms.c
View file

@ -112,7 +112,7 @@ mir_pick_ubo(struct panfrost_ubo_push *push, struct mir_ubo_analysis *analysis,
for (unsigned offs = 0; offs < 4; ++offs) {
struct panfrost_ubo_word word = {
.ubo = ubo,
.offset = (vec4 * 16) + (offs * 4)
.offset = (vec4 * 16) + (offs * 4),
};
push->words[push->count++] = word;

16
src/panfrost/shared/pan_tiling.c
View file

@ -52,11 +52,13 @@
*
*/
/* Given the lower 4-bits of the Y coordinate, we would like to
/*
* Given the lower 4-bits of the Y coordinate, we would like to
* duplicate every bit over. So instead of 0b1010, we would like
* 0b11001100. The idea is that for the bits in the solely Y place, we
* get a Y place, and the bits in the XOR place *also* get a Y. */
* get a Y place, and the bits in the XOR place *also* get a Y.
*/
/* clang-format off */
const uint32_t bit_duplication[16] = {
0b00000000,
0b00000011,
@ -75,9 +77,12 @@ const uint32_t bit_duplication[16] = {
0b11111100,
0b11111111,
};
/* clang-format on */
/* Space the bits out of a 4-bit nibble */
/*
* Space the bits out of a 4-bit nibble
*/
/* clang-format off */
const unsigned space_4[16] = {
0b0000000,
0b0000001,
@ -96,6 +101,7 @@ const unsigned space_4[16] = {
0b1010100,
0b1010101
};
/* clang-format on */
/* The scheme uses 16x16 tiles */

2
src/panfrost/tools/panfrostdump.c
View file

@ -224,12 +224,14 @@ main(int argc, char *argv[])
return EXIT_FAILURE;
}
/* clang-format off */
const struct option longopts[] = {
{ "addr", no_argument, (int *) &print_addr, true },
{ "regs", no_argument, (int *) &print_reg, true },
{ "help", no_argument, NULL, 'h' },
{ NULL, 0, NULL, 0 }
};
/* clang-format on */
while ((c = getopt_long(argc, argv, "arh", longopts, NULL)) != -1) {
switch(c) {