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radeon/vcn: add Arcturus decode support

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different internal registers offset from previous HW

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Leo Liu 2019-06-20 09:00:27 -04:00 • committed by Marek Olšák
parent 7708540363
commit a439863918
1 changed files with 11 additions and 1 deletions
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12
src/gallium/drivers/radeon/radeon_vcn_dec.c
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@ -56,6 +56,11 @@
#define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2)
#define RDECODE_VCN2_ENGINE_CNTL (0x506 << 2)
#define RDECODE_VCN2_5_GPCOM_VCPU_CMD 0x3c
#define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40
#define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44
#define RDECODE_VCN2_5_ENGINE_CNTL 0x9b4
#define NUM_MPEG2_REFS 6
#define NUM_H264_REFS 17
#define NUM_VC1_REFS 5
@ -1597,7 +1602,12 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
}
si_vid_clear_buffer(context, &dec->sessionctx);
if (sctx->family >= CHIP_NAVI10) {
if (sctx->family == CHIP_ARCTURUS) {
dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
} else if (sctx->family >= CHIP_NAVI10) {
dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;