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aco: Always enable idxen for swizzled buffer access on GFX11.

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This helps pass the mesh shader I/O tests.
Swizzled buffer addressing seems to be broken on GFX11
when the idxen bit is 0.

No Fossil DB changes on Rembrandt (GFX10.3).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21930>
This commit is contained in:
Timur Kristóf 2023-02-18 13:45:22 +01:00 • committed by Marge Bot
parent 1f9e44c181
commit a42c57dc01
1 changed files with 8 additions and 4 deletions
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12
src/amd/compiler/aco_instruction_selection.cpp
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@ -7038,7 +7038,10 @@ visit_load_buffer(isel_context* ctx, nir_intrinsic_instr* intrin)
{
Builder bld(ctx->program, ctx->block);
bool idxen = !nir_src_is_const(intrin->src[3]) || nir_src_as_uint(intrin->src[3]);
/* Swizzled buffer addressing seems to be broken on GFX11 without the idxen bit. */
bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD;
bool idxen = (swizzled && ctx->program->gfx_level >= GFX11) ||
!nir_src_is_const(intrin->src[3]) || nir_src_as_uint(intrin->src[3]);
bool v_offset_zero = nir_src_is_const(intrin->src[1]) && !nir_src_as_uint(intrin->src[1]);
bool s_offset_zero = nir_src_is_const(intrin->src[2]) && !nir_src_as_uint(intrin->src[2]);
@ -7050,7 +7053,6 @@ visit_load_buffer(isel_context* ctx, nir_intrinsic_instr* intrin)
s_offset_zero ? Temp(0, s1) : bld.as_uniform(get_ssa_temp(ctx, intrin->src[2].ssa));
Temp idx = idxen ? as_vgpr(ctx, get_ssa_temp(ctx, intrin->src[3].ssa)) : Temp();
bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD;
bool glc = nir_intrinsic_access(intrin) & ACCESS_COHERENT;
bool slc = nir_intrinsic_access(intrin) & ACCESS_STREAM_CACHE_POLICY;
@ -7108,7 +7110,10 @@ visit_store_buffer(isel_context* ctx, nir_intrinsic_instr* intrin)
{
Builder bld(ctx->program, ctx->block);
bool idxen = !nir_src_is_const(intrin->src[4]) || nir_src_as_uint(intrin->src[4]);
/* Swizzled buffer addressing seems to be broken on GFX11 without the idxen bit. */
bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD;
bool idxen = (swizzled && ctx->program->gfx_level >= GFX11) ||
!nir_src_is_const(intrin->src[4]) || nir_src_as_uint(intrin->src[4]);
bool v_offset_zero = nir_src_is_const(intrin->src[2]) && !nir_src_as_uint(intrin->src[2]);
bool s_offset_zero = nir_src_is_const(intrin->src[3]) && !nir_src_as_uint(intrin->src[3]);
@ -7120,7 +7125,6 @@ visit_store_buffer(isel_context* ctx, nir_intrinsic_instr* intrin)
s_offset_zero ? Temp(0, s1) : bld.as_uniform(get_ssa_temp(ctx, intrin->src[3].ssa));
Temp idx = idxen ? as_vgpr(ctx, get_ssa_temp(ctx, intrin->src[4].ssa)) : Temp();
bool swizzled = nir_intrinsic_access(intrin) & ACCESS_IS_SWIZZLED_AMD;
bool glc = nir_intrinsic_access(intrin) & ACCESS_COHERENT;
bool slc = nir_intrinsic_access(intrin) & ACCESS_STREAM_CACHE_POLICY;