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amd/common: Cache intra-tile addresses for retile map.
However complicated DCC addressing is it is still based on tiles. If we have the intra-tile offsets + tile dimensions we can expand that to the full image ourselves. Behavior around ~1080p on a 2500U: old: 30-60 ms on every miss new: 5 ms initally (miss in the tile cache) <0.5 ms afterwards The most common case is that the tile cache only contains data for 2 tiles, which for Raven/Renoir/Navi14 will be 4 KiB each, so the size increase is fairly modest. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5865>
This commit is contained in:
Bas Nieuwenhuizen
Marge Bot
parent
f302ef3853
commit
a37aeb128d
1 changed files with 181 additions and 41 deletions
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@ -61,6 +61,7 @@ struct ac_addrlib {
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*/
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simple_mtx_t dcc_retile_map_lock;
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struct hash_table *dcc_retile_maps;
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struct hash_table *dcc_retile_tile_indices;
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};
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struct dcc_retile_map_key {
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@ -89,6 +90,156 @@ static void dcc_retile_map_free(struct hash_entry *entry)
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free(entry->data);
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}
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struct dcc_retile_tile_key {
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enum radeon_family family;
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unsigned bpp;
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unsigned swizzle_mode;
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bool rb_aligned;
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bool pipe_aligned;
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};
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struct dcc_retile_tile_data {
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unsigned tile_width_log2;
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unsigned tile_height_log2;
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uint16_t *data;
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};
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static uint32_t dcc_retile_tile_hash_key(const void *key)
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{
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return _mesa_hash_data(key, sizeof(struct dcc_retile_tile_key));
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}
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static bool dcc_retile_tile_keys_equal(const void *a, const void *b)
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{
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return memcmp(a, b, sizeof(struct dcc_retile_tile_key)) == 0;
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}
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static void dcc_retile_tile_free(struct hash_entry *entry)
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{
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free((void*)entry->key);
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free(((struct dcc_retile_tile_data*)entry->data)->data);
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free(entry->data);
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}
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/* Assumes dcc_retile_map_lock is taken. */
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static const struct dcc_retile_tile_data *
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ac_compute_dcc_retile_tile_indices(struct ac_addrlib *addrlib,
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const struct radeon_info *info,
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unsigned bpp, unsigned swizzle_mode,
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bool rb_aligned, bool pipe_aligned)
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{
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struct dcc_retile_tile_key key = (struct dcc_retile_tile_key) {
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.family = info->family,
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.bpp = bpp,
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.swizzle_mode = swizzle_mode,
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.rb_aligned = rb_aligned,
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.pipe_aligned = pipe_aligned
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};
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struct hash_entry *entry = _mesa_hash_table_search(addrlib->dcc_retile_tile_indices, &key);
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if (entry)
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return entry->data;
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ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
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ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
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din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
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dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
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din.dccKeyFlags.pipeAligned = pipe_aligned;
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din.dccKeyFlags.rbAligned = rb_aligned;
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din.resourceType = ADDR_RSRC_TEX_2D;
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din.swizzleMode = swizzle_mode;
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din.bpp = bpp;
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din.unalignedWidth = 1;
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din.unalignedHeight = 1;
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din.numSlices = 1;
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din.numFrags = 1;
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din.numMipLevels = 1;
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ADDR_E_RETURNCODE ret = Addr2ComputeDccInfo(addrlib->handle, &din, &dout);
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if (ret != ADDR_OK)
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return NULL;
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {0};
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addrin.size = sizeof(addrin);
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addrin.swizzleMode = swizzle_mode;
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addrin.resourceType = ADDR_RSRC_TEX_2D;
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addrin.bpp = bpp;
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addrin.numSlices = 1;
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addrin.numMipLevels = 1;
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addrin.numFrags = 1;
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addrin.pitch = dout.pitch;
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addrin.height = dout.height;
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addrin.compressBlkWidth = dout.compressBlkWidth;
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addrin.compressBlkHeight = dout.compressBlkHeight;
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addrin.compressBlkDepth = dout.compressBlkDepth;
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addrin.metaBlkWidth = dout.metaBlkWidth;
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addrin.metaBlkHeight = dout.metaBlkHeight;
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addrin.metaBlkDepth = dout.metaBlkDepth;
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addrin.dccKeyFlags.pipeAligned = pipe_aligned;
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addrin.dccKeyFlags.rbAligned = rb_aligned;
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unsigned w = dout.metaBlkWidth / dout.compressBlkWidth;
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unsigned h = dout.metaBlkHeight / dout.compressBlkHeight;
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uint16_t *indices = malloc(w * h * sizeof (uint16_t));
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if (!indices)
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return NULL;
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
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addrout.size = sizeof(addrout);
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for (unsigned y = 0; y < h; ++y) {
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addrin.y = y * dout.compressBlkHeight;
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for (unsigned x = 0; x < w; ++x) {
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addrin.x = x * dout.compressBlkWidth;
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addrout.addr = 0;
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if (Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout) != ADDR_OK) {
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free(indices);
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return NULL;
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}
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indices[y * w + x] = addrout.addr;
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}
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}
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struct dcc_retile_tile_data *data = calloc(1, sizeof(*data));
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if (!data) {
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free(indices);
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return NULL;
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}
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data->tile_width_log2 = util_logbase2(w);
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data->tile_height_log2 = util_logbase2(h);
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data->data = indices;
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struct dcc_retile_tile_key *heap_key = mem_dup(&key, sizeof(key));
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if (!heap_key) {
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free(data);
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free(indices);
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return NULL;
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}
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entry = _mesa_hash_table_insert(addrlib->dcc_retile_tile_indices, heap_key, data);
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if (!entry) {
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free(heap_key);
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free(data);
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free(indices);
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}
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return data;
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}
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static uint32_t ac_compute_retile_tile_addr(const struct dcc_retile_tile_data *tile,
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unsigned stride, unsigned x, unsigned y)
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{
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unsigned x_mask = (1u << tile->tile_width_log2) - 1;
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unsigned y_mask = (1u << tile->tile_height_log2) - 1;
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unsigned tile_size_log2 = tile->tile_width_log2 + tile->tile_height_log2;
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unsigned base = ((y >> tile->tile_height_log2) * stride + (x >> tile->tile_width_log2)) << tile_size_log2;
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unsigned offset_in_tile = tile->data[((y & y_mask) << tile->tile_width_log2) + (x & x_mask)];
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return base + offset_in_tile;
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}
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static uint32_t *ac_compute_dcc_retile_map(struct ac_addrlib *addrlib,
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const struct radeon_info *info,
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unsigned retile_width, unsigned retile_height,
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@ -120,11 +271,17 @@ static uint32_t *ac_compute_dcc_retile_map(struct ac_addrlib *addrlib,
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return map;
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}
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin;
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memcpy(&addrin, in, sizeof(*in));
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
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addrout.size = sizeof(addrout);
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const struct dcc_retile_tile_data *src_tile =
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ac_compute_dcc_retile_tile_indices(addrlib, info, in->bpp,
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in->swizzleMode,
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rb_aligned, pipe_aligned);
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const struct dcc_retile_tile_data *dst_tile =
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ac_compute_dcc_retile_tile_indices(addrlib, info, in->bpp,
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in->swizzleMode, false, false);
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if (!src_tile || !dst_tile) {
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return NULL;
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}
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void *dcc_retile_map = malloc(dcc_retile_map_size);
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if (!dcc_retile_map) {
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@ -133,47 +290,27 @@ static uint32_t *ac_compute_dcc_retile_map(struct ac_addrlib *addrlib,
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}
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unsigned index = 0;
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unsigned w = DIV_ROUND_UP(retile_width, in->compressBlkWidth);
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unsigned h = DIV_ROUND_UP(retile_height, in->compressBlkHeight);
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unsigned src_stride = DIV_ROUND_UP(w, 1u << src_tile->tile_width_log2);
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unsigned dst_stride = DIV_ROUND_UP(w, 1u << dst_tile->tile_width_log2);
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for (unsigned y = 0; y < retile_height; y += in->compressBlkHeight) {
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addrin.y = y;
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for (unsigned y = 0; y < h; ++y) {
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for (unsigned x = 0; x < w; ++x) {
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unsigned src_addr = ac_compute_retile_tile_addr(src_tile, src_stride, x, y);
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unsigned dst_addr = ac_compute_retile_tile_addr(dst_tile, dst_stride, x, y);
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for (unsigned x = 0; x < retile_width; x += in->compressBlkWidth) {
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addrin.x = x;
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/* Compute src DCC address */
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addrin.dccKeyFlags.pipeAligned = pipe_aligned;
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addrin.dccKeyFlags.rbAligned = rb_aligned;
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addrout.addr = 0;
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if (Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout) != ADDR_OK) {
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return NULL;
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if (use_uint16) {
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((uint16_t*)dcc_retile_map)[2 * index] = src_addr;
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((uint16_t*)dcc_retile_map)[2 * index + 1] = dst_addr;
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} else {
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((uint32_t*)dcc_retile_map)[2 * index] = src_addr;
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((uint32_t*)dcc_retile_map)[2 * index + 1] = dst_addr;
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}
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if (use_uint16)
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((uint16_t*)dcc_retile_map)[index * 2] = addrout.addr;
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else
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((uint32_t*)dcc_retile_map)[index * 2] = addrout.addr;
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/* Compute dst DCC address */
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addrin.dccKeyFlags.pipeAligned = 0;
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addrin.dccKeyFlags.rbAligned = 0;
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addrout.addr = 0;
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if (Addr2ComputeDccAddrFromCoord(addrlib->handle, &addrin, &addrout) != ADDR_OK) {
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simple_mtx_unlock(&addrlib->dcc_retile_map_lock);
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return NULL;
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}
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if (use_uint16)
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((uint16_t*)dcc_retile_map)[index * 2 + 1] = addrout.addr;
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else
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((uint32_t*)dcc_retile_map)[index * 2 + 1] = addrout.addr;
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assert(index * 2 + 1 < dcc_retile_num_elements);
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index++;
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++index;
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}
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}
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/* Fill the remaining pairs with the last one (for the compute shader). */
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for (unsigned i = index * 2; i < dcc_retile_num_elements; i++) {
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if (use_uint16)
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@ -276,6 +413,8 @@ struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info,
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simple_mtx_init(&addrlib->dcc_retile_map_lock, mtx_plain);
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addrlib->dcc_retile_maps = _mesa_hash_table_create(NULL, dcc_retile_map_hash_key,
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dcc_retile_map_keys_equal);
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addrlib->dcc_retile_tile_indices = _mesa_hash_table_create(NULL, dcc_retile_tile_hash_key,
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dcc_retile_tile_keys_equal);
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return addrlib;
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}
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@ -284,6 +423,7 @@ void ac_addrlib_destroy(struct ac_addrlib *addrlib)
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AddrDestroy(addrlib->handle);
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simple_mtx_destroy(&addrlib->dcc_retile_map_lock);
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_mesa_hash_table_destroy(addrlib->dcc_retile_maps, dcc_retile_map_free);
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_mesa_hash_table_destroy(addrlib->dcc_retile_tile_indices, dcc_retile_tile_free);
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free(addrlib);
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}
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