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radeonsi: run nir_io_add_const_offset_to_base for TES/TCS as late optimizations

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Other stages don't have indirect indexing, so it's always const.
Doing it here should also remove dead load_const instructions.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
This commit is contained in:
Marek Olšák 2022-01-03 03:40:02 -05:00 • committed by Marge Bot
parent 5a52cfd88b
commit a373b558c0
2 changed files with 8 additions and 3 deletions
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3
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -1477,9 +1477,6 @@ struct nir_shader *si_get_nir_shader(struct si_shader_selector *sel,
if (progress || progress2)
si_nir_late_opts(nir);
/* This must be done again. */
NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in | nir_var_shader_out);
/* This helps LLVM form VMEM clauses and thus get more GPU cache hits.
* 200 is tuned for Viewperf. It should be done last.
*/

8
src/gallium/drivers/radeonsi/si_shader_nir.c
View file

@ -127,6 +127,14 @@ void si_nir_late_opts(nir_shader *nir)
more_late_algebraic = false;
NIR_PASS(more_late_algebraic, nir, nir_opt_algebraic_late);
NIR_PASS_V(nir, nir_opt_constant_folding);
/* We should run this after constant folding for stages that support indirect
* inputs/outputs.
*/
if (nir->options->support_indirect_inputs & BITFIELD_BIT(nir->info.stage) ||
nir->options->support_indirect_outputs & BITFIELD_BIT(nir->info.stage))
NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in | nir_var_shader_out);
NIR_PASS_V(nir, nir_copy_prop);
NIR_PASS_V(nir, nir_opt_dce);
NIR_PASS_V(nir, nir_opt_cse);