mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-21 20:10:14 +01:00
nak/sm20: Add float ops
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34540>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
078ffb860b
commit
a3330f1d46
1 changed files with 353 additions and 0 deletions
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@ -477,6 +477,351 @@ impl SM20Encoder<'_> {
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self.set_dst(14..20, dst);
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self.set_field(26..58, imm_src);
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}
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fn set_rnd_mode(&mut self, range: Range<usize>, rnd_mode: FRndMode) {
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self.set_field(
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range,
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match rnd_mode {
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FRndMode::NearestEven => 0_u8,
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FRndMode::NegInf => 1_u8,
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FRndMode::PosInf => 2_u8,
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FRndMode::Zero => 3_u8,
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},
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);
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}
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fn set_float_cmp_op(&mut self, range: Range<usize>, op: FloatCmpOp) {
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assert!(range.len() == 4);
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self.set_field(
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range,
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match op {
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FloatCmpOp::OrdLt => 0x01_u8,
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FloatCmpOp::OrdEq => 0x02_u8,
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FloatCmpOp::OrdLe => 0x03_u8,
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FloatCmpOp::OrdGt => 0x04_u8,
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FloatCmpOp::OrdNe => 0x05_u8,
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FloatCmpOp::OrdGe => 0x06_u8,
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FloatCmpOp::UnordLt => 0x09_u8,
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FloatCmpOp::UnordEq => 0x0a_u8,
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FloatCmpOp::UnordLe => 0x0b_u8,
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FloatCmpOp::UnordGt => 0x0c_u8,
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FloatCmpOp::UnordNe => 0x0d_u8,
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FloatCmpOp::UnordGe => 0x0e_u8,
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FloatCmpOp::IsNum => 0x07_u8,
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FloatCmpOp::IsNan => 0x08_u8,
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},
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);
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}
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}
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impl SM20Op for OpFAdd {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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let [src0, src1] = &mut self.srcs;
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swap_srcs_if_not_reg(src0, src1, GPR);
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b.copy_alu_src_if_not_reg(src0, GPR, SrcType::F32);
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if src1.as_imm_not_f20().is_some()
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&& (self.saturate || self.rnd_mode == FRndMode::NearestEven)
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{
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b.copy_alu_src(src1, GPR, SrcType::F32);
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}
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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if let Some(imm32) = self.srcs[1].as_imm_not_f20() {
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// Technically the modifier bits for these do work but legalization
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// should fold any modifiers on immediates for us.
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assert!(self.srcs[1].src_mod.is_none());
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e.encode_form_a_imm32(
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0xa,
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Some(&self.dst),
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Some(&self.srcs[0]),
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imm32,
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);
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assert!(self.saturate);
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assert!(self.rnd_mode == FRndMode::NearestEven);
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} else {
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e.encode_form_a(
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SM20Unit::Float,
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0x14,
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Some(&self.dst),
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Some(&self.srcs[0]),
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Some(&self.srcs[1]),
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None,
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);
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e.set_bit(49, self.saturate);
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e.set_rnd_mode(55..57, self.rnd_mode);
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}
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e.set_bit(5, self.ftz);
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e.set_bit(6, self.srcs[1].src_mod.has_fabs());
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e.set_bit(7, self.srcs[0].src_mod.has_fabs());
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e.set_bit(8, self.srcs[1].src_mod.has_fneg());
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e.set_bit(9, self.srcs[0].src_mod.has_fneg());
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}
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}
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impl SM20Op for OpFFma {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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let [src0, src1, src2] = &mut self.srcs;
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swap_srcs_if_not_reg(src0, src1, GPR);
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b.copy_alu_src_if_not_reg(src0, GPR, SrcType::F32);
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b.copy_alu_src_if_fabs(src0, GPR, SrcType::F32);
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b.copy_alu_src_if_fabs(src1, GPR, SrcType::F32);
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b.copy_alu_src_if_fabs(src2, GPR, SrcType::F32);
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if src1.as_imm_not_f20().is_some()
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&& (self.saturate
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|| self.rnd_mode != FRndMode::NearestEven
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|| self.dst.as_reg().is_none()
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|| self.dst.as_reg() != src2.src_ref.as_reg())
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{
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b.copy_alu_src(src1, GPR, SrcType::F32);
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}
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b.copy_alu_src_if_not_reg(src2, GPR, SrcType::F32);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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assert!(!self.srcs[0].src_mod.has_fabs());
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assert!(!self.srcs[1].src_mod.has_fabs());
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assert!(!self.srcs[2].src_mod.has_fabs());
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if let Some(imm32) = self.srcs[1].as_imm_not_f20() {
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// Long immediates are only allowed if src2 == dst.
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assert!(self.dst.as_reg().is_some());
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assert!(self.dst.as_reg() == self.srcs[2].src_ref.as_reg());
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// Technically the modifier bits for these do work but legalization
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// should fold any modifiers on immediates for us.
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assert!(self.srcs[1].src_mod.is_none());
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e.encode_form_a_imm32(
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0x8,
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Some(&self.dst),
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Some(&self.srcs[0]),
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imm32,
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);
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assert!(self.rnd_mode == FRndMode::NearestEven);
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} else {
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e.encode_form_a(
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SM20Unit::Float,
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0xc,
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Some(&self.dst),
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Some(&self.srcs[0]),
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Some(&self.srcs[1]),
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Some(&self.srcs[2]),
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);
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e.set_rnd_mode(55..57, self.rnd_mode);
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}
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e.set_bit(5, self.saturate);
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e.set_bit(6, self.ftz);
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e.set_bit(7, self.dnz);
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e.set_bit(8, self.srcs[2].src_mod.has_fneg());
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let neg0 = self.srcs[0].src_mod.has_fneg();
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let neg1 = self.srcs[1].src_mod.has_fneg();
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e.set_bit(9, neg0 ^ neg1);
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}
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}
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impl SM20Op for OpFMnMx {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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let [src0, src1] = &mut self.srcs;
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swap_srcs_if_not_reg(src0, src1, GPR);
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b.copy_alu_src_if_not_reg(src0, GPR, SrcType::F32);
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b.copy_alu_src_if_f20_overflow(src1, GPR, SrcType::F32);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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e.encode_form_a(
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SM20Unit::Float,
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0x2,
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Some(&self.dst),
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Some(&self.srcs[0]),
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Some(&self.srcs[1]),
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None,
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);
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e.set_bit(5, self.ftz);
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e.set_bit(6, self.srcs[1].src_mod.has_fabs());
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e.set_bit(7, self.srcs[0].src_mod.has_fabs());
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e.set_bit(8, self.srcs[1].src_mod.has_fneg());
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e.set_bit(9, self.srcs[0].src_mod.has_fneg());
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e.set_pred_src(49..53, self.min);
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}
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}
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impl SM20Op for OpFMul {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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let [src0, src1] = &mut self.srcs;
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swap_srcs_if_not_reg(src0, src1, GPR);
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b.copy_alu_src_if_not_reg(src0, GPR, SrcType::F32);
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b.copy_alu_src_if_fabs(src0, GPR, SrcType::F32);
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b.copy_alu_src_if_fabs(src1, GPR, SrcType::F32);
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if src1.as_imm_not_f20().is_some()
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&& self.rnd_mode != FRndMode::NearestEven
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{
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b.copy_alu_src(src1, GPR, SrcType::F32);
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}
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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assert!(!self.srcs[0].src_mod.has_fabs());
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assert!(!self.srcs[1].src_mod.has_fabs());
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if let Some(mut imm32) = self.srcs[1].as_imm_not_f20() {
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// Technically the modifier bits for these do work but legalization
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// should fold any modifiers on immediates for us.
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assert!(self.srcs[1].src_mod.is_none());
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// We don't, however, have a modifier for src0. Just flip the
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// immediate in that case.
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if self.srcs[0].src_mod.has_fneg() {
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imm32 ^= 0x80000000;
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}
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e.encode_form_a_imm32(
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0xc,
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Some(&self.dst),
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Some(&self.srcs[0]),
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imm32,
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);
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assert!(self.rnd_mode == FRndMode::NearestEven);
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} else {
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e.encode_form_a(
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SM20Unit::Float,
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0x16,
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Some(&self.dst),
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Some(&self.srcs[0]),
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Some(&self.srcs[1]),
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None,
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);
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e.set_rnd_mode(55..57, self.rnd_mode);
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let neg0 = self.srcs[0].src_mod.has_fneg();
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let neg1 = self.srcs[1].src_mod.has_fneg();
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e.set_bit(25, neg0 ^ neg1);
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}
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e.set_bit(5, self.saturate);
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e.set_bit(6, self.ftz);
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e.set_bit(7, self.dnz);
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}
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}
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impl SM20Op for OpRro {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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b.copy_alu_src_if_f20_overflow(&mut self.src, GPR, SrcType::F32);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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e.encode_form_b(SM20Unit::Float, 0x18, self.dst, self.src);
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e.set_field(
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5..6,
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match self.op {
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RroOp::SinCos => 0u8,
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RroOp::Exp2 => 1u8,
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},
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);
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e.set_bit(6, self.src.src_mod.has_fabs());
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e.set_bit(8, self.src.src_mod.has_fneg());
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}
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}
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impl SM20Op for OpMuFu {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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b.copy_alu_src_if_not_reg(&mut self.src, GPR, SrcType::I32);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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e.set_opcode(SM20Unit::Float, 0x32);
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e.set_dst(14..20, self.dst);
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e.set_reg_src_ref(20..26, &self.src.src_ref);
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e.set_bit(5, false); // .sat
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e.set_bit(6, self.src.src_mod.has_fabs());
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e.set_bit(8, self.src.src_mod.has_fneg());
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e.set_field(
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26..30,
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match self.op {
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MuFuOp::Cos => 0_u8,
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MuFuOp::Sin => 1_u8,
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MuFuOp::Exp2 => 2_u8,
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MuFuOp::Log2 => 3_u8,
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MuFuOp::Rcp => 4_u8,
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MuFuOp::Rsq => 5_u8,
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MuFuOp::Rcp64H => 6_u8,
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MuFuOp::Rsq64H => 7_u8,
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_ => panic!("mufu{} not supported on SM20", self.op),
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},
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);
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}
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}
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impl SM20Op for OpFSet {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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let [src0, src1] = &mut self.srcs;
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if swap_srcs_if_not_reg(src0, src1, GPR) {
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self.cmp_op = self.cmp_op.flip();
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}
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b.copy_alu_src_if_not_reg(src0, GPR, SrcType::ALU);
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b.copy_alu_src_if_f20_overflow(src1, GPR, SrcType::ALU);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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e.encode_form_a(
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SM20Unit::Float,
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0x6,
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Some(&self.dst),
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Some(&self.srcs[0]),
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Some(&self.srcs[1]),
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None,
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);
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e.set_bit(5, self.ftz);
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e.set_bit(6, self.srcs[1].src_mod.has_fabs());
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e.set_bit(7, self.srcs[0].src_mod.has_fabs());
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e.set_bit(8, self.srcs[1].src_mod.has_fneg());
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e.set_bit(9, self.srcs[0].src_mod.has_fneg());
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e.set_float_cmp_op(55..59, self.cmp_op);
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}
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}
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impl SM20Op for OpFSetP {
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fn legalize(&mut self, b: &mut LegalizeBuilder) {
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use RegFile::GPR;
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let [src0, src1] = &mut self.srcs;
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if swap_srcs_if_not_reg(src0, src1, GPR) {
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self.cmp_op = self.cmp_op.flip();
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}
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b.copy_alu_src_if_not_reg(src0, GPR, SrcType::ALU);
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b.copy_alu_src_if_f20_overflow(src1, GPR, SrcType::ALU);
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}
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fn encode(&self, e: &mut SM20Encoder<'_>) {
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e.encode_form_a(
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SM20Unit::Float,
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0x8,
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None,
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Some(&self.srcs[0]),
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Some(&self.srcs[1]),
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None,
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);
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e.set_bit(6, self.srcs[1].src_mod.has_fabs());
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e.set_bit(7, self.srcs[0].src_mod.has_fabs());
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e.set_bit(8, self.srcs[1].src_mod.has_fneg());
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e.set_bit(9, self.srcs[0].src_mod.has_fneg());
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e.set_pred_dst(14..17, Dst::None);
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e.set_pred_dst(17..20, self.dst);
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e.set_pred_src(49..53, self.accum);
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e.set_pred_set_op(53..55, self.set_op);
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e.set_float_cmp_op(55..59, self.cmp_op);
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e.set_bit(59, self.ftz);
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}
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}
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impl SM20Op for OpFlo {
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@ -1071,6 +1416,14 @@ impl SM20Op for OpS2R {
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macro_rules! as_sm20_op_match {
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($op: expr) => {
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match $op {
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Op::FAdd(op) => op,
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Op::FFma(op) => op,
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Op::FMnMx(op) => op,
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Op::FMul(op) => op,
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Op::Rro(op) => op,
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Op::MuFu(op) => op,
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Op::FSet(op) => op,
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Op::FSetP(op) => op,
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Op::Flo(op) => op,
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Op::IAdd2(op) => op,
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Op::IAdd2X(op) => op,
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