fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-21 15:50:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Revert "intel/fs: Use a pure vertical stride for large register strides"

Browse source 
This reverts commit e8c9e65185.

With the actual bug fixed (by commit 6ac2d16901), this is not
necessary. I'm doubtful of its correctness in any case.
This commit is contained in:
Matt Turner 2017-11-14 11:24:08 -08:00
parent 6ac2d16901
commit a31d038208
1 changed files with 3 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/intel/compiler/brw_fs_generator.cpp
View file

@ -90,19 +90,9 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
* different execution size when the number of components
* written to each destination GRF is not the same.
*/
if (reg->stride > 4) {
/* For registers with an exceptionally large stride, we use a
* width of 1 and only use the vertical stride. This only works
* for sources since destinations require hstride == 1.
*/
assert(reg != &inst->dst);
brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, reg->stride, 1, 0);
} else {
const unsigned width = MIN2(reg_width, phys_width);
brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
}
const unsigned width = MIN2(reg_width, phys_width);
brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
if (devinfo->gen == 7 && !devinfo->is_haswell) {
/* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):